CN104537999A - Panel internal interface capable of being flexibly configured based on system complexity and protocol thereof - Google Patents
Panel internal interface capable of being flexibly configured based on system complexity and protocol thereof Download PDFInfo
- Publication number
- CN104537999A CN104537999A CN201510007305.XA CN201510007305A CN104537999A CN 104537999 A CN104537999 A CN 104537999A CN 201510007305 A CN201510007305 A CN 201510007305A CN 104537999 A CN104537999 A CN 104537999A
- Authority
- CN
- China
- Prior art keywords
- chip
- source
- data
- source drive
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention relates to a panel internal interface capable of being flexibly configured based on the system complexity and a protocol thereof. By means of a display panel driving system interface configuration method and a data transmission method, an end-to-end connection mode and a one-to-two connection mode can be formed through flexible configuration according to system requirements on the basis of not changing the design of a timing controller and a source driving chip, so that specific requirements of different panel systems are met. On the condition that the end-to-end mode meets the bandwidth requirement and the problem that system connection is too complex when many connecting lines are arranged is solved, the end-to-end connection is adopted. When the number of source driving chips in the system is too large, the problems that the number of connecting lines is too large and power consumption is higher will be caused if the end-to-end mode is adopted, the one-to-two mode can be adopted at the moment, the number of the connecting lines can be reduced by one half, and the complexity degree of the panel system is greatly lowered.
Description
Technical field
The present invention relates to flat display field, particularly the board driving mchanism of flat panel display systems and the method for data transmission.
Background technology
Existing panel display board system drive principle as shown in Figure 1.Apparatus for processing of video signals is (as multimedia processor, image processor GPU etc.) by certain interface (as standardized digital signal interface, standard analog signal interface, LVDS interface, eDP interface, v-by-one interface, DVI interface) by data-signal, synchronizing signal, and clock signal (or this three being embedded in a transmission channel) is sent to the timing control circuit of Display panel driver module, the major function of timing control circuit is image enhaucament, colourity controls and sequential control, it carries out serializing process to the received signal, the video flowing of often going is resolved into the video packets passing to each source drive chip, and be transferred to source drive chip according to predefined interface protocol, digital video signal is formed the simulating signal being used for driving data line by source drive chip, for driving source electrode.Timing control circuit chip generates the signal being suitable for grid drive chip simultaneously, and grid line driving circuit is used for driving grid, produces sweep signal.Source drive chip output gray level voltage signal, grid drive and produce line scan signals, both time cooperation thus drive each pixel cell.
Fig. 2 shows timing controller (TCON in prior art, Timing Controller) and source drive chip (driver) between interface configuration mode, wherein Fig. 2 (a) interface shape (as mini-LVDS interface) schematic diagram that is one-to-many, it should be noted that the single line in schematic diagram means that the combination of one group of difference and single-ended signal line (gives more detailed schematic diagram in Fig. 3, be used for transmitting data as mini-LVDS interface standard comprises 3 to 6 pairs of differential signal lines, a pair differential signal line is used for transfer clock, two single-ended signal lines are used for transmission of control signals), there is many shortcomings in the application in it, as many in Seize ACK message passage, EMI poor compatibility, the end-to-end interface shape of the embedded clock technology of the employing therefore described in Fig. 2 (b) more occurs in display panel driver module design in recent years, it should be noted that the single line in Fig. 2 means that it is relative to the interface configuration shown in Fig. 2 (a) for a pair differential signal line (because clock information and other control informations are all embedded in differential signal by packets of information and coding techniques), transport tape is roomy, active channel is few, and have good EMI performance.But along with the fast development of full HD even 4k and 8k large-size screen monitors display panel in recent years, end-to-end interface configuration causes connecting line too much because the source drive chip of required control is more and more, the designing requirement of the narrow frame of panel cannot be met, and too much end-to-end interface transtation mission circuit makes power consumption increase obviously, therefore existing interface configuration mode can not meet the requirement of current technological development trend.
Display panel driver module generally includes: timing controller 300 (TCON, Timing Controller), it is for realizing timing control circuit in Fig. 1, the source drive chip 301 (driver) of multiple cascade, it is for realizing data line drive circuit in Fig. 1 (source driving), line detailed view (such as mini-LVDS interface between them has been shown in Fig. 3, for adopting the interface of the connected mode of traditional one-to-many), timing controller 300, it is by the data-signal of certain interface from apparatus for processing of video signals, and under the control of predetermined clock signal outputting data signals to data line drive circuit, data line drive circuit comprises multiple source drive chip 301, receives the data-signal from timing control circuit, and exports suitable analog voltage to data line, thus drives each pixel cell of panel.Timing controller 300 produces the control signal (or comprising clock signal) for controlling source drive chip 301, and transmitted by control signal bus 302, and by pixel data (R0, G0, B0, RE, GE, BE) send source drive chip 301 to by three odd data buses, 304, three even numbers 306.
Summary of the invention
The present invention proposes a kind of interface configuration and data transmission method of new display panel driving system, can according to the requirement of system complexity flexible configuration, improve existing interface allocation method exist multiple problems.
The interface allocation method of the display panel driving system that the present invention proposes, can on the basis of design not changing timing controller and source drive chip, the connection mode of end-to-end link pattern and a pair two is become, to meet the particular requirement of different panels system according to system requirements flexible configuration.When end to end system can meet bandwidth requirement, and transmission line number can not cause because connecting line too much makes system connect too under complicated situation, adopts end-to-end connected mode; When in system, source drive chip number is too much, adopt end-to-end mode that connecting line can be caused too much, during the more high some problem of power consumption, the mode that can be configured to a pair two just can reduce the connecting line of half, greatly reduce the complexity of panel system, decrease the transmitting terminal power consumption of half accordingly.
The present invention proposes a kind of data transmission method and host-host protocol of new display panel driving system, its interface allocation method proposed with the present invention coordinates, to realize object of the present invention and multiple advantage.
For achieving the above object and advantage, the present invention proposes a kind of drive unit of display panel, for driving a plurality of data lines of display panel, this device comprises: a timing control circuit and a data line drive circuit, the input data that this timing control circuit provides for receiving outside source, and outputed signal to data line drive circuit by multiple output port, this data line drive circuit is made up of multiple source drive chip cascade, each source drive chip receives the signal from timing control circuit by input port, and export analog voltage signal to corresponding data line, thus driving display panel, the port arrangement mode of timing control circuit and source drive chip can be selected arbitrarily between end-to-end link pattern or a pair two connection modes.
In end-to-end link pattern, each output port of timing controller is corresponding with source drive chip to be connected; In the connection mode of a pair two, each output port of timing controller is corresponding with two source drive chips to be connected.
The drive unit of the display panel that the present invention proposes, in a pair two connection modes, each output port of timing control circuit and master, connect from the input port of two source drive chips, in the video stream data host-host protocol that timing control circuit sends to source drive chip, each video packets of data is divided into main video data bag by the specific bag that controls, from video packets of data two parts, wherein main video data bag drives master chip to receive by source, received from chip from video packets of data by source driving, namely each source drive chip receives only one's own video packets of data, and ignore not one's own video packets of data.
The drive unit of the display panel that the present invention proposes, timing control circuit comprises a control bag to the video stream signal that source drive chip sends, this control bag arranges an output mode discrimination bit and a source drive chip discrimination bit, this output mode discrimination bit is configured to end-to-end link pattern or a pair two connection modes for controlling source drive chip, this source drive chip identification is located in a pair two connection modes, and being used for identifying this control bag video packets of data is below driven master chip to receive by source or driven by source to receive from chip.
Accompanying drawing explanation
Fig. 1 shows the theory diagram of existing display panel driving system.
Fig. 2 shows the interface configuration mode structure of existing display panel driving system.
The conventional bus that Fig. 3 shows between timing control circuit and data line drive circuit connects detailed view.
Fig. 4 shows display panel driving system a pair two interface configuration connection diagrams that the present invention proposes.
Fig. 5 shows the data transmission format between timing control circuit in the embodiment that the present invention proposes and source drive chip in end-to-end interface configuration mode.
Fig. 6 shows the data definition of the control bag that the data frame packet in the embodiment of the present invention's proposition contains.
Fig. 7 shows the data transmission format in a pair two interface configuration modes of the present invention's proposition between timing control circuit and source drive chip.
Embodiment
Embodiments of the invention are described in detail below by way of with reference to accompanying drawing 4-7.
In the display panel driver module design that the present invention proposes, multiple source drive chips of timing control circuit and data line drive circuit can be configured to suitable connection mode according to the condition of panel embody rule.The specific function pin configuration of each source drive chip (driver) has inner pull-up circuit.In end-to-end link pattern, this function pin configuration is high level by inner pull-up circuit by the corresponding configuration pin of all source drive chips; And in the connection mode of a pair two, as shown in Figure 4, each output port due to timing control circuit is corresponding with two source drive chips to be connected, wherein said two source drive chips source that is respectively drives master chip (Master) and source to drive from chip (Slave), source drive from chip by its corresponding configuration pin by the pull-down circuit of chip pin outside by drop-down for this function pin be low level (Pull L), thus to indicate this chip be that source driving is from chip.Source drives master chip to be still then high level by the inside pull-up circuit of its corresponding configuration pin by this function pin configuration.Therefore, display panel driver module can according to the concrete property flexible configuration port connection mode of display panel, do not needing to redesign on the basis of timing control circuit chip and data line drive circuit chip, namely retain on the basis of integrated circuit structure of timing control circuit chip and source driving circuit chip, switch in the connection mode of end-to-end link pattern and a pair two, realize flexible configuration.
When multiple source drive chips of timing control circuit and data line drive circuit carry out video data transmission, each frame of video of video stream data comprises identifier, controls bag and video packets of data.Fig. 5 illustrates the data transmission format in end-to-end link pattern.In Fig. 5, K1 is a unique identifier, bag 1 (CTRL1) and video packets of data initial is controlled to indicate, identifier K2 identifies the end of the video packets of data of current line, identifier K4 identifies the end of current video frame, namely the corresponding identifier of last 1 row video packets of data becomes K4 from K2, and to indicate the last 1 row data end of transmission of this frame of video, present frame terminates.Follow another after K4 and control bag 2 (CTRL2).When adopting end-to-end connection mode, each source drive chip can individual reception video packets of data and control bag, and vision signal is converted to corresponding analog voltage and exports data line to, thus drives each pixel cell of liquid crystal panel.
Fig. 6 shows in frame of video the data definition controlling to wrap, controlling bag CTRL1 is 8, the i.e. data of 1 byte, b [0] is defined as FSYNC position, be defined as frame and start flag, be preset as 0, then 1 is set to when frame of video starts, b [1] is POL position, its voltage inverted pattern exported for defining SD, be preset as L, b [2] is MDEN position, be output mode discrimination bit, b [3] is MDID position, i.e. source drive chip discrimination bit, the source drive chip identification of output mode is connected for a pair two, b [4] is BKDU position, it is defined as vertical blanking flag, preset value is L, b [5]-b [7] is for retaining position.When end-to-end pattern, b [2] is 0, be namely positioned at low level L, and when a pair two connection modes, b [2] is 1, is namely positioned at high-order H; When a pair two connection modes are configured to enable, b [3] is source drive chip discrimination bit, when b [3] is 1, illustrate this control bag heel with video packets of data (Video line (slice per SDIC)) belong to source drive master chip (Master), when b [3] is 0, illustrate this control bag heel with video packets of data (Video line (slice per SDIC)) belong to source drive from chip (Slave).
When system works is at a pair two connection modes, the signalling channel that timing controller exports is compared to the output signal channel of end-to-end link pattern, its number can be reduced to half, but also doubles the requirement of transmission bandwidth, this is because the time of video line transmission and display is fixing.
When system works is at a pair two connection modes, as shown in Figure 7, video packets of data is still from identifier K1 with controlling bag CTRL1, but video packets of data is separated into two pieces, two pieces of sub video data bags (Video SD#master and Video SD#slave) are separated by another one identifier K1 and control bag CTRL1, in control bag CTRL1 before master chip sub video data bag, output mode discrimination bit b [2] is positioned at high-order H, and source drive chip discrimination bit b [3] is also positioned at high-order H; And from the control bag CTRL1 before chip sub video data bag, output mode discrimination bit b [2] is positioned at high-order H, source drive chip discrimination bit b [3] is positioned at low level L, thus control master chip sub video data bag (VideoSD#master) by the reception of source driving master chip, received from chip from chip sub video data bag (Video SD#slave) by source driving.Therefore, source drives master chip and source to drive and only need to receive from chip and to store by controlling bag CTRL] the respective independently video packets of data that indicates, and ignore not one's own video packets of data.
Although above embodiment describes the present invention in detail, the aforementioned each side that is described in is illustrative and not restrictive, and should be understood that and can design other modifications and variations multiple.
Claims (4)
1. a drive unit for display panel, for driving a plurality of data lines of display panel, this device comprises:
A timing control circuit and a data line drive circuit, the input data that this timing control circuit provides for receiving outside source, and outputed signal to data line drive circuit by multiple output port, this data line drive circuit is made up of multiple source drive chip cascade, each source drive chip receives the described output signal from timing control circuit by input port, and export analog voltage signal to corresponding data line, thus drive display panel
It is characterized in that: the port arrangement mode of timing control circuit and source drive chip can be selected arbitrarily between end-to-end link pattern or a pair two connection modes, in end-to-end link pattern, each output port of timing control circuit is corresponding with the input port of a source drive chip to be connected; In the connection mode of a pair two, each output port of timing control circuit is corresponding with the input port of two source drive chips to be connected.
2. the drive unit of display panel as claimed in claim 1, in a pair two connection modes, the defeated port of each described output of timing control circuit is connected with the input port of master and slave two source drive chips, in the video stream data signal that timing control circuit sends to source drive chip, each video packets of data is divided into main video data bag, from video packets of data two parts by the specific bag that controls, wherein main video data bag drives master chip to receive by source, is received from video packets of data by source driving from chip.
3. the drive unit of display panel as claimed in claim 2, in the frequency flow data signal that timing control circuit sends to source drive chip, comprise a control bag, this control bag arranges an output mode discrimination bit and a source drive chip discrimination bit, this output mode discrimination bit is configured to end-to-end link pattern or a pair two connection modes for controlling source drive chip, this source drive chip discrimination bit is used in a pair two connection modes, and being used for identifying this control bag video packets of data is below driven master chip to receive by source or driven by source to receive from chip.
4. the drive unit of display panel as claimed in claim 2 or claim 3, the specific function pin of described source drive chip possesses inner pull-up function, namely described source drives drop-down by outside pull-down circuit from this specific function pin of chip is low level, to identify that this source drive chip is for source driving is from chip, described source drives this specific function pin of master chip to be only set to high level by inner pull-up, to identify that this source drive chip drives master chip for source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510007305.XA CN104537999B (en) | 2015-01-08 | 2015-01-08 | A kind of panel itself interface and its agreement that can be according to system complexity flexible configuration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510007305.XA CN104537999B (en) | 2015-01-08 | 2015-01-08 | A kind of panel itself interface and its agreement that can be according to system complexity flexible configuration |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104537999A true CN104537999A (en) | 2015-04-22 |
| CN104537999B CN104537999B (en) | 2017-08-08 |
Family
ID=52853516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510007305.XA Active CN104537999B (en) | 2015-01-08 | 2015-01-08 | A kind of panel itself interface and its agreement that can be according to system complexity flexible configuration |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104537999B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104835472A (en) * | 2015-05-28 | 2015-08-12 | 合肥京东方光电科技有限公司 | Drive chip used for driving display panel, display device and drive control method |
| CN106331851A (en) * | 2016-08-31 | 2017-01-11 | 深圳市华星光电技术有限公司 | Liquid crystal display television and data processing device thereof |
| CN108880551A (en) * | 2018-07-02 | 2018-11-23 | 京东方科技集团股份有限公司 | Motherboard circuit, display module and display device |
| CN109493786A (en) * | 2018-12-29 | 2019-03-19 | 武汉华星光电技术有限公司 | Data output device, display narrow frame module, display and electronic equipment |
| CN115240584A (en) * | 2022-05-30 | 2022-10-25 | 北京奕斯伟计算技术股份有限公司 | Time schedule controller, source electrode driving chip, driving circuit and driving control method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1487493A (en) * | 2002-07-19 | 2004-04-07 | 三星电子株式会社 | Liquid crystal display device including master-slave structure data driving device and driving method thereof |
| US20070195048A1 (en) * | 2006-01-31 | 2007-08-23 | Samsung Electronics Co. Ltd. | Device for adjusting transmission signal level based on channel loading |
| CN100377200C (en) * | 2004-02-04 | 2008-03-26 | 京东方显示器科技公司 | Driving circuit of liquid crystal display |
| CN101273395A (en) * | 2005-09-23 | 2008-09-24 | 安纳帕斯股份有限公司 | Display, column driver integrated circuit, and multi-level detector, and multi-level detection method |
| US20090284509A1 (en) * | 2008-05-19 | 2009-11-19 | Weon-Jun Choe | Display device and clock embedding method |
| KR20110111812A (en) * | 2010-04-05 | 2011-10-12 | 주식회사 실리콘웍스 | Display driving system using single level signaling with embedded clock signal |
| KR101322119B1 (en) * | 2008-12-15 | 2013-10-25 | 엘지디스플레이 주식회사 | Liquid crystal display |
| CN103680374A (en) * | 2012-09-26 | 2014-03-26 | 联咏科技股份有限公司 | Panel display device |
| CN103903546A (en) * | 2012-12-26 | 2014-07-02 | 乐金显示有限公司 | Image display device and method for driving the same |
-
2015
- 2015-01-08 CN CN201510007305.XA patent/CN104537999B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1487493A (en) * | 2002-07-19 | 2004-04-07 | 三星电子株式会社 | Liquid crystal display device including master-slave structure data driving device and driving method thereof |
| CN100377200C (en) * | 2004-02-04 | 2008-03-26 | 京东方显示器科技公司 | Driving circuit of liquid crystal display |
| CN101273395A (en) * | 2005-09-23 | 2008-09-24 | 安纳帕斯股份有限公司 | Display, column driver integrated circuit, and multi-level detector, and multi-level detection method |
| US20070195048A1 (en) * | 2006-01-31 | 2007-08-23 | Samsung Electronics Co. Ltd. | Device for adjusting transmission signal level based on channel loading |
| US20090284509A1 (en) * | 2008-05-19 | 2009-11-19 | Weon-Jun Choe | Display device and clock embedding method |
| KR101322119B1 (en) * | 2008-12-15 | 2013-10-25 | 엘지디스플레이 주식회사 | Liquid crystal display |
| KR20110111812A (en) * | 2010-04-05 | 2011-10-12 | 주식회사 실리콘웍스 | Display driving system using single level signaling with embedded clock signal |
| CN103680374A (en) * | 2012-09-26 | 2014-03-26 | 联咏科技股份有限公司 | Panel display device |
| CN103903546A (en) * | 2012-12-26 | 2014-07-02 | 乐金显示有限公司 | Image display device and method for driving the same |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104835472A (en) * | 2015-05-28 | 2015-08-12 | 合肥京东方光电科技有限公司 | Drive chip used for driving display panel, display device and drive control method |
| CN104835472B (en) * | 2015-05-28 | 2018-01-02 | 合肥京东方光电科技有限公司 | For driving driving chip, display device and the drive control method of display panel |
| US10304398B2 (en) | 2015-05-28 | 2019-05-28 | Boe Technology Group Co., Ltd. | Driver integrated circuit for driving display panel, display device and method for driving driver integrated circuit capable of providing different current intensities to different length transmission wires |
| CN106331851A (en) * | 2016-08-31 | 2017-01-11 | 深圳市华星光电技术有限公司 | Liquid crystal display television and data processing device thereof |
| CN106331851B (en) * | 2016-08-31 | 2020-01-17 | 深圳市华星光电技术有限公司 | Liquid crystal television and data processing device thereof |
| CN108880551A (en) * | 2018-07-02 | 2018-11-23 | 京东方科技集团股份有限公司 | Motherboard circuit, display module and display device |
| CN108880551B (en) * | 2018-07-02 | 2022-05-24 | 京东方科技集团股份有限公司 | Mainboard circuit, display module assembly and display device |
| CN109493786A (en) * | 2018-12-29 | 2019-03-19 | 武汉华星光电技术有限公司 | Data output device, display narrow frame module, display and electronic equipment |
| WO2020133775A1 (en) * | 2018-12-29 | 2020-07-02 | 武汉华星光电技术有限公司 | Data output apparatus, display narrow bezel module, display, and electronic device |
| CN115240584A (en) * | 2022-05-30 | 2022-10-25 | 北京奕斯伟计算技术股份有限公司 | Time schedule controller, source electrode driving chip, driving circuit and driving control method |
| CN115240584B (en) * | 2022-05-30 | 2023-11-28 | 北京奕斯伟计算技术股份有限公司 | Time sequence controller, source electrode driving chip, driving circuit and driving control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104537999B (en) | 2017-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104537999A (en) | Panel internal interface capable of being flexibly configured based on system complexity and protocol thereof | |
| US9015357B2 (en) | Method and device for providing high speed data transmission with video data | |
| JP5670916B2 (en) | Multi-monitor display | |
| US10447964B2 (en) | Interface conversion circuit, display panel driving method and display apparatus | |
| CN103544130B (en) | A kind of windows display equipment and display packing | |
| US9564077B2 (en) | Display apparatus, driving chip set, and operating method thereof | |
| CN101261824B (en) | Display apparatus for displaying input video through various connector | |
| CN103428532B (en) | Multimedia signal transmission system, switching device and transmission method | |
| CN103957374A (en) | 8K ultrahigh-definition display system based on DP interface | |
| CN107872627B (en) | Video matrix control apparatus | |
| CN101093654A (en) | Output driving device of display controlling and method | |
| KR20180072790A (en) | Multi-channel display interface signal generation system of the shared protocol layer | |
| CN114267293B (en) | Display device and display method thereof | |
| CN100386789C (en) | Display panel | |
| US11134297B2 (en) | Video input port | |
| CN101894519B (en) | Data conversion device, data conversion method and data conversion system | |
| CN212381303U (en) | Device for realizing double-link DVI (digital video interactive) based on FPGA (field programmable Gate array) | |
| CN211239967U (en) | Display controller, display control system and LED display system | |
| CN204305204U (en) | A kind of CameraLink-DVI video converter | |
| CN208063339U (en) | A kind of vision signal parser circuitry, vision signal resolver and sending card | |
| CN202488592U (en) | Real-time high definition video transmitter | |
| CN202930010U (en) | Two-sided display control circuit and two-sided display television | |
| CN105282457B (en) | A kind of splicing apparatus and its joining method of non-standard resolution display | |
| TW202110169A (en) | Circuit and method for use in a first display device to facilitate communication with a second display device, and display communication system | |
| CN111010594B (en) | Video signal conversion method and conversion device for display equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 100088 Beijing city Haidian District North Third Ring Road No. 31, No. 4 Building 13 layer (Taisite building) Applicant after: BEIJING CHIPONE NORTH TECHNOLOGY CO., LTD. Address before: 100088 Beijing city Haidian District North Third Ring Road No. 31, No. 4 Building 13 layer (Taisite building) Applicant before: Beijing Jichuang Northern Technology Co.,Ltd. |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |