CN104506195B - A kind of resolution ratio can configure gradual approaching A/D converter - Google Patents
A kind of resolution ratio can configure gradual approaching A/D converter Download PDFInfo
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- CN104506195B CN104506195B CN201410822361.4A CN201410822361A CN104506195B CN 104506195 B CN104506195 B CN 104506195B CN 201410822361 A CN201410822361 A CN 201410822361A CN 104506195 B CN104506195 B CN 104506195B
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Abstract
The invention discloses a kind of resolution ratio can configure gradual approaching A/D converter, including capacitor type digital analog converter, comparator, resolution ratio can configure Approach by inchmeal control logic circuit and clock circuit.Compared with the existing resolution ratio of gradual approaching A/D converter can configure technical solution, the present invention need not be inserted into switch to configure its digit in capacitor type digital analog converter, and directly the resolution ratio of analog-digital converter is configured on Approach by inchmeal control logic algorithm；Because avoiding the switch that can configure in capacitor array, the present invention is convenient and simple in the placement-and-routing of domain, substantially reduces the parasitic capacitance and dead resistance introduced between the key nodes such as capacitance top crown, bottom crown；Compared with prior art is in performance, the invention enables gradual approaching A/D converter normal level is all dropped under each resolution model in the bottom of making an uproar of output signal spectrum, harmonic wave is eliminated, and the dynamic characteristic and static characteristic of analog-digital converter are obtained for significant raising.
Description
Technical field
The present invention relates to analogue-to-digital converters field, and in particular to can configure gradual approaching to a kind of resolution ratio
Number converter.
Background technology
With the continuous progress of integrated circuit technique, the ability of digital circuit processing signal is more and more stronger.But in reality
The world, the signal that integrated circuit participates in processing is largely analog signal, for example, the wireless signal that receives of antenna, it is necessary to by
After low-noise amplifier, frequency mixer, wave filter etc., it is also necessary to by analog-digital converter (ADC, analog-to-digital
Converter digital circuit processing) can just be given.Optical signal, voice signal, temperature signal, pressure signal are after sensor
The analog voltage signal of generation, is equally also required to just give digital circuit processing by ADC conversions.ADC is simulated as connection
Signal acts on self-evident to the bridge of digital signal.Different products applications be to the resolution requirement of ADC it is different,
Therefore the ADC that resolution ratio can configure seems more and more important.
Fig. 1 is that existing resolution ratio can configure gradual approaching A/D converter (Successive Approximation
Register Analog-to-Digital Converter, SAR ADC) the capacitor type number that can configure of technical solution intermediate-resolution
The structure chart of mode converter (Digital-to-Analog Converter, DAC).Existing resolution ratio can configure SAR ADC and pass through
Insertion switch configures DAC digits in capacitance DAC arrays, and reaches together point with corresponding Approach by inchmeal control logic circuit
The purpose that resolution can configure.Insertion switch SW in 8- bits, 9- bits, 10- bits, 11- bits, 12- bit SAR ADC
[15], SW [14], SW [13], SW [12], SW [11] are respectively 00001,00011,00111,01111,11111, switch SW
[25], SW [24], SW [23], SW [22], SW [21] signal values and switch SW [15], SW [14], SW [13], SW [12], SW
[11] signal value is just the same.Fig. 2 is that existing resolution ratio can configure Approach by inchmeal control logic circuit in SAR ADC technical solutions
State machine redirect figure, the State Transferring of Approach by inchmeal control logic circuit is as follows：0000：Hold mode, capacitance DAC arrays
The bottom crown of anode high position section capacitor array 112 and negative terminal low level section capacitor array 121 connects common-mode voltage；Comparator first time ratio
Compared with.0001：C is adjudicated according to the result of laststate comparator1127And C1227Positive negative reference voltage situation is connect, and exports modulus and turns
MSB (highest significant position, Most Significant Bit) position D [11] of parallel operation；Comparator compares for the second time.0010：According to
Laststate comparator results adjudicate C1126And C1226Positive negative reference voltage situation is connect, and exports the MSB-1 positions D of analog-digital converter
[10]；Comparator third time compares.0011：C is adjudicated according to laststate comparator results1125And C1225Connect positive negative reference voltage
Situation, and export the MSB-2 positions D [9] of analog-digital converter；The 4th comparison of comparator.0100：According to laststate comparator knot
Fruit adjudicates C1124And C1224Positive negative reference voltage situation is connect, and exports the MSB-3 positions D [8] of analog-digital converter；Comparator the 5th time
Compare.0101：C is adjudicated according to laststate comparator results1123And C1223Positive negative reference voltage situation is connect, and exports modulus and turns
The MSB-4 positions D [7] of parallel operation；The 6th comparison of comparator.0110：C is adjudicated according to laststate comparator results1122And C1222Connect
Positive negative reference voltage situation, and export the MSB-5 positions D [6] of analog-digital converter；The 7th comparison of comparator.According to SAR ADC's
Different resolution jumps to different states.12- bits, 11- bits, 10 bits, 9 bits, next state point of 8 bits
Wei 0111,1000,1001,1010,1011.0111：C is adjudicated according to laststate comparator results1115And C1215Connect positive and negative ginseng
Voltage condition is examined, and exports the MSB-6 positions D [5] of analog-digital converter.1000：C is adjudicated according to laststate comparator results1114
And C1214Positive negative reference voltage situation is connect, and exports the MSB-7 positions D [4] of analog-digital converter.1001：Compared according to laststate
Device result adjudicates C1113And C1213Positive negative reference voltage situation is connect, and exports the MSB-8 positions D [3] of analog-digital converter.1010：According to
Laststate comparator results adjudicate C1112And C1212Positive negative reference voltage situation is connect, and exports the MSB-9 positions D of analog-digital converter
[2].1011：C is adjudicated according to laststate comparator results1111And C1211Positive negative reference voltage situation is connect, and exports analog-to-digital conversion
The MSB-10 positions D [1] of device.1100：The MSB-11 positions D [0] of ADC is exported according to laststate comparator results, is adopted into next time
Sample stage, NextState 0000.
But the analog switch of insertion is not preferable in actual circuit, there are conducting resistance and parasitic capacitance.
In high-precision SAR ADC, existing resolution ratio, which can configure scheme, can seriously affect the performance of analog-digital converter.
The content of the invention
It is an object of the invention to propose that a kind of resolution ratio can configure SAR ADC, the present invention can solve existing resolution ratio
The problem of performance of SAR ADC is low in configurable scheme.
For this purpose, the present invention uses following technical scheme：
A kind of resolution ratio can configure gradual approaching A/D converter, including capacitor type digital analog converter, comparator, resolution
Rate can configure Approach by inchmeal control logic circuit and clock circuit,
The output terminal of the capacitor type digital analog converter is connected with the input terminal of the comparator, the output of the comparator
End can configure the input terminal of Approach by inchmeal control logic circuit with the resolution ratio and be connected, the clock circuit respectively with the ratio
Approach by inchmeal control logic circuit is can configure compared with device with the resolution ratio to connect；
The capacitor type digital analog converter is used to sample input analog signal and keeps, and can configure according to the resolution ratio
The different switches digitals of Approach by inchmeal control logic circuit output, to establish the analog voltage needed for the comparator；
The comparator is used to be compared the output voltage of the capacitor type digital analog converter, and in the resolution ratio
Under the control for the latch signal that configurable Approach by inchmeal control logic circuit and the clock circuit produce, output digit signals,
The number that the comparator is compared in each conversion can configure gradual approaching A/D converter configuration equal to resolution ratio
Resolution ratio value；
The resolution ratio can configure Approach by inchmeal control logic circuit and be used to sample and kept for the stage, produce described in control
Sampled signal needed for the mistuning calibration function control signal of comparator progress mistuning calibration function and the capacitor type digital analog converter；
In the conversion stage, produce the switches digital and produce the latch signal with the clock circuit, the resolution ratio can
The state machine for configuring Approach by inchmeal control logic circuit redirects accordingly according to the selection of the value of the resolution-control signal received,
And it is sequentially generated the output digit signals that resolution ratio can configure the corresponding digit of gradual approaching A/D converter.
Further, the capacitor type digital analog converter divides segmental structure for (N-1) potential difference, wherein, N can match somebody with somebody for resolution ratio
The ultimate resolution that gradual approaching A/D converter can configure is put, the capacitor type digital analog converter includes high-order section capacitance
Array and low level section capacitor array, it is described a high position section capacitor array and the low level section capacitor array capacitance size respectively according to
The bridging electricity that binary weight redesign, the high position section capacitor array and the low level section capacitor array pass through specific capacitance size
Appearance links together, in the capacitor type digital analog converter all capacitance bottom crowns all by controlling switch and reference voltage,
Negative reference voltage and common-mode voltage link together, and the high position section capacitor array bottom crown is by sampling switch to inputting mould
Intend signal to be sampled.
Resolution ratio of the present invention can configure SAR ADC laying out pattern connect up it is convenient and simple, substantially reduce capacitance
The parasitic capacitance introduced between the key nodes such as top crown, bottom crown, SAR ADC can reach under each different resolution pattern
To optimal dynamic characteristic and static characteristic.
Brief description of the drawings
In order to clearly illustrate the technical solution of exemplary embodiment of the present, below to required in description embodiment
The attached drawing to be used does a simple introduction.Obviously, the attached drawing introduced is the part of the embodiment of the invention to be described
Attached drawing, rather than whole attached drawings, for those of ordinary skill in the art, without creative efforts, may be used also
To obtain other attached drawings according to these attached drawings.
Fig. 1 is the structure that existing resolution ratio can configure the capacitor type DAC that SAR ADC technical solution intermediate-resolutions can configure
Figure.
Fig. 2 is the state machine jump that existing resolution ratio can configure Approach by inchmeal control logic circuit in SAR ADC technical solutions
Turn figure.
Fig. 3 is the structure chart that resolution ratio provided in an embodiment of the present invention can configure SAR ADC.
Wherein, VCM、VRP、VRN、VIP、VIN、ADC_CLK、LATCH_GEN、LATCH、KOS、ADC_RES[2:0]、ADC_
SAMP and SW [11:0] it is respectively common-mode voltage, reference voltage, negative reference voltage, positive input analog signal, negative input simulation
Signal, ADC clock signals, latch produce signal, comparator latch signal, mistuning calibration function control signal, resolution-control signal,
ADC sampled signals and capacitor array bottom crown switch controlling signal.
Fig. 4 is that resolution ratio provided in an embodiment of the present invention can configure SAR ADC intermediate-resolutions and can configure Approach by inchmeal control
The state machine of logic circuit redirects figure.
Fig. 5 is the spectrogram that the SAR ADC that existing resolution ratio can configure in scheme export signal under 12- bit modes.
Fig. 6 is that resolution ratio provided in an embodiment of the present invention can configure the frequency that SAR ADC export signal under 12- bit modes
Spectrogram.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below with reference to attached in the embodiment of the present invention
Figure, by embodiment, is fully described by technical scheme.Obviously, described embodiment is of the invention
Part of the embodiment, instead of all the embodiments, based on the embodiment of the present invention, those of ordinary skill in the art are not doing
The every other embodiment obtained on the premise of going out creative work, each falls within protection scope of the present invention.
Fig. 3 is the structure chart that resolution ratio provided in an embodiment of the present invention can configure SAR ADC.As shown in figure 3, the resolution ratio
Configurable SAR ADC include：
Capacitor type DAC301, comparator 302, resolution ratio can configure Approach by inchmeal control logic circuit 303 and clock circuit
304。
The output terminal of capacitor type DAC301 is connected with the input terminal of comparator 302, the output terminal and resolution ratio of comparator 302
The input terminal connection of configurable Approach by inchmeal control logic circuit 303, clock circuit 304 respectively with comparator 302 and resolution ratio
Configurable Approach by inchmeal control logic circuit 303 connects.
Capacitor type DAC301 is used to sample input analog signal and keeps, and can configure Approach by inchmeal control according to resolution ratio
The different switches digitals that logic circuit 303 exports, to establish the analog voltage needed for comparator 302.
Capacitor type DAC301 is differential configuration, including anode capacitor array 310 and negative terminal capacitor array 320.Wherein,
Anode capacitor array 310 and negative terminal capacitor array 320 are 11 segmental structure capacitor arrays.Anode capacitor array
310 include anode low level section capacitor array 311 and anode high position section capacitor array 312, and negative terminal capacitor array includes negative terminal low level
Section capacitor array 321 and negative terminal high position section capacitor array 322.Wherein, anode low level section capacitor array 311 and negative terminal low level section electricity
It is 5 capacitor arrays to hold array 321, is respectively：C111、C112、C113、C114、C115And C211、C212、C213、C214、C215, electricity
Hold size to determine according to binary weights C, 2C, 4C, 8C and 16C respectively；Anode high position section capacitor array 312 and negative terminal are high-order
Section capacitor array 322 is 6 capacitor arrays, is respectively：C121、C122、C123、C124、C125、C126、C127And C221、C222、C223、
C224、C225、C226、C227, capacitance size determines according to binary weights C, C, 2C, 4C, 8C, 16C and 32C respectively.Anode electricity
All capacitance bottom crowns for holding array 310 and negative terminal capacitor array 320 are all electric with reference voltage, negative reference respectively by switching
Pressure and common-mode voltage connection, in addition, anode high position section capacitor array 312 and negative terminal high position section capacitor array 322 pass through sampling
Switch respectively with positive input analog signal VIPWith negative input analog signal VINConnection.Anode low level section capacitor array and anode are high
Position section capacitor array and negative terminal low level section capacitor array and negative terminal high position section capacitor array pass through specific capacitance size C's respectively
Flying capcitor Ca1、Ca2Link together.
The control signal of all switches can configure Approach by inchmeal control logic circuit by resolution ratio in capacitor type DAC301
303 produce.
Comparator 302 is used to be compared the output voltage of capacitor type DAC301, and can configure in resolution ratio and gradually force
Under the control for the latch signal that nearly control logic circuit 303 and clock circuit 304 produce, output digit signals, comparator 302 exists
The number being compared every time in conversion is equal to the value that resolution ratio can configure the resolution ratio of SARADC configurations.
Resolution ratio can configure Approach by inchmeal control logic circuit 303 and be used to sample and kept for the stage, produces control and compares
Sampled signal needed for the mistuning calibration function control signal and capacitor type DAC of the progress mistuning calibration function of device 302；In the conversion stage, production
It is raw to control the switches digital of all switches in capacitor type DAC and produce control comparator 302 with clock circuit 304
Latch signal, the state machine that resolution ratio can configure Approach by inchmeal control logic circuit 303 control letter according to the resolution ratio received
Number value selection redirect accordingly, and be sequentially generated the output digit signals that resolution ratio can configure the corresponding digits of SAR ADC so that
Achieve the purpose that resolution ratio can configure.
It can configure the SAR ADC in scheme compared to existing resolution ratio, resolution ratio provided in an embodiment of the present invention can configure
The advantages of SAR ADC, need not be inserted into switch in capacitor type DAC, can be realized directly from Approach by inchmeal logical algorithm pair
The configuration of SAR ADC resolution ratio.
Specifically, Fig. 4 is that resolution ratio provided in an embodiment of the present invention can configure SAR ADC intermediate-resolutions and can configure and gradually forces
The state machine of nearly control logic circuit redirects figure, and under each state, the operation which can configure SARADC is as follows：
Sample phase：Resolution ratio is 8- bits, 9- bits, 10- bits, 11- bits, the corresponding sample phase of 12- bits
State is respectively：1000th, 1001,1010,1011 and 1100.Anode high position section capacitor array 312 and negative terminal high position section capacitance battle array
The bottom crown of capacitance meets V respectively in row 322IP、VIN；Anode low level section capacitor array 311 and negative terminal low level section capacitor array 321
The bottom crown of middle capacitance meets VCM；The output termination V of capacitor type DAC301CM, and comparator 302 carries out mistuning calibration function operation.
After each node voltage is established completely in sample phase, anode capacitor array 310 and negative terminal capacitor array 320 export
The electric charge at end is respectively such as following formula：
Q310=VCM×64C-VIP*64C (1)
Q320=VCM×64C-VIN*64C
Wherein, Q310And Q320The respectively electric charge of 320 output terminal of anode capacitor array 310 and negative terminal capacitor array.
The holding stage：The output terminal and V of 0000, capacitor type DAC301CMDisconnect, comparator 302 completes mistuning calibration function operation；
The capacitance bottom crown of anode high position section capacitor array 312 and negative terminal high position section capacitor array 322 is respectively and VIP、VINDisconnect, and connect
VCM；Comparator 302 carries out first time comparison.
The voltage of 320 output terminal of anode capacitor array 310 and negative terminal capacitor array is respectively such as following formula：
Wherein, V310And V310The respectively voltage of 320 output terminal of anode capacitor array 310 and negative terminal capacitor array,
First time quantization stage：0001, C is adjudicated according to the result of laststate comparator 302127And C227Connect positive and negative reference
Voltage condition, and determine MSB (highest significant position, Most Significant Bit) position D [11] of SAR ADC；Comparator 302
Compare for the second time.
Second of quantization stage：0010, C is adjudicated according to the result of laststate comparator 302126And C226Connect positive and negative reference
Voltage condition, and determine the MSB-1 positions D [10] of SAR ADC；302 third time of comparator compares.
Third time quantization stage：0011, C is adjudicated according to the result of laststate comparator 302125And C225Connect positive and negative reference
Voltage condition, and determine the MSB-2 positions D [9] of SAR ADC；The 4th comparison of comparator 302.
4th quantization stage：0100, C is adjudicated according to the result of laststate comparator 302124And C224Connect positive and negative reference
Voltage condition, and determine the MSB-3 positions D [8] of SAR ADC；The 5th comparison of comparator 302.
5th quantization stage：0101, C is adjudicated according to the result of laststate comparator 302123And C223Connect positive and negative reference
Voltage condition, and determine the MSB-4 positions D [7] of SAR ADC；The 6th comparison of comparator 302.
6th quantization stage：0110, C is adjudicated according to the result of laststate comparator 302122And C222Connect positive and negative reference
Voltage condition, and determine the MSB-5 positions D [6] of SAR ADC；The 7th comparison of comparator 302.
7th quantization stage：0111, C is adjudicated according to the result of laststate comparator 302115And C215Connect positive and negative reference
Voltage condition, and determine the MSB-6 positions D [5] of SAR ADC；The 8th comparison of comparator 302.
8th quantization stage：1000, the MSB-7 positions D of SAR ADC is determined according to the result of laststate comparator 302
[4].If SAR ADC are 8- bit modes, export as D [11:4], next sampling, NextState 0000 are carried out；Otherwise, sentence
Certainly C in SAR ADC114And C214Connect positive negative reference voltage situation, the 9th comparison of comparator 302.
9th quantization stage：1001, the MSB-8 positions D of SAR ADC is determined according to the result of laststate comparator 302
[3].If SAR ADC are 9- bit modes, export as D [11:3], next sampling, NextState 0000 are carried out；Otherwise, sentence
Certainly C in SAR ADC113And C213Connect positive negative reference voltage situation, the tenth comparison of comparator 302.
Tenth quantization stage：1010, the MSB-9 positions D of SAR ADC is determined according to the result of laststate comparator 302
[2].If SAR ADC are 10- bit modes, export as D [11:2], next sampling, NextState 0000 are carried out；Otherwise,
Adjudicate C in SAR ADC112And C212Positive negative reference voltage situation is connect, comparator 302 the tenth once compares.
Tenth quantization stage：1011, the MSB-10 of SAR ADC is determined according to the result of laststate comparator 302
Position D [1].If SAR ADC are 11- bit modes, export as D [11:1], next sampling, NextState 0000 are carried out；It is no
Then, C in SAR ADC is adjudicated111And C211Connect positive negative reference voltage situation, the 12nd comparison of comparator 302.
Tenth second quantization stage：1100, the MSB-11 of SAR ADC is determined according to the result of laststate comparator 302
Position D [0], carries out next sampling, NextState 0000.
For the judgement of every, if the result of comparator 302 is 1, then the corresponding positions of SAR ADC output digit signals
For 0, the bottom crown of corresponding capacitance meets V in anode capacitor array 310RN, the bottom crown of corresponding capacitance connects in negative terminal capacitor array 320
VRP；Similarly, if the result of comparator 302 is 0, then the corresponding positions of SAR ADC output digit signals are 1, anode capacitance battle array
The bottom crown of corresponding capacitance meets V in row 310RP, the bottom crown of corresponding capacitance meets V in negative terminal capacitor array 320RN。
The resolution ratio can configure SAR ADC and often complete once to change, anode capacitor array 310 and negative terminal capacitor array 320
The voltage and its difference such as following formula of output terminal：
Wherein, V310 /And V320 /Respectively anode capacitor array 310 and the output terminal of negative terminal capacitor array 320 is turning every time
Voltage at the end of changing；D<i>And！D<i>(i=11) positive input analog signal V is represented as respectivelyIPWith negative input analog signal
VIN12- bit quantizations digital signal,！Represent logic NOT；VRFor VRPWith VRNDifference.
Fig. 5 is the spectrogram that the SAR ADC that existing resolution ratio can configure in scheme export signal under 12- bit modes.
Fig. 6 is that resolution ratio provided in an embodiment of the present invention can configure the spectrogram that SAR ADC export signal under 12- bit modes.Fig. 5
Abscissa and ordinate with Fig. 6 are respectively frequency input signal/sample rate and power, and the unit of wherein power is dB.From Fig. 5
It can be seen that：Frequency spectrum has obvious harmonic wave, and than high many under normal circumstances, significance bit only has 10.67- bits, nothing at bottom of entirely making an uproar
Spuious dynamic range only has 76.49-dB, this is because the conducting resistance and parasitic capacitance that are switched in insertion capacitor type DAC are made
Into.SAR ADC performances under 12- bit modes substantially reduce in prior art, and performance has also dropped under other patterns
It is low.As can be seen from Figure 6：It is provided in an embodiment of the present invention compared with the frequency spectrum of SAR ADC output signals in prior art
Resolution ratio can configure bottom of making an uproar in SAR ADC output signal frequency spectrums and be reduced to normal level, and harmonic wave also eliminates.The embodiment of the present invention
It is 12- bits that the resolution ratio of offer, which can configure significance bits of the SAR ADC under 12- bit resolutions, is carried compared with traditional scheme
High 1.33- bits, spurious-free dynamic range 86.89-dB, improves 10.4-dB compared with traditional scheme.In other resolutions
Under rate pattern, the performance of analog-digital converter is significantly improved, and completely eliminates in traditional scheme in capacitor array
The negative effect that insertion switch is brought.
Table 1：Existing resolution ratio, which can configure SAR ADC in technical solution and resolution ratio provided in an embodiment of the present invention, to match somebody with somebody
SAR ADC are put, it is preceding under 8- bits to 12- bit modes to emulate the dynamic characteristic parameter contrast table drawn.
Table 1
As shown in Table 1：In the prior art scheme, the resolution ratio configuration of SAR ADC is higher, is inserted into capacitor type DAC
Influence of the analog switch to SAR ADC performances it is bigger, in the case where being configured to 12- bit modes, the significance bit of SAR ADC only has
10.67- bits.Scheme compared with the prior art, resolution ratio provided in an embodiment of the present invention can configure SAR ADC in each resolution
Extraordinary effect is attained by under rate.
It should be noted that embodiment provided by the present invention is a specific embodiment, this is not limited to
Invention, resolution ratio provided in an embodiment of the present invention can configure SAR ADC technologies suitable for fully differential structure, pseudo differential architectures and
The resolution ratio of single-ended structure can configure SAR ADC.Resolution ratio is equally applicable to be configured to compare less than any of capacitor array digit
Special resolution ratio can configure SAR ADC.
Resolution ratio provided in an embodiment of the present invention can configure SAR ADC and be added to only by resolution ratio can configure algorithm
In Approach by inchmeal control logic circuit, the designing scheme that SAR ADC are can configure with existing resolution ratio is compared, and avoiding resolution ratio can
Configure the design of capacitance DAC arrays, that is to say, that eliminate needs to carry out the switch that resolution ratio can configure in capacitor array.With existing
There is technical solution to compare, the invention enables laying out pattern wiring it is convenient and simple, be not inserted into any switch in capacitance DAC arrays,
So the parasitic capacitance introduced between the key node such as upper and lower pole plate of capacitance greatly reduces.In the aspect of performance of SAR ADC, with
Prior art is compared, and is reduced at the bottom of making an uproar of output signal spectrum under each resolution model the invention enables SAR ADC
Normal level, harmonic wave are eliminated, and dynamic characteristic and static characteristic are significantly improved.
The technical principle that above are only presently preferred embodiments of the present invention and used.The invention is not restricted to spy described here
Determine embodiment, the various significant changes that can carry out for a person skilled in the art, readjust and substitute all without departing from
Protection scope of the present invention.Therefore, although being described in further detail by above example to the present invention, this hair
It is bright to be not limited only to above example, without departing from the inventive concept, other more equivalence enforcements can also be included
Example, and the scope of the present invention is determined by the scope of claim.
Claims (2)
1. a kind of resolution ratio can configure gradual approaching A/D converter, it is characterised in that including capacitor type digital analog converter, ratio
Approach by inchmeal control logic circuit and clock circuit are can configure compared with device, resolution ratio,
The output terminal of the capacitor type digital analog converter is connected with the input terminal of the comparator, the output terminal of the comparator with
The resolution ratio can configure Approach by inchmeal control logic circuit input terminal connection, the clock circuit respectively with the comparator
Approach by inchmeal control logic circuit is can configure with the resolution ratio to connect；
The capacitor type digital analog converter is used to sample input analog signal and keeps, and can configure gradually according to the resolution ratio
The different switches digitals of control logic circuit output are approached, to establish the analog voltage needed for the comparator；Wherein,
The capacitor type digital analog converter divides segmental structure for (N-1) potential difference, and N can configure gradual approaching A/D converter for resolution ratio
The ultimate resolution that can be configured；
The comparator is used to be compared the output voltage of the capacitor type digital analog converter, and can match somebody with somebody in the resolution ratio
Under the control for putting the latch signal that Approach by inchmeal control logic circuit and the clock circuit produce, output digit signals are described
The number that comparator is compared in each conversion is equal to point that resolution ratio can configure gradual approaching A/D converter configuration
The value of resolution；
The resolution ratio can configure Approach by inchmeal control logic circuit and be used to sample and kept for the stage, produces and controls the comparison
Sampled signal needed for the mistuning calibration function control signal of device progress mistuning calibration function and the capacitor type digital analog converter；Changing
In the stage, produce the switches digital and produce the latch signal with the clock circuit, the resolution ratio can configure
The state machine of Approach by inchmeal control logic circuit redirects accordingly according to the selection of the value of the resolution-control signal received, and according to
The secondary output digit signals for producing resolution ratio and can configure the corresponding digit of gradual approaching A/D converter.
2. resolution ratio according to claim 1 can configure gradual approaching A/D converter, it is characterised in that the capacitance
Type digital analog converter includes high-order section capacitor array and low level section capacitor array, the high position section capacitor array and the low level section
The capacitance size of capacitor array is respectively according to binary weight redesign, the high position section capacitor array and the low level section capacitance battle array
Row are linked together by the flying capcitor of specific capacitance size, and all capacitance bottom crowns are all in the capacitor type digital analog converter
Linked together by controlling switch and reference voltage, negative reference voltage and common-mode voltage, the high position section capacitor array
Bottom crown samples input analog signal by sampling switch.
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