CN104505118B - A kind of level translator in high-speed DRAM - Google Patents
A kind of level translator in high-speed DRAM Download PDFInfo
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- CN104505118B CN104505118B CN201410802761.9A CN201410802761A CN104505118B CN 104505118 B CN104505118 B CN 104505118B CN 201410802761 A CN201410802761 A CN 201410802761A CN 104505118 B CN104505118 B CN 104505118B
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Abstract
The present invention relates to a kind of level translators in high-speed DRAM, utilize two identical level translators and phase inverter inv21.When solving existing level translator rising edge in DRAM with to decline delay difference very big, the technical issues of restricting DRAM speed, the present invention can make that the rising edge of signal out is delayed and trailing edge is delayed and exactly matches.
Description
Technical field
The present invention relates to a kind of level translators in high-speed DRAM.
Background technology
In DRAM, for power saving, internal circuit is generally operational in relatively low voltage, such as 1.1v, and DRAM interface number
It is higher according to voltage, such as 1.8v.In DRAM, a very crucial module is exactly level translator (Level-shifter),
Data is responsible for be promoted to interface voltage (such as 1.8v) from builtin voltage (such as 1.1v) by it.Traditional level translator
Very big with decline delay difference during Level-shifter rising edges, this is also a main bottleneck for restricting DRAM product speed.
As shown in Figure 1, the level translator Level-Shifter of this structure will cause during rising edge and decline delay is serious to lose
Match somebody with somebody.When input signal ls_in by it is low become higher (rising edge) when, n-type metal-oxide-semiconductor (n0) turns on first, and signal ls_out_n is lower, so
P-type metal-oxide-semiconductor p1 is turned on afterwards, and signal ls_out becomes higher, because the driving force of output signal ls_out is weaker.So input letter
Number ls_in by it is low become higher (rising edge) when, rising edge passes to output signal ls_out by 2 metal-oxide-semiconductors (n0 and p1).Work as input
It when signal ls_in is lower by height (trailing edge), is become higher first by phase inverter inv0, ls_in_n, then n-type metal-oxide-semiconductor (n1) is led
Logical, output signal ls_out is lower, so trailing edge passes to ls_out by 1 phase inverter inv0 and 1 metal-oxide-semiconductor.Due to anti-
The delay of phase device (inv0) is more much smaller than the delay of p1, so causing trailing edge delay faster than rising edge delay very much, so as to lead
Duty cycle (duty-cycle) gross distortion of level translator level-shiter outputs is caused, so as to influence the speed of DRAM.
Because the output signal ls_out driving forces of level translator Level-Shifter are not strong, need using two drives
The incremental phase inverter of kinetic force (inv1 and inv2) is used for increasing the driving force of output.
The content of the invention
In order to when solving existing level translator rising edge in DRAM with very big, the restriction that declines delay difference
The technical issues of DRAM speed, the present invention provide a kind of level translator in high-speed DRAM.
The technical solution of the present invention：
A kind of level translator in high-speed DRAM, including the first level conversion unit, first level conversion
Unit includes p-type metal-oxide-semiconductor p10, p-type metal-oxide-semiconductor p11, n-type metal-oxide-semiconductor n10, n-type metal-oxide-semiconductor n11, phase inverter inv10, phase inverter
Inv11 and phase inverter inv12, input signal ls_in are inputted to the grid end of n-type metal-oxide-semiconductor n10, and input signal ls_in is by anti-
Phase device inv10 exports rp input signal ls_in_n, and rp input signal ls_in_n is inputted to the grid end of n-type metal-oxide-semiconductor n11, n
The drain terminal of type metal-oxide-semiconductor n10 and the drain terminal of n-type metal-oxide-semiconductor n11 are grounded, the leakage of the source, p-type metal-oxide-semiconductor p10 of n-type metal-oxide-semiconductor n10
End, the grid end connection of p-type metal-oxide-semiconductor p11, the source of p-type metal-oxide-semiconductor p10 and the source of p-type metal-oxide-semiconductor p11 meet power supply, p-type MOS
The source of the drain terminal of pipe p11, the grid end of p-type metal-oxide-semiconductor p10 and n-type metal-oxide-semiconductor n11 is all connected to A points, phase inverter inv11 and anti-
Phase device inv12 is sequentially connected, and A points are connected with the input terminal of phase inverter inv11, the output terminal output output letter of phase inverter inv12
Number out_1；
It is characterized in that：Further include second electrical level converting unit and phase inverter inv21, including p-type metal-oxide-semiconductor p20,
P-type metal-oxide-semiconductor p21, n-type metal-oxide-semiconductor n20, n-type metal-oxide-semiconductor n21 and phase inverter inv20, rp input signal ls_in_n are inputted to n
The grid end of type metal-oxide-semiconductor n20, rp input signal ls_in_n export rp input signal ls_in_d by phase inverter inv20, instead
Phase input signal ls_in_d is inputted to the grid end of n-type metal-oxide-semiconductor n21, the drain terminal of n-type metal-oxide-semiconductor n20 and the drain terminal of n-type metal-oxide-semiconductor n21
It is grounded, the grid end connection of the source of n-type metal-oxide-semiconductor n20, the drain terminal of p-type metal-oxide-semiconductor p20, p-type metal-oxide-semiconductor p21, p-type metal-oxide-semiconductor p20
Source and the source of p-type metal-oxide-semiconductor p21 connect power supply, the drain terminal of p-type metal-oxide-semiconductor p21, the grid end and n-type of p-type metal-oxide-semiconductor p20
The source of metal-oxide-semiconductor n21 is all connected to A ＇ points, and A ' are connected with the input terminal of phase inverter inv21, the output terminal of phase inverter inv22
Output signal output out_2, output signal out_1 form output signal out after converging with output signal out_2.
Metallic resistance r1 and metallic resistance r2 are further included, output signal out_1 is inputted to one end of metallic resistance r1, output
Signal out_2 is inputted to one end of metallic resistance r2, and the other end of metallic resistance r1 connects shape with the other end of metallic resistance r2
Into output signal out.
Advantage for present invention：
Two same level converting units (LS1, LS2) of the invention, for LS1, the rising edge when ratio of ls_out_1
It is big to decline delay, after 2 phase inverters (inv11, inv12), when rising edge of out_1 is still more much larger than declining delay.
It is bigger than declining delay during the rising edge of ls_out_n_2 for LS2, after 1 phase inverter inv21, the decline of out_2
It is much larger when delay is than rising edge.Signal out_1 and out_2 is connected to together by metallic resistance r1 and r2, by skipping adjustment
The resistance value of r1 and r2 can exactly match the rising edge delay of signal out and trailing edge delay.
Description of the drawings
Fig. 1 is the structure diagram of traditional level translator；
Fig. 2 is the structure diagram for the level translator in high-speed DRAM of the present invention.
Specific embodiment
A kind of level translator in high-speed DRAM is converted including the first level conversion unit LS1 and second electrical level
Unit LS2, the first level conversion unit include p-type metal-oxide-semiconductor p10, p-type metal-oxide-semiconductor p11, n-type metal-oxide-semiconductor n10, n-type metal-oxide-semiconductor n11,
Phase inverter inv10, phase inverter inv11 and phase inverter inv12, input signal ls_in are inputted to the grid end of n-type metal-oxide-semiconductor n10,
Input signal ls_in by phase inverter inv10 export rp input signal ls_in_n, rp input signal ls_in_n input to
The grid end of n-type metal-oxide-semiconductor n11, the drain terminal of the drain terminal and n-type metal-oxide-semiconductor n11 of n-type metal-oxide-semiconductor n10 are grounded, the source of n-type metal-oxide-semiconductor n10
End, the grid end connection of the drain terminal of p-type metal-oxide-semiconductor p10, p-type metal-oxide-semiconductor p11, the source of p-type metal-oxide-semiconductor p10 and the source of p-type metal-oxide-semiconductor p11
End connects power supply, and the source of the drain terminal of p-type metal-oxide-semiconductor p11, the grid end of p-type metal-oxide-semiconductor p10 and n-type metal-oxide-semiconductor n11 is all connected to A
Point, phase inverter inv11 and phase inverter inv12 are sequentially connected, and A points are connected with the input terminal of phase inverter inv11, phase inverter inv12
Output terminal output signal output out_1；Second electrical level converting unit includes p-type metal-oxide-semiconductor p20, p-type metal-oxide-semiconductor p21, n-type MOS
Pipe n20, n-type metal-oxide-semiconductor n21, phase inverter inv20 and phase inverter inv21, rp input signal ls_in_n are inputted to n-type MOS
The grid end of pipe n20, rp input signal ls_in_n export rp input signal ls_in_d by phase inverter inv20, and reverse phase is defeated
Enter signal ls_in_d to input to the grid end of n-type metal-oxide-semiconductor n21, the drain terminal of the drain terminal and n-type metal-oxide-semiconductor n21 of n-type metal-oxide-semiconductor n20 connects
Ground, the grid end connection of the source of n-type metal-oxide-semiconductor n20, the drain terminal of p-type metal-oxide-semiconductor p20, p-type metal-oxide-semiconductor p21, the source of p-type metal-oxide-semiconductor p20
The source of end and p-type metal-oxide-semiconductor p21 connect power supply, drain terminal, the grid end of p-type metal-oxide-semiconductor p20 and the n-type metal-oxide-semiconductor of p-type metal-oxide-semiconductor p21
The source of n21 is all connected to A ＇ points, and A ' are connected with the input terminal of phase inverter inv21, the output signal output of phase inverter inv22
Out_2, output signal out_1 form output signal out after converging with output signal out_2.Further include metallic resistance r1 and gold
Belong to resistance r2, output signal out_1 is inputted to one end of metallic resistance r1, and output signal out_2 is inputted to metallic resistance r2's
One end, the other end of metallic resistance r1 connect to form output signal out with the other end of metallic resistance r2.
In the solution of the present invention, using two identical Level-Shifter (LS1 and LS2).For LS1,
It is bigger than declining delay during the rising edge of ls_out_1, after 2 phase inverters (inv11 and inv12), during the rising edge of out_1
It is still more much larger than declining delay.It is bigger than declining delay during the rising edge of ls_out_n_2 for LS2, by 1 reverse phase
After device inv21, the decline of out_2 is much larger when being delayed than rising edge.Signal out_1 and out_2 passes through metallic resistance r1 and r2
It is connected to together, by the resistance value for skipping adjustment r1 and r2 the rising edge of signal out can be made to be delayed and be delayed completely with trailing edge
Matching.
Claims (2)
1. a kind of level translator in high-speed DRAM, including the first level conversion unit, the first level conversion list
Member includes p-type metal-oxide-semiconductor p10, p-type metal-oxide-semiconductor p11, n-type metal-oxide-semiconductor n10, n-type metal-oxide-semiconductor n11, phase inverter inv10, phase inverter inv11
And phase inverter inv12, input signal ls_in are inputted to the grid end of n-type metal-oxide-semiconductor n10, input signal ls_in passes through phase inverter
Inv10 exports rp input signal ls_in_n, and rp input signal ls_in_n is inputted to the grid end of n-type metal-oxide-semiconductor n11, n-type
The drain terminal of metal-oxide-semiconductor n10 and the drain terminal of n-type metal-oxide-semiconductor n11 are grounded, the source of n-type metal-oxide-semiconductor n10, drain terminal, the p of p-type metal-oxide-semiconductor p10
The grid end connection of type metal-oxide-semiconductor p11, the source of p-type metal-oxide-semiconductor p10 and the source of p-type metal-oxide-semiconductor p11 meet power supply, p-type metal-oxide-semiconductor p11
Drain terminal, the grid end of p-type metal-oxide-semiconductor p10 and the source of n-type metal-oxide-semiconductor n11 be all connected to A points, phase inverter inv11 and phase inverter
Inv12 is sequentially connected, and A points are connected with the input terminal of phase inverter inv11, the output terminal output signal output of phase inverter inv12
out_1；
It is characterized in that：Second electrical level converting unit and phase inverter inv21 are further included, including p-type metal-oxide-semiconductor p20, p-type metal-oxide-semiconductor
P21, n-type metal-oxide-semiconductor n20, n-type metal-oxide-semiconductor n21 and phase inverter inv20, rp input signal ls_in_n are inputted to n-type metal-oxide-semiconductor
The grid end of n20, rp input signal ls_in_n export rp input signal ls_in_d, anti-phase input by phase inverter inv20
Signal ls_in_d is inputted to the grid end of n-type metal-oxide-semiconductor n21, and the drain terminal of the drain terminal and n-type metal-oxide-semiconductor n21 of n-type metal-oxide-semiconductor n20 connects
Ground, the grid end connection of the source of n-type metal-oxide-semiconductor n20, the drain terminal of p-type metal-oxide-semiconductor p20, p-type metal-oxide-semiconductor p21, the source of p-type metal-oxide-semiconductor p20
The source of end and p-type metal-oxide-semiconductor p21 connect power supply, drain terminal, the grid end of p-type metal-oxide-semiconductor p20 and the n-type metal-oxide-semiconductor of p-type metal-oxide-semiconductor p21
The source of n21 is all connected to A ＇ points, and A ' are connected with the input terminal of phase inverter inv21, and the output terminal output of phase inverter inv22 is defeated
Go out signal out_2, output signal out_1 forms output signal out after converging with output signal out_2.
2. the level translator according to claim 1 in high-speed DRAM, it is characterised in that：Further include metallic resistance
R1 and metallic resistance r2, output signal out_1 are inputted to one end of metallic resistance r1, and output signal out_2 is inputted to metal electricity
One end of r2 is hindered, the other end of metallic resistance r1 connects to form output signal out with the other end of metallic resistance r2.
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| CN201410802761.9A CN104505118B (en) | 2014-12-18 | 2014-12-18 | A kind of level translator in high-speed DRAM |
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| JP3123463B2 (en) * | 1997-05-16 | 2001-01-09 | 日本電気株式会社 | Level conversion circuit |
| JP3717781B2 (en) * | 2000-10-30 | 2005-11-16 | 株式会社ルネサステクノロジ | Level conversion circuit and semiconductor integrated circuit |
| CN101488742A (en) * | 2008-01-15 | 2009-07-22 | 瑞昱半导体股份有限公司 | Electric level converting apparatus and method |
| CN103795401A (en) * | 2014-02-18 | 2014-05-14 | 南通大学 | Output unit circuit with controllable output level |
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Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant before: Xi'an Sinochip Semiconductors Co., Ltd. |
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