CN104502835B - Serial link in-chip signal quality oscilloscope circuit and method - Google Patents
Serial link in-chip signal quality oscilloscope circuit and method Download PDFInfo
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Abstract
The invention provides a serial link in-chip signal quality oscilloscope circuit and method. The circuit comprises a code pattern generating circuit, a sampling circuit, a serial-to-parallel circuit, a data detection circuit, an alternating-current coupling capacitor, a differential DAC (Digital to Analog Conversion) circuit and a phase difference circuit, wherein the phase of the sampling circuit can be manually controlled through the phase difference circuit. The phase of a sampling clock is scanned through a phase interpolation circuit; meanwhile, scanning on an input differential signal common-mode voltage is performed; the eye pattern of a serial signal input into a system is depicted by taking the bit error rate as a standard through two-dimensional scanning of two variables including time and voltage, so that the quality is evaluated. The circuit is implemented through a digital-analog hybrid circuit, is integrated into a chip, and can be applied to testing of various signal links. By adopting the circuit, the interference of external factors such as channels and encapsulation can be eliminated, and quality information of an input signal in the chip can be truly restored.
Description
Technical field
The invention belongs to be IC design technology, it is related to signal quality oscillography circuit and side in a kind of serial link piece
Method.
Background technology
, it is necessary to be estimated to being sent to the terminal i.e. signal of receiving terminal during high-speed serial signals link test.
Conventional means are that the signal for being sent to receiving terminal is observed using oscillograph, but due to the influence of encapsulation etc., oscillography
The signal that device is observed also only is the signal entered before receiver encapsulation.Due to chip package have pin, wiring, substrate cabling,
Also there is certain decay in the parasitic influence such as press welding block, the signal sampled to chip receiving terminal from encapsulation outer pin, therefore, show
Signal that ripple device is observed and the non-real signal in receiving terminal sampling, this assessment and failure of chip to signal quality are determined
Position brings certain difficulty.
The content of the invention
The present invention provides a kind of production method for shaking serial signal source, and the circuit is based on the serial chain of phase difference value circuit
Road receiver and data detection circuit.By sampling clock phase and minimum input difference two two-dimensional scans of variable of amplitude,
With the bit error rate as standard, the eye pattern of the serial signal in the system of being input to is depicted, so as to assess its quality.
Particular technique solution of the invention is as follows：
Signal quality oscillography circuit in a kind of serial link piece, it is characterized in that：
Pattern including being sequentially connected produces circuit I 1, sample circuit I2, string to turn and circuit I 3, data detection circuit I4,
Also include ac coupling capacitor (C1, C2), difference DAC-circuit I5, phase difference value circuit I 6；
The pattern produces circuit I 1 to generate specific periodicity serial differential signals and by differential channel Ch1 and Ch2
Output；
The ac coupling capacitor C1 and C2 is located at pattern and produces the difference between circuit I 1 and sample circuit I2 to believe respectively
On road Ch1 and Ch2, for removing the DC information in serial differential signals；
According to DAC control codes, the output direct current signal that output difference amplitude is not waited connects the difference DAC-circuit I5 respectively
Enter differential channel Ch1 and Ch2；
The phase difference value circuit I 6 exports clock defeated according to the phase of phase difference value circuit control code scanning sample clock
Go out onto the clock of sample circuit；
The sample circuit I2 samples to the serial signal being input into；
String is turned the serial number that the simultaneously parallel data of circuit output produces circuit generation with pattern by the data detection circuit
According to being contrasted, the corresponding bit error rate is calculated.
Signal quality oscillometric method in a kind of serial link piece, it is characterized in that, comprises the following steps：
1] specific pattern is produced：
Pattern produces circuit to directly generate specific periodicity parallel signal, by defeated after the transmitter string of serial link
Go out differential signal (Dinp, Dinn), or generate specific periodicity serial signal, exported by driver；
2] DC information is removed：
Serial differential signals remove DC information therein by ac coupling capacitor C1 and C2；
3] control of signal sampling：
3.1] input data minimum differential amplitude control：
Difference DAC passes through the direct current signal that the change output difference amplitude of control routine is not waited, after being connected to AC coupled
Serial signal on so that the common-mode voltage of the differential serial signals of input be equal to DAC output differential voltage；By same every time
The polarity increase in one direction reduces the control bit of DAC and changes the common mode deviation of input difference serial signal, so as to change defeated
Enter the minimum differential amplitude of data；
3.2] clock phase scanning：
The one sampling period is divided into several pieces by the sampling clock of sample circuit by phase difference value circuit, per a
The minimum control bit of corresponding its control routine, when receiving serial signal, phase difference is opened or closed according to unidirectional polarity
It is worth the control routine of circuit, the phase that a minimum control bit carrys out scanning sample clock is incremented by every time；
4] signal sampling, the data after sampling turn by string and export parallel data after circuit；Signal sampling therein
Comprise the following steps that：
4.1] input data minimum differential amplitude traversal：
When sample circuit receives data, often change a sampling clock phase, difference DAC control codes are completed according to step 3.1
Once traversal, a minimum control bit is changed every time, reversing at same direction, detection DAC control codes often change once
When the corresponding bit error rate and record；
4.2] sampling clock phase traversal：
After step 4.1 terminates the control code traversal of DAC, according to one phase of step 4.1 same direction reversing
The minimum control bit of difference circuit, then travel through the control code of DAC by step 4.1, so continue, until phase difference value circuit control
Code traversal processed terminates；
5] error rate analyzer：
Parallel data enters in data detection circuit, produces the serial data that circuit is produced to be contrasted by with pattern,
By data accumulation, so as to calculate the corresponding bit error rate；
Parallel data produces the serial data that circuit is produced to be contrasted by turn in data detection circuit with pattern, if
Comparing result is consistent, and error number is zero；
If comparing result is inconsistent, error number adds one, until contrast to last position, obtains total error number；
The bit error rate=total error number/total amount of data (total bit of parallel data).
6] signal quality oscillography in piece：
At the end of step 5, by the corresponding minimum differential amplitude of DAC control codes and the corresponding phase-group of phase difference value circuit
Into two-dimensional coordinate depict, and read the corresponding bit error rate in each coordinate points, you can complete with the bit error rate as reference
Piece in signal oscillography.
Advantages of the present invention is as follows：
1st, by phase-interpolation circuit, while carrying out the scanning of input differential signal common-mode voltage so as to change differential signal
Minimum differential amplitude.By two two-dimensional scans of variable of time and voltage, with the bit error rate as standard, depict to be input to and be
The eye pattern of the serial signal in system, so as to assess its quality.
2nd, circuit is integrated in piece by Digital Analog Hybrid Circuits realization, excludes the interference of the extraneous factors such as channel, encapsulation,
Quality information of the original input signal in chip internal can be truly gone back, be can be used in multi-signal link test.
Brief description of the drawings
Fig. 1 is the circuit realiration figure of the method for the present invention；
Fig. 2 is flow chart of the method for the present invention；
Description of reference numerals：I1- patterns produce circuit, I2- sample circuits, I3- strings to turn and circuit, I4- Data Detections electricity
Road, I5- difference DAC-circuits, I6- phase difference value circuits, Ch1, Ch2- differential channel；C1, C2- ac coupling capacitor.
Specific embodiment
Below in conjunction with the accompanying drawings and specific embodiment, technical scheme is clearly and completely stated.Obviously,
The embodiment stated only is a part of embodiment of the invention, rather than whole embodiments, based on the embodiment in the present invention,
Those skilled in the art are not making the every other embodiment that creative work premise is obtained, and belong to guarantor of the invention
Shield scope.
As shown in figure 1, a kind of signal quality oscillography circuit in serial link piece, including the pattern being sequentially connected produces circuit
I1, sample circuit I2, string turn and circuit I 3, data detection circuit I4, also including ac coupling capacitor (C1, C2), difference DAC electricity
Road I5, phase difference value circuit I 6；Pattern produces circuit I 1 to generate specific periodicity serial differential signals and by differential channel
Ch1 and Ch2 is exported；
Ac coupling capacitor C1 and C2 are located at the differential channel Ch1 between pattern generation circuit I 1 and sample circuit I2 respectively
On Ch2, for removing the DC information in serial differential signals；Difference DAC-circuit I5 is according to DAC control codes, output difference
The output direct current signal that amplitude is not waited, is respectively connected to differential channel Ch1 and Ch2；Phase difference value circuit I 6 is according to phase difference value electricity
The phase of road control code scanning sample clock, in output clock output to the clock of sample circuit；Sample circuit I2 is to input
Serial signal is sampled；String is turned the string that the simultaneously parallel data of circuit output produces circuit generation with pattern by data detection circuit
Row data are contrasted, and calculate the corresponding bit error rate.
As shown in Fig. 2 signal quality oscillometric method in a kind of serial link piece, comprises the following steps：
1] specific pattern is produced：
Pattern produces circuit to directly generate specific periodicity parallel signal, by defeated after the transmitter string of serial link
Go out differential signal (Dinp, Dinn), or generate specific periodicity serial signal, exported by driver；
2] DC information is removed：
Serial differential signals remove DC information therein by ac coupling capacitor C1 and C2；
3] control of signal sampling：
3.1] input data minimum differential amplitude control：
Difference DAC passes through the direct current signal that the change output difference amplitude of control routine is not waited, after being connected to AC coupled
Serial signal on so that the common-mode voltage of the differential serial signals of input be equal to DAC output differential voltage；By same every time
The polarity increase in one direction reduces the control bit of DAC and changes the common mode deviation of input difference serial signal, so as to change defeated
Enter the minimum differential amplitude of data；
3.2] clock phase scanning：
The one sampling period is divided into several pieces by the sampling clock of sample circuit by phase difference value circuit, per a
The minimum control bit of corresponding its control routine, when receiving serial signal, phase difference is opened or closed according to unidirectional polarity
It is worth the control routine of circuit, the phase that a minimum control bit carrys out scanning sample clock is incremented by every time；
4] signal sampling, the data after sampling turn by string and export parallel data after circuit；Signal sampling therein
Comprise the following steps that：
4.1] input data minimum differential amplitude traversal：
When sample circuit receives data, often change a sampling clock phase, difference DAC control codes are completed according to step 3.1
Once traversal, a minimum control bit is changed every time, reversing at same direction, detection DAC control codes often change once
When the corresponding bit error rate and record；
4.2] sampling clock phase traversal：
After step 4.1 terminates the control code traversal of DAC, according to one phase of step 4.1 same direction reversing
The minimum control bit of difference circuit, then travel through the control code of DAC by step 4.1, so continue, until phase difference value circuit control
Code traversal processed terminates；
5] error rate analyzer：
Parallel data enters in data detection circuit, produces the serial data that circuit is produced to be contrasted by with pattern,
By data accumulation, so as to calculate the corresponding bit error rate；
Parallel data produces the serial data that circuit is produced to be contrasted by turn in data detection circuit with pattern, if
Comparing result is consistent, and error number is zero；
If comparing result is inconsistent, error number adds one, until contrast to last position, obtains total error number；
The bit error rate=total error number/total amount of data (total bit of parallel data).
6] signal quality oscillography in piece：
When step 5] at the end of, by the corresponding minimum differential amplitude of DAC control codes and the corresponding phase of phase difference value circuit
The two-dimensional coordinate of composition is depicted, and reads the corresponding bit error rate in each coordinate points, you can it is ginseng to complete with the bit error rate
According to piece in signal oscillography.
The present invention provides signal quality oscillometric method in a kind of serial link piece, and the method is comprised the following steps：
1] signal sends specific pattern
The pattern of data detection circuit produces circuit I 1 to send specific cyclical signal, can send parallel signal, leads to
Dinp and Dinn is exported after crossing the transmitter string of serial link, serial signal also can be transmitted, (figure is directly exported by driver
In equally represented with Dinp and Dinn)；
2] receiver receives signal and bit error rate detection
The serial differential signals Dinp and Dinn sent by step 1 is sent to serial link receiving device by channel
In Receiver, the sample circuit I2 sampled signals of receiver turn by string and export parallel data after circuit I 3.Parallel data
Into in the data detection circuit I4 in data detection circuit, produce the data that circuit is produced to be contrasted by with pattern, lead to
The accumulation of a certain amount of data is crossed, so as to calculate the corresponding bit error rate；
3] clock phase scanning
The one sampling period is divided into several pieces by the sampling clock of sample circuit by phase difference value circuit I 6, each
Part corresponds to the minimum control bit of its control routine Pctrl, when receiving data, phase difference is opened or closed according to same direction polarity
It is worth the control routine of circuit, incremental (or successively decreasing) minimum control bit carrys out the phase of scanning sample clock every time；
4] input data minimum differential amplitude control
The output direct current signal that difference DAC I5 are not waited by the change output difference amplitude of control routine Dctrl, it is total to
Mode voltage keeps immobilizing.The serial differential data of serial link receiving device after ac coupling capacitor C1 and C2 by removing it
The DC information of signal, the output of difference DAC is connected on the signal after AC coupled so that the differential serial data of input
Common-mode voltage is equal to the differential voltage of DAC outputs.Increase or reduce the control bit of DAC by each same direction to change input
The common mode deviation of differential serial signals, so as to change the minimum differential amplitude of input data.
5] input data minimum differential amplitude traversal and error rate analyzer
When step 2 receives data, often change a sampling clock phase, difference DAC control codes are completed according to step 4
Once travel through, a minimum control bit is changed every time, reversing at same direction is now detected according to the bit error rate of step 2
Calculate when DAC control codes often change one time the corresponding bit error rate and record.
6] sampling clock phase traversal and error rate analyzer
After step 5 terminates the control code traversal of DAC, according to one phase difference value of step 3 same direction reversing
The minimum control bit of circuit, then travel through the control code of DAC by step 5, while calculate the corresponding bit error rate and store, so after
It is continuous, until phase difference value circuit control code traversal terminates.
7] signal quality oscillography in piece
At the end of step 6, by the corresponding minimum differential amplitude of DAC control codes and the corresponding phase-group of phase difference value circuit
Into two-dimensional coordinate depict, and read the corresponding bit error rate in each coordinate points, you can complete with the bit error rate as reference
Piece in signal oscillography.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
The present invention has been described in detail, it will be understood by those within the art that：It still can be to foregoing each implementation
Technical scheme described in example is modified, or carries out equivalent to which part technical characteristic；And these modification or
Replace, do not make the spirit and scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution.
Claims (2)
1. signal quality oscillography circuit in a kind of serial link piece, it is characterised in that：
Pattern including being sequentially connected produces circuit I 1, sample circuit I2, string to turn and circuit I 3, data detection circuit I4, also wraps
Include ac coupling capacitor C1 and C2, difference DAC-circuit I5, phase difference value circuit I 6；
The pattern produces circuit I 1 to generate specific periodicity serial differential signals and exported by differential channel Ch1 and Ch2；
The ac coupling capacitor C1 and C2 is located at the differential channel Ch1 between pattern generation circuit I 1 and sample circuit I2 respectively
On Ch2, for removing the DC information in serial differential signals；
The difference DAC-circuit I5 according to DAC control codes, output difference amplitude not wait output direct current signal, it is poor to be respectively connected to
Divide channel Ch1 and Ch2；
The phase difference value circuit I 6 exports clock output and arrives according to the phase of phase difference value circuit control code scanning sample clock
On the clock of sample circuit；
The sample circuit I2 samples to the serial signal being input into；
The data detection circuit enters the string turn serial data that simultaneously parallel data of circuit output is produced with pattern generation circuit
Row contrast, calculates the corresponding bit error rate.
2. signal quality oscillometric method in a kind of serial link piece, it is characterised in that comprise the following steps：
1] specific pattern is produced：
Pattern produces circuit to directly generate specific periodicity parallel signal, by output difference after the transmitter string of serial link
Sub-signal (Dinp, Dinn), or specific periodicity serial signal is generated, exported by driver；
2] DC information is removed：
Serial differential signals remove DC information therein by ac coupling capacitor C1 and C2；
3] control of signal sampling：
3.1] input data minimum differential amplitude control：
Difference DAC passes through the direct current signal that the change output difference amplitude of control routine is not waited, and is connected to the string after AC coupled
On row signal so that the common-mode voltage of the differential serial signals of input is equal to the differential voltage of DAC outputs；By each same side
To polarity increase or reduce the control bit of DAC and change the common mode deviation of input difference serial signal, so as to change input number
According to minimum differential amplitude；
3.2] clock phase scanning：
The one sampling period is divided into several pieces by the sampling clock of sample circuit by phase difference value circuit, per a correspondence
The minimum control bit of its control routine, when receiving serial signal, phase difference value electricity is opened or closed according to unidirectional polarity
The control routine on road, is incremented by the phase that a minimum control bit carrys out scanning sample clock every time；
4] signal sampling, the data after sampling turn by string and export parallel data after circuit；Signal sampling therein it is specific
Step is as follows：
4.1] input data minimum differential amplitude traversal：
When sample circuit receives data, often change a sampling clock phase, the one of difference DAC control codes is completed according to step 3.1
Secondary traversal, changes a minimum control bit every time, and reversing at same direction, detection DAC control codes often change a phase
The bit error rate answered simultaneously is recorded；
4.2] sampling clock phase traversal：
After step 4.1 terminates the control code traversal of DAC, according to one phase difference value of step 4.1 same direction reversing
The minimum control bit of circuit, then travel through the control code of DAC by step 4.1, so continue, until phase difference value circuit control code
Traversal terminates；
5] error rate analyzer：
Parallel data enters in data detection circuit, produces the serial data that circuit is produced to be contrasted by with pattern, passes through
Data accumulation, so as to calculate the corresponding bit error rate；
Parallel data produces the serial data that circuit is produced to be contrasted by turn in data detection circuit with pattern, if contrast
Result is consistent, and error number is zero；
If comparing result is inconsistent, error number adds one, until contrast to last position, obtains total error number；
The bit error rate=total error number/total amount of data；
6] signal quality oscillography in piece：
At the end of step 5, the corresponding minimum differential amplitude of DAC control codes and the corresponding phase of phase difference value circuit are constituted
Two-dimensional coordinate is depicted, and reads the corresponding bit error rate in each coordinate points, you can complete the piece with the bit error rate as reference
The oscillography of interior signal.
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| CN106330596A (en) * | 2015-07-03 | 2017-01-11 | 中兴通讯股份有限公司 | Signal detection method and signal detection device |
| CN106707053B (en) * | 2016-11-15 | 2019-04-30 | 中国电子科技集团公司第四十一研究所 | A kind of system and method improving vector network analyzer high-speed link power of test |
| CN111371468B (en) * | 2020-03-24 | 2021-07-23 | 上海格巍半导体有限公司 | Signal transmitting circuit, signal receiving circuit and electronic equipment for serial communication |
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Effective date of registration: 20221202 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No.15, Jinye 2nd Road, Xi'an, Shaanxi 710119 Patentee before: 631ST Research Institute OF AVIC |