CN104485280A - Method for manufacturing grid electrode - Google Patents
Method for manufacturing grid electrode Download PDFInfo
- Publication number
- CN104485280A CN104485280A CN201410853051.9A CN201410853051A CN104485280A CN 104485280 A CN104485280 A CN 104485280A CN 201410853051 A CN201410853051 A CN 201410853051A CN 104485280 A CN104485280 A CN 104485280A
- Authority
- CN
- China
- Prior art keywords
- wsi
- grid electrode
- side wall
- layer
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 9
- 239000000377 silicon dioxide Substances 0.000 abstract description 9
- 229910052681 coesite Inorganic materials 0.000 abstract 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract 5
- 229910052682 stishovite Inorganic materials 0.000 abstract 5
- 229910052905 tridymite Inorganic materials 0.000 abstract 5
- 238000001259 photo etching Methods 0.000 abstract 2
- 239000003990 capacitor Substances 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 abstract 1
- 230000008961 swelling Effects 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for manufacturing a grid electrode. The method includes the steps that (1) polycrystalline silicon, a first WSi layer, a first SiO2 layer, a second WSi layer and a second SiO2 layer are sequentially deposited on a substrate according to a conventional method; (2) photoetching is conducted for the first time, and an MIP capacitor is formed at a field oxide area; (3) photoetching is conducted for the second time, and the grid electrode is formed at an active area; (4) N2 is connected in for conducting thermal annealing; (5) grid electrode side wall SiO2 is deposited. According to the method, the nitrogen annealing step is additionally executed before the side wall SiO2 is deposited, the damaged WSi on the grid electrode surface is repaired, and the swelling problem of the side wall of the grid electrode due to the fact that the WSi is oxidized into WOx when the side wall SiO2 is deposited is solved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to the manufacture craft of grid.
Background technology
In semiconductor fabrication, gate surface WSi (tungsten silicide) is if be etched early stage, bulge can be produced after follow-up side wall silicon dioxide deposition, affect HCI (hot carrier injection, hot carrier injection effect), unfavorable to the program capability of OTP (One Time Programmable) device especially.Such as, shown in Figure 1, in MIP electric capacity etching process, the WSi of polysilicon surface sustains damage, and the associative key of polysilicon surface WSi is destroyed, and causes follow-up side wall SiO
2during deposit, WSi is oxidized, generates WOx (tungsten oxide) bulge, and as shown in Figure 2, WOx bulge makes side wall become large, as shown in Figure 3, affects HCI, causes OTP to lose efficacy (see Fig. 4).
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method of grid, and it can avoid grid curb wall to produce bulge.
For solving the problems of the technologies described above, the manufacture method of grid of the present invention, step comprises:
1) conventionally depositing polysilicon, ground floor WSi, ground floor SiO successively on substrate
2, second layer WSi, second layer SiO
2;
2) first time chemical wet etching, oxygen district on the scene forms MIP electric capacity;
3) second time chemical wet etching, forms grid in active area;
4) N is passed into
2carry out thermal annealing;
5) deposit grid curb wall SiO
2.
The temperature of above-mentioned thermal annealing is 700 ~ 800 DEG C, and the flow of nitrogen is for being more than or equal to 25L/min.
The present invention by adding a step n 2 annealing step before side wall silicon dioxide deposition, and repair the tungsten silicon that gate surface is impaired, like this, when deposit side wall silicon dioxide, WSi would not be oxidized to WOx, thus avoids the formation of WOx bulge.
Accompanying drawing explanation
Fig. 1 makes in gate process, the etching process schematic diagram of MIP electric capacity.
Fig. 2 is that the WSi of polysilicon surface sustains damage when MIP electric capacity etches, follow-up side wall SiO
2during deposit, WSi is oxidized to WOx and forms bulge.
Fig. 3 is that WOx bulge causes SiO
2side wall becomes large.Wherein, a figure is the side wall size do not had in WOx bulge situation, and b figure is the side wall size had in WOx bulge situation.
Fig. 4 is CP (Circuit Probing, the wafer sort) figure had in WOx bulge situation.
Fig. 5 is N
2when flow is 20L/min, still have a small amount of bulge.
Fig. 6 is N
2after increased flow capacity to 25L/min, occur without bulge.
Embodiment
Understand more specifically for having technology contents of the present invention, feature and effect, now by reference to the accompanying drawings, details are as follows:
The manufacture method of CMOS (complementary metal oxide semiconductors (CMOS)) grid of the present embodiment, specifically comprises following processing step:
Step 1, conventionally depositing polysilicon, ground floor WSi, ground floor SiO successively on substrate
2, second layer WSi, second layer SiO
2.
Step 2, for the first time chemical wet etching, oxygen district on the scene forms MIP electric capacity.
Step 3, second time chemical wet etching, forms grid in active area.
Above step 1 ~ step 3 can be shown in Figure 1.
Step 4, passes into N
2carry out thermal annealing, to repair ground floor WSi.
The temperature of thermal annealing is 700 ~ 800 DEG C.
During thermal annealing, the flow of nitrogen needs to be more than or equal to 25L/min, is involved in that (if there is air to be involved in, the WSi that air can be etched with surface reacts and generates bulge, as can see from Figure 5, works as N to prevent air
2when flow is 20L/min, still have a small amount of bulge).
Step 5, deposit grid curb wall SiO
2.
After increasing n 2 annealing step, the impaired tungsten silicon of gate surface obtains reparation, during follow-up side wall silicon dioxide deposition, does not just occur WOx bulge, as shown in Figure 6.
Claims (3)
1. the manufacture method of grid, is characterized in that, step comprises:
1) conventionally depositing polysilicon, ground floor WSi, ground floor SiO successively on substrate
2, second layer WSi, second layer SiO
2;
2) first time chemical wet etching, oxygen district on the scene forms MIP electric capacity;
3) second time chemical wet etching, forms grid in active area;
4) N is passed into
2carry out thermal annealing;
5) deposit grid curb wall SiO
2.
2. method according to claim 1, is characterized in that, step 4), the temperature of thermal annealing is 700 ~ 800 DEG C.
3. method according to claim 1, is characterized in that, step 4), the flow of nitrogen is for being more than or equal to 25L/min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410853051.9A CN104485280A (en) | 2014-12-31 | 2014-12-31 | Method for manufacturing grid electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410853051.9A CN104485280A (en) | 2014-12-31 | 2014-12-31 | Method for manufacturing grid electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104485280A true CN104485280A (en) | 2015-04-01 |
Family
ID=52759816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410853051.9A Pending CN104485280A (en) | 2014-12-31 | 2014-12-31 | Method for manufacturing grid electrode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104485280A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5756392A (en) * | 1997-01-22 | 1998-05-26 | Taiwan Semiconductor Manuacturing Company, Ltd. | Method of formation of polycide in a semiconductor IC device |
| US5946599A (en) * | 1997-07-24 | 1999-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor IC device |
| CN101853811A (en) * | 2009-04-03 | 2010-10-06 | 世界先进积体电路股份有限公司 | Method for manufacturing semiconductor device |
| CN103730344A (en) * | 2012-10-12 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Method for forming silicon oxide side wall of gate of metal tungsten silicide |
-
2014
- 2014-12-31 CN CN201410853051.9A patent/CN104485280A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5756392A (en) * | 1997-01-22 | 1998-05-26 | Taiwan Semiconductor Manuacturing Company, Ltd. | Method of formation of polycide in a semiconductor IC device |
| US5946599A (en) * | 1997-07-24 | 1999-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor IC device |
| CN101853811A (en) * | 2009-04-03 | 2010-10-06 | 世界先进积体电路股份有限公司 | Method for manufacturing semiconductor device |
| CN103730344A (en) * | 2012-10-12 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Method for forming silicon oxide side wall of gate of metal tungsten silicide |
Non-Patent Citations (1)
| Title |
|---|
| 董颖: "硅化钨MIP电容侧墙淀积工艺优化", 《微电子学》 * |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150401 |
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| RJ01 | Rejection of invention patent application after publication |