CN109994479A - The manufacturing method and disposal programmable device of disposal programmable device - Google Patents
The manufacturing method and disposal programmable device of disposal programmable device Download PDFInfo
- Publication number
- CN109994479A CN109994479A CN201910263249.4A CN201910263249A CN109994479A CN 109994479 A CN109994479 A CN 109994479A CN 201910263249 A CN201910263249 A CN 201910263249A CN 109994479 A CN109994479 A CN 109994479A
- Authority
- CN
- China
- Prior art keywords
- silicon nitride
- nitride layer
- programmable device
- layer
- base area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The present invention provides a kind of manufacturing method of disposal programmable device, the step of manufacturing disposal programmable device includes: to provide a substrate, is formed with first grid structure, the first sidewall structure, second grid structure and the second sidewall structure on the substrate；Silicon oxide layer is formed on the second grid structure, the second side wall；The first silicon nitride layer is formed on the silicon oxide layer；The second silicon nitride layer is formed on first silicon nitride layer, the first grid structure, the first sidewall structure.Wherein, the silicon oxide layer and first silicon nitride layer constitute the barrier layer of an ON structure; the disposal programmable device is under the barrier layer of the ON structure and the duplicate protection of second silicon nitride layer; it can be lost to avoid the electronics stored in the second grid structure or with cation, positive defect and hole there is a situation where neutralizing, improve the data holding ability of the disposal programmable device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the manufacturing method of a kind of disposal programmable device and primary
Property programming device.
Background technique
Disposal programmable device (OTP) is a kind of memory device, due to its simple process, low in cost and be widely applied
In various semiconductor products.The amendment of the simulation electronic product of the as low as several bit grades of the application range of OTP arrives data or generation greatly
The kilobit member grade of code storage.
Data holding ability is one of the important parameter of OTP performance superiority and inferiority, and OTP generally utilizes channel hot electron injection effect
It answers, thermoelectron is made to penetrate gate oxide and is stored in the grid of CMOS transistor, so that the threshold voltage of transistor occurs partially
It moves, to carry out distinguishing state to control the switch of CMOS, i.e., so-called " 1 " and " 0 " realizes that data storage and data are kept, but
It is current OTP due to the electronics stored in grid is lost over time or with cation, positive defect, hole generation neutralization
There are the insufficient defects of data holding ability.
Summary of the invention
The purpose of the present invention is to provide a kind of manufacturing method of disposal programmable device and disposal programmable device,
To solve the problems, such as that disposal programmable device holding capacity is insufficient.
In order to solve the above technical problems, the present invention provides a kind of manufacturing method of disposal programmable device, it is described primary
The manufacturing method of property programming device includes:
A substrate is provided, the substrate includes the first base area and the second base area, is formed with the first grid on first base area
Pole structure is formed with second grid structure on second base area；
Silicon oxide layer is formed, the silicon oxide layer covers the second grid structure and second base area；
The first silicon nitride layer is formed, first silicon nitride layer covers the silicon oxide layer, wherein first silicon nitride
Layer and the silicon oxide layer constitute the barrier layer of an ON structure；
The second silicon nitride layer is formed, second silicon nitride layer covers first silicon nitride layer, the first grid knot
Structure and first base area.
Optionally, in the manufacturing method of the disposal programmable device, the first gold medal is formed on first base area
Belong to silicide layer, the first grid structure is located on first metal silicide layer.
Optionally, in the manufacturing method of the disposal programmable device, the first grid structure includes the first grid
Electrode and the second metal silicide layer in the first gate electrode.
Optionally, in the manufacturing method of the disposal programmable device, the thickness of the silicon oxide layer betweenThe thickness of first silicon nitride layer between
Optionally, in the manufacturing method of the disposal programmable device, using sub-atmospheric pressure chemical vapor deposition work
Skill forms the silicon oxide layer.
Optionally, heavy using plasma enhanced chemical gas phase in the manufacturing method of the disposal programmable device
Product technique forms first silicon nitride layer.
Optionally, in the manufacturing method of the disposal programmable device, after forming first silicon nitride layer
And before forming second silicon nitride layer, the manufacturing method of the disposal programmable device further include:
Thermal annealing is carried out using the first silicon nitride layer described in ultraviolet light, and to first silicon nitride layer.
Optionally, in the manufacturing method of the disposal programmable device, the technological temperature of the thermal annealing is between 500
DEG C~550 DEG C.
Optionally, in the manufacturing method of the disposal programmable device, the stress of second silicon nitride layer is
1.45Gpa~1.55Gpa.
Optionally, heavy using plasma enhanced chemical gas phase in the manufacturing method of the disposal programmable device
Long-pending mode forms second silicon nitride layer.
Optionally, in the manufacturing method of the disposal programmable device, the technique of formation second silicon nitride layer
Temperature is between 350 DEG C~550 DEG C.
The present invention also provides a kind of disposal programmable devices, comprising:
Substrate, the substrate include the first base area and the second base area, are formed with first grid structure on first base area,
Second grid structure is formed on second base area；
Silicon oxide layer, the silicon oxide layer cover the second grid structure and second base area；
First silicon nitride layer, first silicon nitride layer cover the silicon oxide layer, wherein first silicon nitride layer and
The silicon oxide layer constitutes the barrier layer of an ON structure；And
Second silicon nitride layer, second silicon nitride layer cover first silicon nitride layer, the first grid structure and
First base area.
In conclusion silicon oxide layer is formed the present invention provides a kind of manufacturing method of disposal programmable device, it is described
Silicon oxide layer covers the second grid structure；Then, the first silicon nitride layer is formed on the silicon oxide layer；Then, in institute
It states and forms the second silicon nitride layer on the first silicon nitride layer, wherein the silicon oxide layer and first silicon nitride layer constitute an ON
The barrier layer of structure, the disposal programmable device the ON structure barrier layer and second silicon nitride layer it is dual
Under protection, it can be lost to avoid the electronics stored in the second grid structure or be sent out with cation, positive defect and hole
Raw the case where neutralizing, to improve the data holding ability of the disposal programmable device.
Detailed description of the invention
Fig. 1-Fig. 2 is semiconductor structure signal of the disposal programmable device of the embodiment of the present invention in each processing step
Figure；
Wherein,
100- substrate, the first base area 101-, the second base area 102-, 110- first grid structure, 111- first gate electrode,
The second metal silicide layer of 112-, the first sidewall structure of 130-, the first metal silicide layer of 140-, 210- second grid structure,
The second sidewall structure of 220-, 230- silicon oxide layer, the first silicon nitride layer of 240-, the second silicon nitride layer of 300-.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to the manufacturing method of disposal programmable device proposed by the present invention and one
Secondary property programming device is described in further detail.According to following explanation and claims, advantages and features of the invention will
It becomes apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to convenient, bright
The purpose of the embodiment of the present invention is aided in illustrating clearly.In addition, the structure that attached drawing is shown is often a part of practical structures.It is special
Other, the emphasis that each attached drawing needs to show is different, uses different ratios sometimes.
The present invention provides a kind of manufacturing method of disposal programmable device, the manufacturer of the disposal programmable device
Method includes:
A substrate is provided, the substrate includes the first base area and the second base area, is formed with the first grid on first base area
Pole structure is formed with second grid structure on second base area；
Silicon oxide layer is formed, the silicon oxide layer covers the second grid structure and second base area；
The first silicon nitride layer is formed, first silicon nitride layer covers the silicon oxide layer, wherein first silicon nitride
Layer and the silicon oxide layer constitute the barrier layer of an ON structure；
The second silicon nitride layer is formed, second silicon nitride layer covers first silicon nitride layer, the first grid knot
Structure and first base area.
Further, Fig. 1-Fig. 2 is please referred to, Fig. 1-Fig. 2 is the disposal programmable device of the embodiment of the present invention in each work
Semiconductor structure schematic diagram in skill step.
Firstly, providing a substrate 100 with reference to Fig. 1, the substrate 100 includes the first base area 101 and the second base area 102, institute
It states and is formed with first grid structure 110 on the first base area 101, be formed with second grid structure 210 on second base area 102.
Specifically, in the present embodiment, the first grid structure 110 is control gate, the second grid structure 210 is floating gate.
Further, the first sidewall structure 130, first sidewall structure 130 are also formed on first base area 101
Positioned at the two sides of the first grid structure 110；It is also formed with the second sidewall structure 230 on second base area 102, described
Two sidewall structures 230 are located at the two sides of the second grid structure 210.
Preferably, the first metal silicide layer 140, the first grid structure 110 are formed on first base area 101
On first metal silicide layer 140.Wherein, first metal silicide layer 140 is subsequent contact hole and institute
It states and the Ohmic contact of a metal and semiconductor is provided between the first base area 101, the metal being subsequently formed can be reduced and mutually linked
The resistance of structure.
The first grid structure 110 includes first gate electrode 111 and the second gold medal in the first gate electrode 111
Belong to silicide layer 112, wherein the material of the gate electrode 111 is, for example, the chemical combination of polysilicon, metal or polysilicon and metal
Object.
Then, as shown in Figure 1, in the first grid structure 110, first sidewall structure 130, first base area
101, the silicon oxide layer is formed on the second grid structure 210, the second sidewall structure 230 and second base area 102
230, then using dry etch process etching be located at 110 surface of first grid structure, 130 surface of the first sidewall structure and
The silicon oxide layer 230 on first base area 101 is only to be covered the second grid structure 210 and second base
The silicon oxide layer 230 in area 102, specifically, formed the silicon oxide layer 230 thickness between?
In the present embodiment, the silicon oxide layer 230 is deposited using sub-atmospheric pressure chemical vapor deposition process, wherein reaction pressure Gao Jie
Between 30Torr~600Torr, reaction temperature between 280 DEG C~320 DEG C, meanwhile, be passed through tetraethyl silane (TEOS)
With ozone (O3) participate in the depositing operation of the silicon oxide layer 230.Further, it is located at the first grid knot in dry etching
When the silicon oxide layer 230 on 110 surface of structure, 130 surface of the first sidewall structure and first base area 101, it is passed through Cl2、
Ar、CHF3Participate in etching.
Then, as shown in Figure 1, on the silicon oxide layer 230,110 surface of first grid structure, first side
130 surface of wall construction and 101 surface of the first base area form the first silicon nitride layer 240, are then carved using dry etch process
Eating away is located at 110 surface of first grid structure, 130 surface of the first sidewall structure and 101 surface of the first base area
The first silicon nitride layer 240, only to be covered first silicon nitride layer 240 of the silicon oxide layer 230, wherein described
First silicon nitride layer 240 and the silicon oxide layer 230 constitute the barrier layer of an ON structure.The silicon oxide layer 230 and described
One silicon nitride layer 240 constitutes the barrier layer of an ON structure, and the disposal programmable device is protected on the barrier layer of the ON structure
Under shield, the electronics stored in the second grid structure can be effectively prevented and be lost, improve the disposal programmable device
Data holding ability.Specifically, the thickness of first silicon nitride layer 240 between Using plasma
Enhanced chemical vapor deposition processes form first silicon nitride layer 240, while being passed through SiH4, NH3, N2O and N2Described in participation
The depositing operation of first silicon nitride layer 240.Further, it is located at 110 surface of first grid structure, described in dry etching
When first silicon nitride layer 240 on 130 surface of the first sidewall structure and 101 surface of the first base area, it is passed through Cl2、BCl2、Ar、
CHF3Participate in etching.
Further, using the first silicon nitride layer 240 described in ultraviolet light, and to first silicon nitride layer 240 into
Row thermal annealing, and the technological temperature of the thermal annealing is between 500 DEG C~550 DEG C.
Then, with reference to Fig. 2, the second silicon nitride layer 300 is formed, second silicon nitride layer 300 covers first nitridation
Silicon layer 240, the first grid structure 110, first sidewall structure 130 and first base area 101.Specifically, described
The stress of second silicon nitride layer 300 is 1.45Gpa~1.55Gpa, in the present embodiment, using plasma enhanced chemical gas phase
The mode of deposition forms second silicon nitride layer 300, and the technological temperature control for depositing second silicon nitride layer 300 is existed
Between 350 DEG C~550 DEG C, by the lower reaction pressure between 2~10Torr, and it is passed through SiH4,2NH3, N2 ginseng
With depositing operation, and the power by adjusting radio-frequency signal generator obtains heavily stressed second silicon nitride layer 300.High stress
Second silicon nitride layer 300 can further avoid the electronics of the inner storage of the second grid structure 210 from being lost, improve
The reliability of the disposal programmable device.Because the electronics stored in the second grid structure 210 is feminine gender, hold
It is easily neutralized with positive defect, to cause the electronics stored in the second grid structure 210 to be lost, in addition, described the
In the case that protective layer of the electronics stored in two gate structures 210 on its surface is weaker, in addition can with outside protective layer
There is a situation where neutralize for cation and hole.The protective layer of the second grid structure 210 in the present invention is the equal of institute
Silicon oxide layer 230, first silicon nitride layer 240 and second silicon nitride layer 300 this three layers combination are stated, so described one
Secondary property programming device is in the barrier layer (silicon oxide layer 230 and first silicon nitride layer 240) of the ON structure and institute
Under the duplicate protection for stating the second silicon nitride layer 300, can to avoid the electronics of the inner storage of the second grid structure 210 be lost or
With cation, positive defect and hole there is a situation where neutralizing, so that the data for improving the disposal programmable device are protected
Hold ability.
The present invention also provides a kind of disposal programmable devices, comprising:
Substrate 100, the substrate 100 include the first base area 101 and the second base area 102, are formed on first base area 101
There is first grid structure 110, is formed with second grid structure 210 on second base area 102；
Silicon oxide layer 230, the silicon oxide layer 230 cover the second grid structure 210 and second base area 102；
First silicon nitride layer 240, first silicon nitride layer 240 cover the silicon oxide layer 230, wherein described first
Silicon nitride layer 240 and the silicon oxide layer 230 constitute the barrier layer of an ON structure；And
Second silicon nitride layer 300, second silicon nitride layer 300 cover first silicon nitride layer 240, the first grid
Pole structure 110 and first base area 101.
In conclusion silicon oxide layer is formed the present invention provides a kind of manufacturing method of disposal programmable device, it is described
Silicon oxide layer covers the second grid structure；Then, the first silicon nitride layer is formed on the silicon oxide layer；Then, in institute
It states and forms the second silicon nitride layer on the first silicon nitride layer, wherein the silicon oxide layer and first silicon nitride layer constitute an ON
The barrier layer of structure, the disposal programmable device the ON structure barrier layer and second silicon nitride layer it is dual
Under protection, it can be lost to avoid the electronics stored in the second grid structure or be sent out with cation, positive defect and hole
Raw the case where neutralizing, to improve the data holding ability of the disposal programmable device.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (12)
1. a kind of manufacturing method of disposal programmable device, which is characterized in that the manufacturer of the disposal programmable device
Method includes:
A substrate is provided, the substrate includes the first base area and the second base area, is formed with first grid knot on first base area
Structure is formed with second grid structure on second base area；
Silicon oxide layer is formed, the silicon oxide layer covers the second grid structure and second base area；
Form the first silicon nitride layer, first silicon nitride layer covers the silicon oxide layer, wherein first silicon nitride layer and
The silicon oxide layer constitutes the barrier layer of an ON structure；
Form the second silicon nitride layer, second silicon nitride layer cover first silicon nitride layer, the first grid structure and
First base area.
2. the manufacturing method of disposal programmable device according to claim 1, which is characterized in that on first base area
It is formed with the first metal silicide layer, the first grid structure is located on first metal silicide layer.
3. the manufacturing method of disposal programmable device according to claim 1, which is characterized in that the first grid knot
Structure includes first gate electrode and the second metal silicide layer in the first gate electrode.
4. the manufacturing method of disposal programmable device according to claim 1, which is characterized in that the silicon oxide layer
Thickness betweenThe thickness of first silicon nitride layer between
5. the manufacturing method of disposal programmable device according to claim 4, which is characterized in that use sub-atmospheric pressure
It learns gas-phase deposition and forms the silicon oxide layer.
6. the manufacturing method of disposal programmable device according to claim 4, which is characterized in that enhanced using plasma
Type chemical vapor deposition process forms first silicon nitride layer.
7. the manufacturing method of disposal programmable device according to claim 1, which is characterized in that forming described first
After silicon nitride layer and before forming second silicon nitride layer, the manufacturing method of the disposal programmable device is also wrapped
It includes:
Thermal annealing is carried out using the first silicon nitride layer described in ultraviolet light, and to first silicon nitride layer.
8. the manufacturing method of disposal programmable device according to claim 7, which is characterized in that the work of the thermal annealing
Skill temperature is between 500 DEG C~550 DEG C.
9. the manufacturing method of disposal programmable device according to claim 1, which is characterized in that second silicon nitride
The stress of layer is 1.45Gpa~1.55Gpa.
10. the manufacturing method of disposal programmable device according to claim 9, which is characterized in that increased using plasma
The mode of strong type chemical vapor deposition forms second silicon nitride layer.
11. the manufacturing method of disposal programmable device according to claim 10, which is characterized in that form described second
The technological temperature of silicon nitride layer is between 350 DEG C~550 DEG C.
12. a kind of disposal programmable device characterized by comprising
Substrate, the substrate include the first base area and the second base area, are formed with first grid structure on first base area, described
Second grid structure is formed on second base area；
Silicon oxide layer, the silicon oxide layer cover the second grid structure and second base area；
First silicon nitride layer, first silicon nitride layer cover the silicon oxide layer, wherein first silicon nitride layer and described
Silicon oxide layer constitutes the barrier layer of an ON structure；And
Second silicon nitride layer, second silicon nitride layer cover first silicon nitride layer, the first grid structure and described
First base area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910263249.4A CN109994479A (en) | 2019-04-02 | 2019-04-02 | The manufacturing method and disposal programmable device of disposal programmable device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910263249.4A CN109994479A (en) | 2019-04-02 | 2019-04-02 | The manufacturing method and disposal programmable device of disposal programmable device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109994479A true CN109994479A (en) | 2019-07-09 |
Family
ID=67132079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910263249.4A Pending CN109994479A (en) | 2019-04-02 | 2019-04-02 | The manufacturing method and disposal programmable device of disposal programmable device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109994479A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038342A (en) * | 2020-08-14 | 2020-12-04 | 华虹半导体(无锡)有限公司 | OTP (one time programmable) device and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100096685A1 (en) * | 2006-10-12 | 2010-04-22 | Jiang Yan | Strained Semiconductor Device and Method of Making Same |
| CN102427066A (en) * | 2011-12-05 | 2012-04-25 | 上海先进半导体制造股份有限公司 | One-time programmable read-only memory for CMOS (Complementary Metal Oxide Semiconductor) and manufacturing method thereof |
| CN103943570A (en) * | 2014-03-20 | 2014-07-23 | 上海华力微电子有限公司 | Preparation method for metal silicide mask in OTP memory |
-
2019
- 2019-04-02 CN CN201910263249.4A patent/CN109994479A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100096685A1 (en) * | 2006-10-12 | 2010-04-22 | Jiang Yan | Strained Semiconductor Device and Method of Making Same |
| CN102427066A (en) * | 2011-12-05 | 2012-04-25 | 上海先进半导体制造股份有限公司 | One-time programmable read-only memory for CMOS (Complementary Metal Oxide Semiconductor) and manufacturing method thereof |
| CN103943570A (en) * | 2014-03-20 | 2014-07-23 | 上海华力微电子有限公司 | Preparation method for metal silicide mask in OTP memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038342A (en) * | 2020-08-14 | 2020-12-04 | 华虹半导体(无锡)有限公司 | OTP (one time programmable) device and forming method thereof |
| CN112038342B (en) * | 2020-08-14 | 2022-12-27 | 华虹半导体(无锡)有限公司 | OTP device forming method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10879462B2 (en) | Devices including multi-portion liners | |
| CN108538712B (en) | Method for manufacturing contact hole | |
| US8350311B2 (en) | Semiconductor device | |
| US7320919B2 (en) | Method for fabricating semiconductor device with metal-polycide gate and recessed channel | |
| US20070013070A1 (en) | Semiconductor devices and methods of manufacture thereof | |
| CN110391247B (en) | Semiconductor element and manufacturing method thereof | |
| CN109994479A (en) | The manufacturing method and disposal programmable device of disposal programmable device | |
| CN103794502A (en) | Semiconductor device and manufacturing method thereof | |
| US20180211922A1 (en) | Semiconductor device including conductive structure having nucleation structure and method of forming the same | |
| US8569173B2 (en) | Methods of protecting elevated polysilicon structures during etching processes | |
| CN103839806B (en) | Semiconductor devices and its manufacture method | |
| CN107492572B (en) | Semiconductor transistor element and manufacturing method thereof | |
| US20150249010A1 (en) | Semiconductor device and method of manufacturing same | |
| TW200403763A (en) | Manufacturing method of semiconductor integrated circuit device | |
| KR20150064330A (en) | Semiconductor devices and methods of manufacturing the same | |
| CN108573911A (en) | Semiconductor structure and forming method thereof | |
| CN105336784A (en) | Semiconductor device and manufacturing method thereof | |
| US9431408B2 (en) | Methods for fabricating integrated circuits with a high-voltage MOSFET | |
| CN110391185B (en) | Method for manufacturing semiconductor element | |
| US10204914B2 (en) | Method for fabricating semiconductor device | |
| US6974989B1 (en) | Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing | |
| CN106298676A (en) | Method for manufacturing semiconductor element | |
| KR20080002602A (en) | Method for forming a gate of semiconductor device having dual gate | |
| KR101129021B1 (en) | Method for fabricating transistor in semiconductor device | |
| KR100548579B1 (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190709 |