CN104471593B - 功能嵌体的制造方法 - Google Patents

功能嵌体的制造方法 Download PDF

Info

Publication number
CN104471593B
CN104471593B CN201280074655.2A CN201280074655A CN104471593B CN 104471593 B CN104471593 B CN 104471593B CN 201280074655 A CN201280074655 A CN 201280074655A CN 104471593 B CN104471593 B CN 104471593B
Authority
CN
China
Prior art keywords
chip
antenna
supporting layer
retainer member
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201280074655.2A
Other languages
English (en)
Other versions
CN104471593A (zh
Inventor
S·阿雅拉
U·弗特
L·佩拉达
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Assa Abloy AB
Original Assignee
Assa Abloy AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Assa Abloy AB filed Critical Assa Abloy AB
Publication of CN104471593A publication Critical patent/CN104471593A/zh
Application granted granted Critical
Publication of CN104471593B publication Critical patent/CN104471593B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773Antenna details
    • G06K19/07777Antenna details the antenna being of the inductive type
    • G06K19/07779Antenna details the antenna being of the inductive type the inductive antenna being a coil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G06K19/07754Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna the connection being galvanic
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773Antenna details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4885Wire-like parts or pins
    • H01L21/4889Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2208Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
    • H01Q1/2225Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/753Means for applying energy, e.g. heating means by means of pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/753Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301Bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7565Means for transporting the components to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75743Suction holding means
    • H01L2224/75745Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758Means for moving parts
    • H01L2224/75801Lower part of the bonding apparatus, e.g. XY table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758Means for moving parts
    • H01L2224/75841Means for moving parts of the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/781Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • H01L2224/78101Chamber
    • H01L2224/78102Vacuum chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/787Means for aligning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Details Of Aerials (AREA)

Abstract

制造功能嵌体的方法包括步骤:‑)提供具有至少第一侧和第二侧的支撑层;‑)在所述支撑层中嵌入线型天线;‑)在连接站处理具有所述嵌入的线型天线的所述支撑层,其中‑)所述支撑层在所述第一侧上由保持器件靠近,该保持器件保持具有包括连接垫的表面的芯片;‑)所述支撑层在所述第二侧上由连接器件靠近;并且‑)通过在所述保持器件和所述连接器件之间施加的相反压力将所述天线导线连接至所述连接垫。

Description

功能嵌体的制造方法
技术领域
本发明涉及RFID器件领域,其包括通过直接键合而与芯片连接的天线。
更具体地,本发明涉及一种用于将芯片与嵌入在衬底中的线型天线直接键合以形成功能嵌体的方法。
本发明还涉及一种由此处描述的方法制造的功能嵌体。
背景技术
Finn等人的美国专利6,233,818公开了一种制造RFID嵌体的方法。更具体地,该专利公开了一种在制造设置于衬底上并且包括线圈及芯片单元的应答器单元的过程中用于线型导体的接触的方法及器件,芯片单元例如为具有端子区域的芯片模块。借助根据该现有技术中描述的发明的方法,再也不需要为了使芯片单元的端子区域与线圈的终端接触而提供在其上形成了扩展端子区域的单独的接触衬底。更确切地,线圈衬底用作用于线圈的衬底,并且在例如应答器单元是为了服务于芯片卡的制造的情况下,通过与该芯片卡的尺寸对应的塑料支撑片形成线圈衬底,线圈衬底用作接触或定位辅助设备,为线圈的终端和芯片单元的端子区域的相对定位服务。在这种情况下,芯片单元可以为了此目的设置在衬底的凹槽中或者可以提供在衬底的表面上。第一种选择提供可选地在线型导体固定之前在凹槽中设置芯片单元的可能性或者仅在线型导体固定之后在凹槽中引入芯片单元的可能性,目的是随后实施在端子区域上的线型导体的实际接触。
更具体地,在该现有技术中,首先通过接线器件使用超声将天线施加于衬底,以使导线与衬底附着。从而形成具有起始天线区和终端天线区的天线,两个区都横越窗口形状的衬底凹槽。接着,芯片模块放置在凹槽中由此模块的端子接触区域毗邻起始和终端天线区。随后,通过热电极的方法实现端子接触区域和天线的起始及终端天线区之间的电连接,在压力和温度的影响下,热电极通过使线型天线和芯片的端子接触区域之间的材料闭合而产生连接(这也称作热压合)。
EP专利申请2 001 077公开了一种用于制造包括连接到接触垫的应答器天线的器件的方法和一种通过所述方法获得的器件。具体地,提供具有端子连接的天线与衬底接触。接触垫放置在衬底上并且与天线的端子部连接。借助通过在垫和端子部之间引入能量而焊接的方法建立连接。放置垫以提供面向天线端子连接部的表面。该部设置在衬底上并且焊接能量直接施加于垫。在接近天线端子部的衬底中形成空腔,并且微电路至少部分地嵌入在空腔中,并且接触垫定位为面向天线端子部,以及使用热压合或超声实现焊接。为了实现这一焊接步骤,使用穿过与端子部相对的加固片或加固层的砧台,以便在焊接操作过程中提供支撑。这因此使砧台产生了空穴,其必须被仔细地放置以对应于端子部位置。
以上引用的文献中公开的发明事实上(在实际中)全都涉及了芯片模块的用途。按照定义,芯片模块比芯片大得多并且还包括更大的连接垫。用于非接触嵌体的典型芯片模块是NXP的mob6,呈现的表面积是8100x5100μm,厚度是300μm,并且连接垫每个的表面积是1500x 5100μm。
US专利5,572,410公开了一种直接与线型天线连接的芯片。在该专利中,线圈围绕核缠绕并且线圈的两端焊接至芯片的有源层上方沉积的金属路径。被称作“直接键合”的这种技术使生产的应答器的尺寸、构成组件的数量以及相关的制造费用最小化。
作为芯片的普通小型焊垫的扩展的金属路径,称作大凸块(或大焊垫)并且呈现的尺寸适合于连接天线线圈(其典型地呈现直径60-80μm)。例如,这些应用中使用的典型芯片是NXP的Hitagμ,其中芯片表面积是550x550μm,厚度150μm,并且大凸块呈现表面积为294x164μm(而原始焊垫仅60x 60μm)。
还需要注意的是,在该文献中公开的特定的应用中,天线不是嵌入在支撑层中,而是围绕铁芯缠绕。生产的应答器的共振频率为约125kHz并且天线呈现多于300匝。天线不需要精确调试,并且仅需要将天线螺旋圈一个在另一个上高速缠绕。
然而,如果想以更高的频率运行,例如13.56MHz,必须控制每个螺旋圈的形式和相对间距以正确地调试天线。线嵌是制造高频线型天线最有效和流行的技术。但是到目前为止,这是专门通过使用芯片模块来制造。这引入了重要的限制,因为生产的嵌体不能比使用的模块更薄。
制造更薄的高频嵌体是尝试将直接键合和线嵌技术结合的主要动机。
表1是市场上可以用作直接键合的一些高频芯片的列表。和以上描述的NXP的mob6对比,这些芯片呈现小得多的尺寸(不仅是厚度)。
表1:适合于直接键合的高频芯片的例子
问题是当天线线圈固定在大的塑料片上的同时如何适当地处理如此小的芯片。当前对于芯片模块(其比单芯片重得多且大得多)使用的解决方法在如此大规模制造中不再适用。
发明内容
本发明的一个目标是改进已知的器件和方法。
更准确地,本发明的一个目标是通过芯片与嵌入在衬底中的线型天线的直接键合而使制造更薄的RFID嵌体变为可能,芯片例如为RFID芯片。
总体来说,本发明允许得到比芯片厚度与天线厚度之和更薄的高频RFID单层(芯片和天线内置于载体单层本身)
本领域中已知的和将裸芯用作倒装芯片的其他HF RFID技术会更厚,这是由于下述事实:其需要将天线(经蚀刻的天线或经丝网印刷的天线)旋转于其上的不含孔的承载层。在此步骤之后,芯片连接在天线上并且最终的厚度将是芯片厚度+天线厚度+承载层厚度的和。在此情况下,承载层需要被加入层的总厚度,而当使用如本申请中描述的本发明的原则时该缺点不再存在。
根据一个方面,本发明涉及一种将嵌入的线型天线与芯片直接键合的方法,由此该方法允许从一侧保持芯片的同时通过例如焊机头的连接头从另一侧将天线导线与所述芯片连接。
更准确地,该方法包括至少下列步骤:
-)提供具有至少第一侧和第二侧的支撑层;
-)在支撑层中嵌入至少一个线型天线;
-)在连接站处理具有所述嵌入的线型天线的支撑层,其中
-)支撑层在第一侧上由保持器件靠近,该保持器件保持具有包括连接垫的表面的至少一个芯片;
-)支撑层在第二侧上由连接器件靠近;并且
-)通过在保持器件和连接器件之间施加的相反压力将天线导线连接至连接垫。
在该方法中,可以沿着处理路径处理具有导线嵌入的天线的支撑层,并且保持器件和连接器件都可以通过基本垂直于所述处理路径的移动而靠近支撑层。
在该方法的实施例中,连接步骤可以通过热压合完成。
在该方法的实施例中,支撑层包括至少一个贯通孔,在连接步骤过程中或在连接步骤之前不久,通过保持器件将芯片定位在贯通孔中。
在该方法的实施例中,线型天线用于与芯片的连接垫连接的连接部分定位在贯通孔的上方。
在该方法的实施例中,在线型天线嵌入步骤期间,线型天线的连接部分定位在贯通孔的上方。
在实施例中,该方法可以包括附加的步骤,用于在线圈嵌入步骤之后以及在与芯片连接的步骤之前或期间,将线型天线的连接部分重新定位在贯通孔的上方。
在该方法的实施例中,在与芯片的连接步骤之前,连接部分经历了平整步骤,以提供用于与芯片的接触垫连接的更大且基本平坦的导电区域。
在该方法的实施例中,保持器件和/或连接器件包括在连接步骤期间用以定位和保持连接部分与连接垫对准的装置。
在该方法的实施例中,嵌入步骤包括热压步骤,以将导线完全嵌入在支撑层内。
在该方法的实施例中,保持器件通过真空将芯片保持就位。
在该方法的实施例中,芯片的所有连接垫同时连接至线型天线。
在该方法的实施例中,同时连接是通过一个单独的压合头实现的,该压合头的宽度足以覆盖芯片的所有连接垫。
在该方法的实施例中,同时制造多个功能嵌体,因为支撑层是大的规格,其包括用于将与多个芯片连接的多个嵌入天线导线的多个位置。
在该方法的实施例中,保持器件包括多个位置以保持将与多个天线连接的多个芯片。
在该方法的实施例中,保持器件由真空板形成,该真空板包括多个吸孔以通过真空使得多个芯片被保持就位。真空板至少在垂直于支撑层的处理路径的方向上是可移动的。
在该方法的实施例中,连接器件包括多个连接头以将多个芯片同时连接至多个天线。
附图说明
从以下详细的说明以及以下的图将会更好地理解本发明,其显示
图1示出在本发明中使用的支撑层的侧切图;
图2示出了图1的支撑层,其中导线(典型地为线型天线)已被嵌入在其上;
图3概略地示出图2的支撑层的顶视图;
图4示出图2的支撑层的线嵌的可选概略图;
图5示出导线平整步骤的可选概略图;
图6概略地示出图5平整步骤的结果;
图7和8以两种变体示出了根据本发明的芯片的堆积;
图9示出图7和8沉积步骤的结果;
图10示出图9的顶视图;
图11示出根据本发明的保持头的实施例;
图12示出用于实行本发明的方法的系统的实施例的概略图;
图13示出用于实行本发明的方法的系统的另一个实施例的概略图;
图14示出用于实行本发明的方法的系统的另一个实施例的概略图;
图15示出了显示如何操作本发明的实施例的侧视图。
具体实施方式
典型的支撑层在图1中示出,标号1。该层例如为150μm的PC层,如同在RFID卡领域和RFID卡应用中使用的。其他类似或等同的层(具有其他尺寸和/或由其他材料制成)当然也可以在本发明的框架内被使用。
该层可以在将要沉积芯片的地方包括孔或开口2,这从以下的说明会很清楚。
为了构造功能嵌体,首先在支撑层1上形成天线。该天线优选为线型天线3,并且如图2和3所示(图3仅示出越过孔2的端部而未示出构成天线的全部匝,如在RFID器件领域所知的),线型天线3的两个端部4越过开口2(当存在于层中时)。
图4示出了可选的方法步骤,其中施加热预压至具有导线3的支撑层1,以使导线3完全嵌入在支撑层1中。该步骤由两个加热板5和6完成,并且结果是线型天线3完全嵌入在形成支撑层1的衬底中。该可选的步骤有两个目的:
1.得到尽可能薄的最终的功能嵌体。理想的理论厚度对应于芯片的厚度加上导线端部4的厚度(最终的结果也参见图9)。
2.确保使全部天线在支撑层内处于同一水平(包括天线的两端),以方便进一步的步骤(如果需要的话)。
图5示出本发明的方法中另一个可选步骤,其中在连接步骤之前平整用于与芯片的连接的导线的部分4。该系统使用至少一个压板7(优选2个),其按压线型天线3的部分4以平整所述部件4,部分4用于与芯片接触部的连接。该平整操作的结果在图6中示出。该可选步骤的目的是减小最终嵌体的厚度(如图4中示出的那个),以及得到更大的且平坦的导电平面以便于与芯片垫的连接。
图7和8示出本发明的方法的原理,用于将芯片(或芯片模块)附接至施加到支撑层1的线型天线。一旦天线导线3已经被施加到支撑层1(见以上说明),其就被传送到键合站。在那里,所述支撑层1在一侧上由保持芯片11的保持器件10(例如保持头)靠近,由此所述芯片包括连接垫12,以及在另一侧上由连接器件13靠近。为了实现连接垫12和导线用于连接的部分4之间的连接,保持器件和连接器件都对导线4和芯片11施加相反的压力。典型地,通过热压合或热焊接实现连接。作为例子,连接器件13可以由金刚石头或另一合适和等同的头和材料制成。
如示出的,芯片和保持器件可以从支撑层1的任何一侧带来。通过任何其他的配置是可能的,例如支撑层1是垂直的而器件10和13的压力轴是水平的。
有利地,如果连接头13的宽度足以同时覆盖两个垫12,则导线4可以同时连接至芯片11的垫12。但是两步键合顺序也是可以接受的方案。
本发明的特征是在芯片保持器件上完成焊接,但是利用放置于承载有导线的衬底的两侧上的两个工具(连接器件&保持器件)。关键点是所有的元件必须正确对准以使两个导线部分4可以焊接至芯片垫12。
可选地,导线定位装置可以安装在保持器件或连接器件任何一个上以允许精确调整导线部分的位置/方向。例如,可以在这里使用PCT申请WO 2008/114091(其内容通过引用包含在本申请中)中公开的原理在芯片的连接垫上方正确地定位导线部分4。当然,本领域中公知的任何其他导线抓取装置或导线引导装置也是可用的。
作为例子,连接器件13可以由金刚石头或另一合适和等同的头和材料制成。
图9和10示出如参考图7和8解释的连接操作的结果。具体地,图9在横切图中示出用本发明的方法生产的功能嵌体,并且图10在顶视图中示出同样的结果。在该图中,为了简单的缘故,只是概略地表示天线导线而不是通常形成天线的所有的导线匝,这对于本领域技术人员是明显的。
如以上讨论的(见图4的说明),最终的嵌体的厚度对应于芯片的厚度加上线圈的一个端部4的厚度。例如,NXP的芯片P60D144VA呈现的总厚度(包括凸块厚度)为87μm,并且在压合键合步骤过程中导线端部4经过轻微平整化的(从80μm到大约60μm),可以预计大约150μm的薄RFID嵌体的实现。而且,如果使用图5的平整步骤,甚至可以生产更薄的嵌体。
图11示出芯片的保持器件10的示例性细节。在该例子中,保持器件10使用真空以保持芯片11,所述真空通过在保持器件10的顶表面16中开口的贯通孔15施加。优选地,表面16在区域16'中不含吸气孔,其中当通过保持器件保持芯片时芯片11的接触部12(或大凸块)将放置在区域16'中以提供稳定的支撑表面和良好的焊接。
典型地,保持器件由金属或陶瓷制成。对于非常薄的芯片例如NXP的P60D144VA特别地推荐使用这样的真空保持系统,因为施加在芯片边缘上的机械压力具有风险(芯片破裂)。
图12示出根据本发明用于形成嵌体的系统的顶视图。标号18示出送料器,其用来将要施加至嵌体的单个的芯片11送给系统。例如,每个芯片可以通过拾取和放置系统19从送料器18取得并沉积在保持器件10的表面16上。优选地,具有保持器件10的芯片16的适当定位和对准可以在照相机视觉控制系统的帮助下实现。形成支撑层的片20邻近保持器件10,如上所述,该片20包括数个嵌入的天线和一系列孔2(在该例子中4x8个孔),这些孔2对应于施加在支撑层1上的天线。
如之后要描述的,片20在之后(在天线的嵌入和芯片的施加之后)可以被切割为单个的功能嵌体。考虑到片20的尺寸以及单个嵌体1的尺寸,由片20生产的单个嵌体的数量可以变化。图12示出8x4的配置,但是在本发明的框架内其他配置是当然可能的。
一旦芯片11已经被拾取和放置在保持器件10上,所述器件可以在X、Y和Z方向(图12示出Z垂直于X、Y轴)移动到片20上的正确位置,以如图7和8所示以及以上讨论的那样放置芯片11。同时,连接器件13移动到片20的另一侧的同样的位置,用于与保持器件10配合并实行本发明的方法步骤。因此,连接器件也可以在X、Y和Z方向移动。
当芯片11连接至天线3时,确保准确地定位芯片11并且垫12处于相对于天线用于连接的导线部分4的正确位置是很重要的。
因此,使用调节系统以确保正确的对准和可能修正芯片的相对位置。为了这个目的,系统可以使用例如器件10和13的X、Y定位装置,其与例如视觉系统(照相机)耦合,Z的自由度(垂直)用来在保持器件10和连接器件13之间施加相反压力。
可选地,也可以在X-Y平面内控制片20的位置。在这样的配置中,连接器件13只需要沿Z方向可移动(以取得键合压力)并且保持器件将已到达固定位置键合位置(相对于X-Y固定的连接器件13来限定)。
可以顺序地施加芯片11,一个芯片11接另一个芯片,或数个芯片11可以同时施加,例如逐行施加。保持器件10和连接器件13因此适应地在每一侧上具有单独的头(顺序施加)或数个头(并行施加),头的数目和相对位置当然与片20的配置和芯片11的尺寸相适应。
作为例子,图13中示出了并行工作的机器。在该例子中,其使用的是具有四个头10的内联保持器件系统10'以及对应的具有四个连接头13的内联连接器件系统13'。这仅仅是例子并且内联系统可以例如包括另外数量的头,例如两个或更多,或者甚至跟将从片20中生产的嵌体的数目一样多。
对于通过拾取和放置系统19在每个保持器件上放置芯片,仅示出了一个送料器18,但使用不止一个这样的送料器18是可能的,例如两个或四个,以在每个器件10上并行(一次四个)或并行加顺序(两个和两个)地放置芯片。当然,根据环境以及保持器件/头的数量,选择可以变化。
在一个实施例中,当分别地施加芯片11时,可以刚好在器件10、13的相反压力施加到芯片11和线圈4之前控制该定位调节。
在另一个实施例中,在并行施加芯片11的情况下,可以同时进行调节,但是如果需要,则分别地控制并且调节每个芯片10以在施加压力之前正确地放置芯片。优选地,在这样的配置中,器件10的每个头与测量系统耦合,例如光学系统(照相机)以允许发生所述调节。
在进一步的实施例中,当并行施加数个芯片11时尤其有用,可以例如通过光学设施(例如照相机)首先确定每个天线在片20上的位置或每个开口2(如果存在)的位置,并且一旦知道这些位置,将芯片11放置在保持器件10上的相应位置处。如果保持器件10的头相对于彼此固定则可以使用该配置,在头上的单个芯片11的水平面处进行位置调节。保持器件还可以由一个延长的真空板制成,如图11的那个,但是要大得多并且具有方便地放置芯片(没有固定位置)的可能性。可选地,根据本发明的方法,一旦芯片通过保持头而保持但在施加相反的压力之前,可以在器件10(和13)的每个头之间进行相对位置调节。
图14示出进一步的实施例,在键合站中同时并行施加芯片。更具体地,标号21标识为芯片11的放置区域或站,拾取和放置工具22将从送料器18获得的单独的芯片放置在其上。每个芯片的位置可以从片20预先确定,片20承载有嵌入天线3并且还可以包括孔2。例如通过光学设施(例如照相机)的方法可以进行该确定。一旦知道了天线的位置,就可能通过拾取和放置工具22将各个芯片堆放在芯片放置区域21中的相应位置,在例如由金属或陶瓷制成的刚性真空板23上。在该实施例中,支撑件23发挥的是前面描述的保持器件10的作用,但是这里该保持器件承载多个芯片11。
一旦在板23上已经放置所需数量的芯片11,接着沿处理路径移动板23至键合区域或站24,具有天线的片20也来到此处,根据这里描述的本发明的原理,板也被处理以将芯片11施加和连接至天线4。
通过使用连接器件13,每个芯片11可以单独地顺序键合至天线4(见图7和8公开的有关原则)或者可能进行并行程序,其中多个(即多于一个)芯片连接至天线。在这种情况下,也有多个连接头(在图14中标号13')并行地工作。
连接头的数量可以等于将要放置在一个片20上的芯片的数量,从而芯片与天线的连接可以在一个单个方法步骤中完成。
注意到,使用如此大的保持板23的问题在于需要如图15所示的支撑条25以保持支撑片20水平。可能的解决方案是在板24中对应支撑条而制造凹槽26,从而当保持板靠近支撑片20附近时,支撑条将进入凹槽26而不会阻挡板23的移动。
一旦芯片与天线连接,接着片20就被传输到另一个区域或站以进一步处理,例如单个功能嵌体的切割。
整个系统优选通过计算机系统以及能够实行该方法的合适的程序监控。典型地,这样的计算机设施及程序将管理和运行该方法步骤,至少例如片19的和芯片11的送达,在真空控制下的芯片在保持头10上的放置,头在片上的正确位置处的移动,芯片11位置的调节(通过定向设施例如照相机)和施加相反压力的连接步骤本身,以及通过该方法生产的嵌体的进一步的处理步骤,例如移动到切割站,在那里将片20通过切割成这样的单个嵌体而生产出单个嵌体。
当然,这里描述的所有方法和实施例是作为示意性例子而不是要在限定的方式内解释。在本发明的范围内修改是可能的,例如通过使用等同的设施和方法步骤。此外,这里描述的不同实施例可以看情况结合在一起。

Claims (17)

1.一种制造功能嵌体的方法,包括:
-)提供具有至少第一侧和第二侧的支撑层;
-)在所述支撑层中嵌入线型天线;
-)在连接站处理具有所述嵌入的线型天线的所述支撑层,其中
-)所述支撑层在所述第一侧上由保持器件靠近,该保持器件保持具有包括连接垫的表面的芯片;并且所述支撑层在所述第二侧上由连接器件靠近;并且
-)通过在所述保持器件和所述连接器件之间施加的相反压力将所述天线导线连接至所述连接垫,
其中所述支撑层包括贯通孔,在连接步骤过程中或在连接步骤之前,通过所述保持器件将芯片定位在所述贯通孔中。
2.如权利要求1所述的方法,其中沿着处理路径处理具有导线嵌入的天线的支撑层,并且保持器件和连接器件都通过基本垂直于所述处理路径的移动而靠近支撑层。
3.如前述权利要求中一项所述的方法,其中连接步骤通过热压合完成。
4.如权利要求1所述的方法,其中线型天线用于与芯片的连接垫连接的连接部分定位在所述贯通孔的上方。
5.如权利要求4所述的方法,其中在线型天线嵌入步骤期间,线型天线的连接部分定位在所述贯通孔的上方。
6.如权利要求4所述的方法,包括附加的步骤,用于在线嵌步骤之后以及在与芯片连接的步骤之前或期间,将线型天线的连接部分重新定位在所述贯通孔的上方。
7.如权利要求4到6中一项所述的方法,其中在与芯片的连接步骤之前,连接部分经历了平整步骤,以提供用于与芯片的接触部连接的更大且基本平坦的导电区域。
8.如权利要求4到6中一项所述的方法,其中保持器件和/或连接器件包括在连接步骤期间用以定位和保持连接部分与连接垫对准的装置。
9.如权利要求1、2和4到6中一项所述的方法,其中嵌入步骤包括热压步骤,以将导线完全嵌入在所述支撑层内。
10.如权利要求1、2和4到6中一项所述的方法,其中保持器件通过真空将芯片保持就位。
11.如权利要求1、2和4到6中一项所述的方法,其中芯片的所有连接垫同时连接至线型天线。
12.如权利要求11所述的方法,其中所述同时连接是通过一个单独的压合头实现的,该压合头的宽度足以覆盖芯片的所有连接垫。
13.如权利要求1、2和4到6中一项所述的方法,其中同时制造多个功能嵌体,因为支撑层是大的规格,其包括用于将与多个芯片连接的多个嵌入的天线导线的多个位置。
14.如权利要求13所述的方法,其中保持器件包括多个位置以保持将与多个天线连接的多个芯片。
15.如权利要求14所述的方法,其中保持器件由真空板形成,该真空板包括多个吸孔以通过真空将多个芯片保持就位。
16.如权利要求13所述的方法,其中连接器件包括多个连接头以将多个芯片同时连接至多个天线。
17.一种功能嵌体,其由根据前述权利要求中一项所述的方法制造。
CN201280074655.2A 2012-07-12 2012-07-12 功能嵌体的制造方法 Active CN104471593B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2012/063671 WO2014008937A1 (en) 2012-07-12 2012-07-12 Method of manufacturing a functional inlay

Publications (2)

Publication Number Publication Date
CN104471593A CN104471593A (zh) 2015-03-25
CN104471593B true CN104471593B (zh) 2018-02-02

Family

ID=46640649

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280074655.2A Active CN104471593B (zh) 2012-07-12 2012-07-12 功能嵌体的制造方法

Country Status (5)

Country Link
US (2) US9501733B2 (zh)
EP (1) EP2873031B1 (zh)
CN (1) CN104471593B (zh)
MY (1) MY189207A (zh)
WO (1) WO2014008937A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY188490A (en) * 2014-12-15 2021-12-14 Assa Abloy Ab Method of producing a functional inlay and inlay produced by the method
WO2017079847A1 (en) * 2015-11-11 2017-05-18 Ks Circuits Inc. Communications antennas, systems and methods of manufacture thereof
US20180091070A1 (en) * 2016-09-23 2018-03-29 Hamilton Sundstrand Corporation Redundant channel motor and method
US10702198B2 (en) * 2016-11-29 2020-07-07 Dexcom, Inc. Wire-assembly apparatus for invasive biosensors
US11203501B2 (en) 2017-09-29 2021-12-21 Avery Dennison Retail Information Services Llc Systems and methods for transferring a flexible conductor onto a moving web
EP3688668B8 (en) * 2017-09-29 2022-08-24 Avery Dennison Retail Information Services LLC Strap mounting techniques for wire format antennas
KR102001243B1 (ko) * 2017-11-28 2019-07-17 신혜중 다중 와이어를 선으로 하는 안테나 선 형성을 위한 와이어 임베딩 헤드
WO2019236476A1 (en) 2018-06-04 2019-12-12 SparkMeter, Inc. Wireless mesh data network with increased transmission capacity
US10833051B2 (en) * 2019-01-24 2020-11-10 International Business Machines Corporation Precision alignment of multi-chip high density interconnects
CN114586041A (zh) 2019-08-28 2022-06-03 艾利丹尼森零售信息服务有限公司 旋转不敏感型射频识别器件和形成该器件的方法
SE2051294A1 (en) * 2020-11-06 2022-05-07 Fingerprint Cards Anacatum Ip Ab Integrated biometric sensor module and method for manufacturing a smartcard comprising an integrated biometric sensor module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101160596A (zh) * 2005-04-18 2008-04-09 日立化成工业株式会社 电子装置的制造方法
CN101836325A (zh) * 2007-05-21 2010-09-15 格马尔托股份有限公司 用于制造包含连接到接触垫片的应答器天线的装置的方法以及所获得的装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6097089A (en) * 1998-01-28 2000-08-01 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
JPS6384130A (ja) * 1986-09-29 1988-04-14 Toshiba Corp ワイヤボンディング方法
ES2059215T3 (es) 1991-02-25 1994-11-01 Ake Gustafson Procedimiento de fijacion de un bobinado a un circuito electronico.
US5994910A (en) * 1994-12-21 1999-11-30 International Business Machines Corporation Apparatus, and corresponding method, for stress testing wire bond-type semi-conductor chips
US6242802B1 (en) * 1995-07-17 2001-06-05 Motorola, Inc. Moisture enhanced ball grid array package
EP0880754B1 (de) * 1996-02-12 2000-05-17 David Finn Verfahren und vorrichtung zur kontaktierung eines drahtleiters
US5731244A (en) * 1996-05-28 1998-03-24 Micron Technology, Inc. Laser wire bonding for wire embedded dielectrics to integrated circuits
JP3065549B2 (ja) * 1997-01-09 2000-07-17 富士通株式会社 半導体チップ部品の実装方法
TW497236B (en) * 2001-08-27 2002-08-01 Chipmos Technologies Inc A soc packaging process
US7176506B2 (en) * 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US20070018186A1 (en) * 2005-07-19 2007-01-25 Lg Chem, Ltd. Light emitting diode device having advanced light extraction efficiency and preparation method thereof
US8067253B2 (en) * 2005-12-21 2011-11-29 Avery Dennison Corporation Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film
AU2007349611C1 (en) 2006-09-26 2015-08-06 Hid Global Gmbh Method of connecting an antenna to a transponder chip and corresponding inlay substrate
US7979975B2 (en) 2007-04-10 2011-07-19 Feinics Amatech Teavanta Methods of connecting an antenna to a transponder chip
US20080179404A1 (en) * 2006-09-26 2008-07-31 Advanced Microelectronic And Automation Technology Ltd. Methods and apparatuses to produce inlays with transponders
JP2008177350A (ja) * 2007-01-18 2008-07-31 Fujitsu Ltd 電子装置の製造方法および製造装置
US20080191333A1 (en) * 2007-02-08 2008-08-14 Advanced Chip Engineering Technology Inc. Image sensor package with die receiving opening and method of the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101160596A (zh) * 2005-04-18 2008-04-09 日立化成工业株式会社 电子装置的制造方法
CN101836325A (zh) * 2007-05-21 2010-09-15 格马尔托股份有限公司 用于制造包含连接到接触垫片的应答器天线的装置的方法以及所获得的装置

Also Published As

Publication number Publication date
EP2873031B1 (en) 2018-08-22
US9780062B2 (en) 2017-10-03
CN104471593A (zh) 2015-03-25
US9501733B2 (en) 2016-11-22
WO2014008937A1 (en) 2014-01-16
MY189207A (en) 2022-01-31
US20160026910A1 (en) 2016-01-28
US20170005066A1 (en) 2017-01-05
EP2873031A1 (en) 2015-05-20

Similar Documents

Publication Publication Date Title
CN104471593B (zh) 功能嵌体的制造方法
CN101627400B (zh) 连接天线到应答器芯片和相应的嵌件基底的方法
KR101455770B1 (ko) 트랜스폰더에 있어서 안테나선의 설치 및 접속
AU2007349611C1 (en) Method of connecting an antenna to a transponder chip and corresponding inlay substrate
US7581308B2 (en) Methods of connecting an antenna to a transponder chip
TWI363303B (en) Rfid tag manufacturing methods and rfid tags
KR100850095B1 (ko) 부품실장장치, 실장장치 및 부품실장방법
US8286332B2 (en) Method and apparatus for making a radio frequency inlay
TW200805171A (en) RFID tag manufacturing method and RFID tag
US10474308B2 (en) Position detection sensor and method for manufacturing position detection sensor
US10262906B2 (en) Method of producing a functional inlay and inlay produced by the method
JP4295713B2 (ja) 表示装置の組み立て装置及び表示装置の組み立て方法
JP2007065867A (ja) 非接触icタグ製造方法とその装置、および非接触icタグ
EP2070014B1 (en) Method and apparatus for making a radio frequency inlay
US8299925B2 (en) RFID tag and manufacturing method thereof
JP4112506B2 (ja) 実装機及び実装方法
SG174832A1 (en) Method and apparatus for making a radio frequency inlay
JP2003132325A (ja) コイルアンテナ、コイルアンテナの製造方法、及びコイルアンテナを用いた電子タグの製造方法、ならびにコイルアンテナの製造装置
JP2002342730A (ja) コイルの巻線装置、icチップとコイルの接続装置、フレキシブルicモジュールの製造装置及び情報担体の製造装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant