CN104467423B - Secondary switch duty ratio signal time sequence control circuit for single-inductance multi-output switching power supply converter - Google Patents
Secondary switch duty ratio signal time sequence control circuit for single-inductance multi-output switching power supply converter Download PDFInfo
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- CN104467423B CN104467423B CN201410836860.9A CN201410836860A CN104467423B CN 104467423 B CN104467423 B CN 104467423B CN 201410836860 A CN201410836860 A CN 201410836860A CN 104467423 B CN104467423 B CN 104467423B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention provides a secondary switch duty ratio signal time sequence control circuit for a single-inductance multi-output switching power supply converter. A secondary switch duty ratio signal time sequence control circuit formed by a duty ratio time sequence signal generating circuit and a non-overlapping duty ratio time sequence signal generating circuit is additionally arranged in a secondary loop control circuit. An output voltage sampling feedback network outputs difference module electricity VDM1, difference module electricity VDM2 and difference module electricity VDM3, the difference module electricity VDM1, the difference module electricity VDM2 and the difference module electricity VDM3 output a signal PWM1, a signal PWM2 and a signal PWM3 respectively after passing through three error amplifiers and three comparators in the secondary loop control circuit, the signal PWM1, the signal PWM2 and the signal PWM3 generate four secondary switch duty ratio signals D1, D2, D3 and D4 through the secondary switch duty ratio signal time sequence control circuit and a secondary switch drive circuit in the secondary loop control circuit, and the secondary switch duty ratio signals D1, D2, D3 and D4 control on-off of four secondary power switch tubes Sn1, Sn2, Sn3 and Sn4 in the switching power supply converter respectively.
Description
Technical field
The present invention relates to switching power converters, account for particularly to one list inductance multiple output switch electric power changer secondary switch
Empty ratio signal sequence control circuit, belongs to microelectronic.
Background technology
Single inductance multi output (Single-Inductor Multiple-output, SIMO) switching power converters is a kind of novel
Multi-output switching transformer configuration, utilizes each output branch road time-sharing work principle, only uses single inductance can realize multiple-channel output
Voltage, it is adaptable to the power supply of many-valued electrical voltage system.Each output branch road shares an inductance, time-sharing work, greatly reduces electricity
The number of inductance needed for road, thus while realizing accurately control independent to each road output branch road, substantially reduce changer
The size of system.But respectively output branch road is when time-sharing work, there is serious overlapping conducting between each output branch switch, lead
Send a telegraph inducing current descending slope mutation problems, add the ripple of each output branch road output voltage, whole system time serious, can be destroyed
The stability of system, makes changer normally to work.Therefore, secondary switch duty cycle signals is carried out accurately sequencing contro
Become research focus.The secondary switch duty cycle signals sequencing contro of single-inductance double-output switching power converters only needs one instead
Phase device can realize, and when exporting branch road and expanding to more than three tunnels and three tunnels, this sequential control method is the most unworkable, because of
This, single inductance multiple output switch electric power changer needs to increase a secondary switch duty cycle signals sequential control circuit, to many
Road secondary switch duty cycle signals sequential accurately controls, the stability of the whole switch power supply system of guarantee.
Summary of the invention
For overcoming the defect of prior art, the present invention provides a kind of single inductance multiple output switch electric power changer secondary switch duty
Ratio signal sequence control circuit, utilizes simple Digital Logical Circuits accurately to control secondary switch duty cycle signals sequential
System, solves secondary duty cycle signals and the unstable problem of system that is overlapping thus that cause occurs.
The technical scheme that the present invention takes is as follows: a kind of single inductance multiple output switch electric power changer secondary switch duty cycle signals
Sequential control circuit, single inductance multiple output switch electric power changer includes power stage circuit and controlled stage circuit, controlled stage circuit
Control including output voltage sampling feedback circuit, peak-current mode-common mode main ring control circuit and voltage mode-differential mode secondary ring
Circuit, four road output voltage Vo1～Vo4 that input is switching power converters of output voltage sampling feedback network, output electricity
Pressure sampling feedback network is output as common-mode voltage Vcm and three differential mode voltages VDM1, VDM2, VDM3；Main ring
Control circuit includes error amplifier, comparator, rest-set flip-flop and driving and dead zone function circuit, and output voltage is sampled
The common-mode voltage Vcm of feedback network output is by including error amplifier, comparator, rest-set flip-flop and driving and dead band
The main ring control circuit that control circuit is constituted produces primary switches duty cycle signals D0, controls main in switching power converters
Power switch tube S p0, the break-make of Sn0.
It is characterized in that: setting up secondary switch duty cycle signals sequential control circuit in secondary loop control circuit, output voltage is adopted
Three differential mode voltages VDM1, VDM2, VDM3 of sample feedback network output, three errors in time loop control circuit are put
Three the pwm signal PWM1 exported respectively after big device and three comparators, PWM2, PWM3 pass through secondary switch
Secondary switch drive circuit in duty cycle signals sequential control circuit and time loop control circuit produces four secondary switch duties
Ratio signal D1, D2, D3, D4, control respectively in switching power converters four secondary power switching tube Sn1, Sn2,
The break-make of Sn3, Sn4；
The described secondary switch duty cycle signals sequential control circuit set up includes that dutycycle clock signal produces circuit and Fei Jiao
Folded dutycycle clock signal produces circuit two parts, and it is three PWM letters that dutycycle clock signal produces the input signal of circuit
Number PWM1, PWM2, PWM3 and clock signal clk, dutycycle clock signal produces circuit four duties of output
Connect non-overlapping dutycycle clock signal produce the input of circuit than clock signal ND_1, ND_2, ND_3, ND_4,
Non-overlapping dutycycle clock signal produces circuit output four non-overlapping dutycycle clock signal ND1, ND2, ND3, ND4,
Wherein:
Dutycycle clock signal produces circuit and includes two nor gate NOR1 and NOR2, ten not gate NOT1～NOT10
And four rest-set flip-flops 1～rest-set flip-flop 4；The reset terminal R of rest-set flip-flop 1 connects clock signal clk, set
End S connect PWM1 signal, outfan Q1 after not gate NOT1 and NOT2, output duty cycle clock signal ND_1；
Two inputs of nor gate NOR1 connect PWM2 signal and clock signal clk, the output of nor gate NOR1 respectively
The set end S, reset terminal R that connect rest-set flip-flop 2 through not gate NOT3 connect PWM1 signal, outfan Q2 warp
After crossing not gate NOT4 and NOT5, output duty cycle clock signal ND_2；Two inputs of nor gate NOR2 are respectively
Connecting PWM3 signal and clock signal clk, the output of nor gate NOR2 connects rest-set flip-flop through not gate NOT6
The set end S, reset terminal R of 3 connects PWM2 signal, and outfan Q3, after not gate NOT7 and NOT8, exports
Dutycycle clock signal ND_3；The set end S of rest-set flip-flop 4 connects clock signal clk, and reset terminal R connects PWM3
Signal, outfan Q4 after not gate NOT9 and NOT10, output duty cycle clock signal ND_4；
Non-overlapping dutycycle clock signal produce circuit include eight nor gate NOR3～NOR10, four not gate NOT11～
Two inputs of NOT14, nor gate NOR3 connect dutycycle clock signal ND_1 and ND_4, nor gate respectively
The output of NOR3 connects an input of nor gate NOR4, and another input of nor gate NOR4 connects duty
Ratio clock signal ND_1, the output of nor gate NOR4 exports non-overlapping dutycycle clock signal through not gate NOT11
ND1；Two inputs of nor gate NOR5 connect dutycycle clock signal ND_1 and ND_2, nor gate NOR5 respectively
Output connect the input of nor gate NOR6, another input of nor gate NOR6 connects dutycycle sequential
Signal ND_2, the output of nor gate NOR6 exports non-overlapping dutycycle clock signal ND2 through not gate NOT12；Or
Two inputs of not gate NOR7 connect dutycycle clock signal ND_2 and ND_3, the output of nor gate NOR7 respectively
Connecting an input of nor gate NOR8, another input of nor gate NOR8 connects dutycycle clock signal
ND_3, the output of nor gate NOR8 exports non-overlapping dutycycle clock signal ND3 through not gate NOT13；Nor gate
Two inputs of NOR9 connect dutycycle clock signal ND_3 and ND_4 respectively, and the output of nor gate NOR9 connects
One input of nor gate NOR10, another input of nor gate NOR10 connects dutycycle clock signal ND_4,
The output of nor gate NOR10 exports non-overlapping dutycycle clock signal ND4 through not gate NOT14.
Advantages of the present invention and remarkable result: the present invention is directed to exist between each branch road output of time-sharing work serious overlapping conducting
Cause inductive current descending slope mutation problems, cause each branch road output voltage ripple coefficient to increase this defect, be additionally arranged secondary
Level duty cycle of switching signal sequence control circuit, has accurately controlled the switching sequence of each output branch road, has reduced each output and prop up
The ripple factor of road output voltage, improves the stability of whole system.
Accompanying drawing explanation
Fig. 1 is the integrated circuit figure of the present invention；
Fig. 2 is secondary switch duty cycle signals sequential control circuit schematic diagram in the present invention；
Fig. 3 a) it is the dutycycle clock signal timing waveform and the inductive current oscillogram that produce each point in circuit；
Fig. 3 b) it is that non-overlapping dutycycle clock signal produces the timing waveform of each point in circuit.
Detailed description of the invention
Such as Fig. 1, it is known that single inductance four output switch power source changer include power stage circuit and controlled stage circuit, controlled stage
Circuit includes that output voltage sampling feedback network, main ring control circuit use peak-current mode-common mode configuration, determines conversion
Device four road load current sum, i.e. flows through total current I of inductance LL；Secondary loop control circuit uses voltage mode-differential mode structure,
Determine inductive current ILDistribution in four tunnels export branch road.The input of output voltage sampling feedback network is that Switching Power Supply becomes
Four road output voltage Vo1～Vo4 of parallel operation, be output as common-mode voltage Vcm and three differential mode voltage VDM1, VDM2,
VDM3.Main ring control circuit includes error amplifier, comparator, rest-set flip-flop and driving and dead zone function circuit,
Secondary loop control circuit includes three error amplifiers, three comparators and secondary switch drive circuit.Output voltage sampling feedback
The common-mode voltage Vcm of network output produces primary switches duty cycle signals D0 by main ring control circuit, controls Switching Power Supply
The break-make of main power switch tube S p0, Sn0 in changer；Three differential mode voltages of output voltage sampling feedback network output
VDM1, VDM2, VDM3 produce secondary switch duty cycle signals by time loop control circuit and control switching power converters
The break-make of middle secondary power switching tube Sn1, Sn2, Sn3, Sn4.
The present invention, on the basis of above-mentioned available circuit, is additionally arranged secondary switch duty cycle signals sequencing contro electricity in secondary ring
Road, after this circuit is connected to three comparators of secondary ring, before secondary switch drive circuit, its input signal is three PWM
Signal PWM1, PWM2, PWM3 and clock signal clk, be output as four non-overlapping dutycycle clock signal ND1,
ND2, ND3, ND4, be then passed through secondary switch drive circuit produce four secondary switch duty cycle signals D1, D2,
D3, D4, for controlling four secondary power switching tube Sn1, Sn2, Sn3, Sn4 in switching power converters respectively
Break-make.
As in figure 2 it is shown, secondary switch duty cycle signals sequential control circuit is produced circuit and non-overlapping by dutycycle clock signal
Dutycycle clock signal produces circuit two parts composition, and wherein, dutycycle clock signal produces circuit and includes two nor gates
NOR1 and NOR2, ten not gate NOT1～NOT10 and four rest-set flip-flops 1～rest-set flip-flop 4.RS triggers
The reset terminal R of device 1 connects clock signal clk, and set end S connects PWM1 signal, and outfan Q1 is through not gate
After NOT1 and NOT2, output duty cycle clock signal ND_1.Two inputs of nor gate NOR1 connect respectively
PWM2 signal and clock signal clk, it is ensured that put 1 to when each clock cycle starts output Q2.Nor gate NOR1
Output through not gate NOT3 connect rest-set flip-flop 2 set end S, reset terminal R connect PWM1 signal, output
End Q2 after not gate NOT4 and NOT5, output duty cycle clock signal ND_2.Two of nor gate NOR2 defeated
Enter end and connect PWM3 signal and clock signal clk respectively, it is ensured that put 1 to when each clock cycle starts output Q3.
Set end S, reset terminal R that the output of nor gate NOR2 connects rest-set flip-flop 3 through not gate NOT6 connect PWM2
Signal, outfan Q3 after not gate NOT7 and NOT8, output duty cycle clock signal ND_3.Rest-set flip-flop 4
Set end S connect clock signal clk, it is ensured that putting 1 to when each clock cycle starts output Q4, reset terminal R connects
PWM3 signal, outfan Q4 after not gate NOT9 and NOT10, output duty cycle clock signal ND_4.
Non-overlapping dutycycle clock signal produce circuit include eight nor gate NOR3～NOR10, four not gate NOT11～
Two inputs of NOT14, nor gate NOR3 connect dutycycle clock signal ND_1 and ND_4, nor gate respectively
The output of NOR3 connects an input of nor gate NOR4, and another input of nor gate NOR4 connects duty
Ratio clock signal ND_1, the output of nor gate NOR4 exports non-overlapping dutycycle clock signal through not gate NOT11
ND1；Two inputs of nor gate NOR5 connect dutycycle clock signal ND_1 and ND_2, nor gate NOR5 respectively
Output connect the input of nor gate NOR6, another input of nor gate NOR6 connects dutycycle sequential
Signal ND_2, the output of nor gate NOR6 exports non-overlapping dutycycle clock signal ND2 through not gate NOT12；Or
Two inputs of not gate NOR7 connect dutycycle clock signal ND_2 and ND_3, the output of nor gate NOR7 respectively
Connecting an input of nor gate NOR8, another input of nor gate NOR8 connects dutycycle clock signal
ND_3, the output of nor gate NOR8 exports non-overlapping dutycycle clock signal ND3 through not gate NOT13；Nor gate
Two inputs of NOR9 connect dutycycle clock signal ND_3 and ND_4 respectively, and the output of nor gate NOR9 connects
One input of nor gate NOR10, another input of nor gate NOR10 connects dutycycle clock signal ND_4,
The output of nor gate NOR10 exports non-overlapping dutycycle clock signal ND4 through not gate NOT14.
When the output branch road conducting of i-th (i=1,2,3,4) bar, inductive current descending slope is-Voi/L, if now there is jth
(j=1,2,3,4, j ≠ i) bar output branch road also simultaneously turns on, and inductive current descending slope will become-(Voi*ri+Voj*rj)/(ri+rj),
Wherein, Voi, Voj are respectively i-th and the output voltage of j-th strip output branch road, ri and rj is respectively i-th and j-th strip
The conducting resistance of output branch switch pipe.Therefore inductive current descending slope is sent out in secondary switch duty cycle signals overlap branch
Raw sudden change, causes output voltage ripple to increase, and also can break the stability of meeting whole system time serious.Above-mentioned dutycycle sequential is believed
Number produce circuit and non-overlapping dutycycle clock signal to produce circuit two parts and be simple Digital Logical Circuits, it is possible to list
The secondary switch duty cycle signals sequential of inductance multiple output switch electric power changer accurately controls.Output voltage is by output
Voltage sample feedback network, voltage mode-differential mode control circuit, produce pwm signal, then the PWM letter to output
Number carry out the adjustment in sequential logic and obtain accurate secondary switch duty cycle signals D1 by secondary switch drive circuit,
D2, D3, D4, control the break-make of secondary switch pipe, it is ensured that the situation that each secondary switch will not simultaneously turn on.
Fig. 3 is timing waveform and the inductive current oscillogram of circuit each point in Fig. 2.List inductance four output switch of the present invention
During supply convertor work, first Article 1 output branch road is charged by inductance, and output voltage Vo1 charges to setting value
After, turn off power switch tube S n1 of Article 1 output branch road, open power switch tube S n2 of Article 2 output main road, with
This analogizes, until clock cycle Mo, power switch tube S n4 that Article 4 exports branch road turns off, and opens Sn1 simultaneously.
Such as Fig. 3 a), when each cycle starts, CLK signal is reset to 0 to rest-set flip-flop 1 output, i.e. Q1 is 0, Article 1
Output branch power switching tube Sn1 conducting, when Article 1 branch road output voltage reaches setting value, produces PWM1 signal,
Q1 is set to 1, until next cycle starts.The outfan Q2 of rest-set flip-flop 2 is resetted by PWM1 signal simultaneously
Being 0, Article 2 output branch power switching tube Sn2 conducting, inductance is to Article 2 output branch road charging, when Article 2 branch road
When output voltage reaches setting value, produce PWM2 signal, Q2 is put 1, Q3 is reset to 0, Article 2 output
Road power switch tube S n2 turns off, and Article 3 output branch power switching tube Sn3 conducting, inductance exports branch road to Article 3
Charging, when Article 3 branch road output voltage reaches setting value, produces PWM3 signal, Q3 is put 1, resetted by Q4
Being 0, Article 3 output branch power switching tube Sn3 turns off, Article 4 output branch power switching tube Sn4 conducting, inductance
To Article 4 output branch road charging until the next cycle starts.Such as Fig. 3 b), there is low level to overlap between ND_1 and ND_2,
After nor gate, the output of nor gate and ND_2 signal again through nor gate and a not gate, ND_1 and ND_2 it
Between low level overlapping part become high level, be output as ND2；Low level is had to overlap between ND_2 and ND_3, Jing Guohuo
Non-behind the door, the output of nor gate and ND_3 signal are again through nor gate and a not gate, low electricity between ND_2 and ND_3
Usual friendship is folded partially changes into high level, is output as ND3；Low level is had to overlap between ND_3 and ND_4, after nor gate,
The output of nor gate and ND_4 signal are again through nor gate and a not gate, low level overlap between ND_3 and ND_4
Divide and become high level, be output as ND4；Low level is had to overlap between ND_4 and ND_1, after nor gate, nor gate
Output and ND_1 signal again through nor gate and a not gate, between ND_4 and ND_1, low level overlapping part becomes
High level, is output as ND1.
The feature of this patent is and content has revealed that as above, but those skilled in the art is potentially based on the explanation of the present invention
And do all substitutions and modifications without departing substantially from spirit.Therefore, should to be not limited to single inductance four defeated for protection scope of the present invention
Go out the secondary switch duty cycle signals sequencing contro of Buck type switching power converters, it should comprise all single inductance multi output
The secondary switch duty cycle signals sequencing contro of switching power converters, should comprise the various replacement without departing substantially from the present invention and repair
Change, and contained by claims.
Claims (1)
1. a single inductance multiple output switch electric power changer secondary switch duty cycle signals sequential control circuit, single inductance multiple output switch electric power changer includes power stage circuit and controlled stage circuit, controlled stage circuit includes output voltage sampling feedback circuit, peak-current mode-common mode main ring control circuit and voltage mode-differential mode time loop control circuit, the four road output voltage Vo1 ~ Vo4 that input is switching power converters of output voltage sampling feedback network, output voltage sampling feedback network is output as common-mode voltage Vcm and three differential mode voltages VDM1, VDM2, VDM3；Main ring control circuit includes error amplifier, comparator, rest-set flip-flop and driving and dead zone function circuit, the main ring control circuit that the common-mode voltage Vcm of output voltage sampling feedback network output is constituted by including error amplifier, comparator, rest-set flip-flop and driving and dead zone function circuit produces primary switches duty cycle signals D0, control main power switch tube S p0 in switching power converters, the break-make of Sn0；
It is characterized in that: in secondary loop control circuit, set up secondary switch duty cycle signals sequential control circuit, three differential mode voltage VDM1 of output voltage sampling feedback network output, VDM2, three pwm signal PWM1 that VDM3 exports after three error amplifiers in secondary loop control circuit and three comparators respectively, PWM2, PWM3 produces four secondary switch duty cycle signals D1 by the secondary switch drive circuit in secondary switch duty cycle signals sequential control circuit and time loop control circuit, D2, D3, D4, control four secondary power switching tube Sn1 in switching power converters respectively, Sn2, Sn3, the break-make of Sn4；
The described secondary switch duty cycle signals sequential control circuit set up includes that dutycycle clock signal produces circuit and non-overlapping dutycycle clock signal produces circuit two parts, it is three pwm signal PWM1 that dutycycle clock signal produces the input signal of circuit, PWM2, PWM3 and clock signal clk, dutycycle clock signal produces circuit four dutycycle clock signal ND_1 of output, ND_2, ND_3, ND_4 connects non-overlapping dutycycle clock signal and produces the input of circuit, non-overlapping dutycycle clock signal produces circuit four non-overlapping dutycycle clock signal ND1 of output, ND2, ND3, ND4, wherein:
Dutycycle clock signal produces circuit and includes two nor gate NOR1 and NOR2, ten not gate NOT1～NOT10 and four rest-set flip-flops 1～rest-set flip-flop 4；The reset terminal R of rest-set flip-flop 1 connects clock signal clk, and set end S connects PWM1 signal, outfan Q1 after not gate NOT1 and NOT2, output duty cycle clock signal ND_1；Two inputs of nor gate NOR1 connect PWM2 signal and clock signal clk respectively, the output of nor gate NOR1 connects the set end S of rest-set flip-flop 2 through not gate NOT3, reset terminal R connects PWM1 signal, outfan Q2 after not gate NOT4 and NOT5, output duty cycle clock signal ND_2；Two inputs of nor gate NOR2 connect PWM3 signal and clock signal clk respectively, the output of nor gate NOR2 connects the set end S of rest-set flip-flop 3 through not gate NOT6, reset terminal R connects PWM2 signal, outfan Q3 after not gate NOT7 and NOT8, output duty cycle clock signal ND_3；The set end S of rest-set flip-flop 4 connects clock signal clk, and reset terminal R connects PWM3 signal, outfan Q4 after not gate NOT9 and NOT10, output duty cycle clock signal ND_4；
Non-overlapping dutycycle clock signal produces circuit and includes eight nor gate NOR3～NOR10, four not gate NOT11～NOT14, two inputs of nor gate NOR3 connect dutycycle clock signal ND_1 and ND_4 respectively, the output of nor gate NOR3 connects an input of nor gate NOR4, another input of nor gate NOR4 connects dutycycle clock signal ND_1, and the output of nor gate NOR4 exports non-overlapping dutycycle clock signal ND1 through not gate NOT11；Two inputs of nor gate NOR5 connect dutycycle clock signal ND_1 and ND_2 respectively, the output of nor gate NOR5 connects an input of nor gate NOR6, another input of nor gate NOR6 connects dutycycle clock signal ND_2, and the output of nor gate NOR6 exports non-overlapping dutycycle clock signal ND2 through not gate NOT12；Two inputs of nor gate NOR7 connect dutycycle clock signal ND_2 and ND_3 respectively, the output of nor gate NOR7 connects an input of nor gate NOR8, another input of nor gate NOR8 connects dutycycle clock signal ND_3, and the output of nor gate NOR8 exports non-overlapping dutycycle clock signal ND3 through not gate NOT13；Two inputs of nor gate NOR9 connect dutycycle clock signal ND_3 and ND_4 respectively, the output of nor gate NOR9 connects an input of nor gate NOR10, another input of nor gate NOR10 connects dutycycle clock signal ND_4, and the output of nor gate NOR10 exports non-overlapping dutycycle clock signal ND4 through not gate NOT14.
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| US9692296B1 (en) * | 2016-02-12 | 2017-06-27 | Texas Instruments Incorporated | Single-input-multiple-output (SIMO) DC-DC converters and SIMO DC-DC converter control circuits |
| CN105790582B (en) * | 2016-03-08 | 2019-01-15 | 中山大学 | A kind of list inductance multiple output DC-DC converter and its control method |
| CN105634279B (en) * | 2016-03-25 | 2018-03-20 | 东南大学 | A kind of method for improving single inductor multi-output power converter load transient response |
| CN105846678B (en) * | 2016-03-25 | 2018-04-24 | 东南大学 | A kind of secondary ring control system of list inductance multiple output switch electric power converter |
| CN107546977B (en) * | 2016-06-24 | 2019-12-03 | 辰芯科技有限公司 | A kind of multiphase interleaving direct current transducer |
| CN107769552B (en) * | 2016-08-23 | 2019-09-17 | 炬芯（珠海）科技有限公司 | A kind of control method, device and the converter of list inductance multi output converter |
| CN112911757A (en) * | 2021-01-27 | 2021-06-04 | 上汽大众汽车有限公司 | Multifunctional LED driving system and driving method |
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| CN103683923A (en) * | 2014-01-03 | 2014-03-26 | 东南大学 | Control circuit of single-inductor four-output step-down switching power supply |
| CN103813589A (en) * | 2014-01-24 | 2014-05-21 | 东南大学 | Isolation type high-power light emitting diode (LED) driving power source with multi-output current sharing |
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