CN107546977B - A kind of multiphase interleaving direct current transducer - Google Patents
A kind of multiphase interleaving direct current transducer Download PDFInfo
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Abstract
The invention discloses a kind of multiphase interleaving direct current transducers.A kind of multiphase interleaving direct current transducer, including multi-phase clock control unit, external feedback circuit and at least two branches parallel with one another；Branch includes logic trigger circuit, driving power pipe circuit and comparison circuit；The input current of sampled output is added with ramp signal as slope comparison signal, and sample compared with the voltage signal of negative terminal input is carried out PWM with slope comparison signal by comparison circuit for acquiring the peak value sampling electric current of driving power pipe circuit output；Multi-phase clock control unit, is 2 π/N clock signal for successively differing for the branch phase difference output of unlatching, and the branch of unlatching is that the voltage output end of driving power pipe circuit has the branch of output voltage.The present invention avoids introducing operational amplifier by balanced with the peak point current that common voltage circuit realizes each phase branches based on peak point current, saves hardware spending.
Description
Technical field
The present embodiments relate to direct current transducer technology more particularly to a kind of multiphase interleaving direct current transducers.
Background technique
Mobile phone or intelligent terminal are mostly coped with using multi-core processor multi-functional at present and high performance basic now
Demand, these processor chips have following characteristics and development trend: 1) technique node constantly reduces 2) superpower operational capability
Constantly soaring core number；3) more complicated framework is to cope with the operation and switching of various modes.The above processor
The voltage regulating module that the feature of core supplies power for proposes great challenge, is mainly manifested in: 1) covering extremely low working voltage.2)
High-current output ability and high efficiency, the integrated DC-DC converter of conventional power devices have been difficult in terms of efficiency and heat dissipation
It is competent, and the DCDC that power device is external, it is meant that the increase of cost.3) quick load response performance.Complicated applied field
Scape needs processor to be switched fast between " busy " " spare time ".In order to meet above-mentioned low pressure low ripple, high efficiency, high power density,
The technical indicators such as rapid response speed expand many trials and research in direct current transducer field both at home and abroad.
Multiphase DC converter technology (multiphase DCDC) is the solution party more and more discussed in recent years
One of case.Compared with traditional one phase synchronous buck controller, multi-phase controlling device increases one or more transformation channels, each
360 degree/the N of phase relative spacing (N is the number of phases) in converter channel.By taking two are in parallel step-down type dc converter as an example.Voltage
Feedback control loop is output VOUT by the end RIN to FB, compares operation with the reference voltage VREF of error amplifier positive terminal,
Obtain output Vc.Vc is connected to two channels, sums respectively with the current error signal in each channel and obtains Vd1 and Vd2.Respectively
It is compared with the ramp signal of misphase position, obtains the pwm signal of pulsewidth modulation, respectively drive the power output stage of two-phase.Often
A branch uses resistance RISEN, samples the output electric current of current channel, asks difference to obtain current error signal with average current, should
Error signal and aforesaid voltage error amplification signal Vc sum, and into voltage feedback loop, realize the stream of electric current, guarantee every
The electric current in a channel is of substantially equal, and power can be sent out from two-phase access mean allocation.
The calculating of existing Multiphase Parallel have the disadvantage that for realize current balance to sum it up averaging and it is multiple plus
Subtract operation, circuit is complicated；Lack phase increase and decrease mechanism, while loading light, multiphase drives multiple branch circuit dynamic power consumption accounting big, more
Phase DC converter efficiency rapid drawdown.
Summary of the invention
The present invention provides a kind of multiphase interleaving direct current transducer, to realize peak point current equilibrium, saves hardware cost.
In a first aspect, the embodiment of the invention provides a kind of multiphase interleaving direct current transducers, comprising:
Multi-phase clock control unit, external feedback circuit and at least two branches parallel with one another；
It include logic trigger circuit, driving power pipe circuit and comparison circuit in each branch；
The comparison circuit, the peak value sampling end of sampling input terminal connection driving power pipe circuit, ramp input end connects
The drive output of driving power pipe circuit is connect, PWM compares the first triggering end that output end connects the logic trigger circuit, uses
It is generated in the peak value sampling electric current of acquisition driving power pipe circuit output, and according to the driving current of the driving power pipe circuit
The input current of sampled output is added with ramp signal as slope comparison signal by ramp signal, and negative terminal is inputted
Voltage signal samples compared with carrying out PWM with the slope comparison signal；
The external feedback circuit, input terminal connect the voltage output end connection of the driving power pipe circuit of each branch
Place for making the difference the output voltage of the driving power pipe circuit of each branch compared with preset reference voltage, and is exported to described
The negative terminal of comparison circuit；
The multi-phase clock control unit, output terminal of clock connect the second triggering of the driving power pipe circuit of each branch
End, for successively differing the clock signal for being for the branch phase difference output of unlatching, N is the number for the branch opened, unlatching
Branch is that the voltage output end of driving power pipe circuit has the branch of output voltage；
The output end of the logic trigger circuit connects the driving input terminal of the driving power pipe circuit, when the first triggering
When voltage being held to be greater than zero and the second triggering end reception rising edge clock signal, which is opened by its output end.
Further, the driving power pipe circuit include: gate driving circuit, top power tube, following power tube with
And matching inductance；The output end of the logic trigger circuit connects the input terminal of the gate driving circuit, the gate driving
Two output end of circuit is separately connected the grid of the top power tube and the grid of the following power tube, the top power tube
Drain electrode be connected with the source electrode of the following power tube, first output end of gate driving circuit connects the comparison circuit
The source level at ramp input end, top power tube powers on, the drain ground connection of following pipe；The sampling input terminal of the comparison circuit connects
The top power tube is to acquire the top power tube peak point current；One end connection top power tube of the matching inductance
Drain electrode, the input terminal of the other end junction connection external feedback circuit of the matching inductance of each branch.
Further, external feedback circuit includes that the voltage output end for sampling the driving power pipe circuit of each branch connects
Connect the proportional sampling circuit and first comparator of place's output voltage, the anode input reference voltage of the first comparator, negative terminal
The output end of the proportional sampling circuit is connected, the input terminal of the first comparator is separately connected PWM comparator in each branch
Negative terminal, the output end of the PWM comparator connects the second logical triggering end of the logic trigger circuit.
Further, the comparison circuit includes that current sampling module, ramp circuit, first adder and PWM compare
Device；The sampled output of current sampling module and the output end of ramp circuit are all connected with the input terminal of first adder, and described
The anode of the output end connection PWM comparator of one adder, the output end connection PWM comparator of the external feedback circuit are born
End.
Further, the multi-phase clock control unit includes phase control unit, clock output end unit, peak value sampling
Add circuit, ratio circuit and ADC threshold decision circuit；The peak value sampling output end of each branch comparison circuit connects the peak
The input terminal of value sampling add circuit, the output end of the peak value sampling add circuit connect the input terminal of the ratio circuit,
The output end of the ratio circuit connects the input terminal of the ADC threshold decision circuit, the output of the ADC threshold decision circuit
End connects the phase control unit, and the clock that the output end of the phase control unit connects the clock output unit generates
Input terminal, the first triggering end of the output end connection logic trigger circuit of the clock output unit.
Further, the multi-phase clock control unit further includes critical comparator, the first ratio of the critical comparator
Compared with the output end that end connects the proportional sampling circuit, second compares the default enabled charge threshold level of end connection, the critical ratio
Compared with the full branch enable end that the output end of device connects the multi-phase clock control unit.
Further, the phase control unit, for the output according to current threshold comparison result threshold decision circuit
Signal controls the enabled open state of each branch；The clock output end unit, for being inputted according to the phase control unit
Unlatching the clock signal that successively differs of branch number N phase difference output to the logic trigger circuit for opening branch the first touching
Originator.
Further, peak value sampling add circuit includes the sampling hold circuit and adder of each branch, and each branch compares
The peak value sampling output end of circuit is separately connected the input terminal of the sampling hold circuit of each branch, and each branch sampling keeps electricity
The output end on road is all connected with the input terminal of the adder, and the output end of shown adder connects the input of the ratio circuit
End.
Further, the logic trigger circuit is set-reset flip-floop, and first triggering end is the end S, second triggering
End is the end R, and the output end is the end Q.
It further, further include capacitor Cout, one end of capacitor Cout connects the electricity of the driving power pipe circuit of each branch
Press output end junction, the other end ground connection of capacitor Cout.
Further, the phase control unit includes RN, N-1 electricity of power input and N number of series connection divider resistance
Comparator is flowed, ratio circuit output end is accessed to the anode of each current comparator, the junction of adjacent two divider resistance connects institute
The negative terminal of each current comparator is stated, the output end of the current comparator is all connected with the input terminal of the ADC threshold decision circuit,
The output end of the ADC threshold decision circuit connects the input terminal of the clock output unit.
The present invention by balanced with the peak point current that common voltage circuit realizes each phase branches based on peak point current,
And then average current equilibrium is first realized in the insignificant situation of inductance inductance value difference, introducing operational amplifier is avoided, is saved hard
Part expense.
Detailed description of the invention
Fig. 1 a is the structural block diagram in the embodiment of the present invention 2；
Fig. 1 b is the circuit diagram in the embodiment of the present invention 2；
Fig. 2 is circuit diagram (one of the phase control unit and ADC threshold decision circuit in the embodiment of the present invention 2
Realize that details citing (four phases) is as shown in Figure 2)；
Fig. 3 is the relation schematic diagram of the load segment and number of phases and efficiency in the embodiment of the present invention 2；
Clock waveform when Fig. 4 is the two-phase work in the embodiment of the present invention 2；
Clock waveform when Fig. 5 is the three-phase work in the embodiment of the present invention 2；
Fig. 6 is the efficiency curve diagram signal in the entire loading range in the embodiment of the present invention 2；
Fig. 7 is the phase control signal signal after the digital filtering in the embodiment of the present invention 2；
Fig. 8 is to prevent output from quickly falling schematic diagram of mechanism in the embodiment of the present invention 2；
Fig. 9 is in the embodiment of the present invention 2 to the Logic Priority grade relationship of each branch control.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
A kind of multiphase interleaving direct current transducer that the embodiment of the present invention one provides specifically includes: multi-phase clock control is single
Member, external feedback circuit and N number of branch parallel with one another, N are more than or equal to 2.
It include logic trigger circuit, driving power pipe circuit and comparison circuit in each branch.Driving power pipe electricity
Road is used for the triggering according to logic trigger circuit and generates corresponding electric current, and is branch energy storage.Comparison circuit, sampling input
The peak value sampling end of end connection driving power pipe circuit, ramp input end connects the drive output of driving power pipe circuit, PWM
Compare the first triggering end of output end connection logic trigger circuit.For acquiring the peak value sampling electricity of driving power pipe circuit output
Stream, and ramp signal is generated according to the driving current of driving power pipe circuit, the input current of sampled output and slope are believed
It number is added and to be used as slope comparison signal, and sampling compared with voltage signal and the slope comparison signal of negative terminal input are carried out PWM.
External feedback circuit, input terminal connect the voltage output end junction of the driving power pipe circuit of each branch, use
It makes the difference, and exports to comparison circuit compared with preset reference voltage in by the output voltage of the driving power pipe circuit of each branch
Negative terminal；
The voltage signal of negative terminal input is by the output voltage of the driving power pipe circuit of each branch and preset reference voltage
Compare the voltage VC made the difference, is sampled compared with carrying out PWM with slope comparison signal Vramp, and current-mode control mode, by
Clock, clock increase the electric current of driving power pipe circuit along the unlatching driving power pipe circuit that arrives, then internal vramp is natural
Increase, the inductive current peak of each branch can be controlled by the Vc in loop, referring to following formula:
Vc=Vramp(peak)-----------------------------------------------------(1)
Vramp(peak)=(Iramp(peak)+Ip(peak))*Rramp---------------(2)
Ip(peak)For the current signal that sampling input terminal obtains, Iramp(peak)For the slope current generated in comparison circuit
Signal closes top pipe, completes the supplying power for outside period when Vramp increases to Vc.
Multi-phase clock control unit, output terminal of clock connect the second triggering end of the driving power pipe circuit of each branch,
It is 2 π/N clock signal for successively being differed for the branch phase difference output of unlatching, N is the number for the branch opened, unlatching
Branch is that the voltage output end of driving power pipe circuit has the branch of output voltage；
The driving input terminal of the output end connection driving power pipe circuit of logic trigger circuit, when the first triggering end voltage is big
When zero and the second triggering end reception rising edge clock signal, which is opened by its output end.
The present invention is extended to the control of multiphase peak-current mode, utilizes on the basis of single-phase peak-current mode controls
Ramp voltage comprising peak current information, using common feedback loop signals i.e. the error signal of voltage control loop as
Benchmark is compared, the purpose of current balance is realized.Rather than branch current operation is directlyed adopt, therefore side compared with prior art
Case, implementation are simpler.
Present invention introduces the fragmentation techniques to load current, likewise, because peak current information and load current exist
Certain linear relationship, the present invention utilizes peak current information, by analog digital converting unit, to obtain as load current
The foundation of segmentation.
Embodiment two
Fig. 1 a and Fig. 1 b are a kind of circuit theory of multiphase interleaving direct current transducer provided by Embodiment 2 of the present invention
Figure, the present embodiment is on the basis of the various embodiments described above, preferably by multi-phase clock control unit, external feedback circuit, logic
The branch of trigger circuit, driving power pipe circuit and comparison circuit advanced optimizes.
A kind of multiphase interleaving direct current transducer includes multi-phase clock control unit 210, external feedback circuit 220, extremely
Few two branches 230 and capacitor Cout parallel with one another.
It include logic trigger circuit 231, driving power pipe circuit 232 and comparison circuit 233 in each branch 230.
Logic trigger circuit 231 is set-reset flip-floop, and the first triggering end is the end S, and the second triggering end is the end R, output end Q
End.
Driving power pipe circuit 232 includes: gate driving circuit 2321, top power tube 2322, following power tube 2323
And matching inductance Ln, n are branch number；The end Q (output end of logic trigger circuit 231) of set-reset flip-floop connects gate driving
Input terminal, two output end of gate driving circuit of circuit 2321 are separately connected the grid of top power tube and the grid of following power tube
The drain electrode of pole, top power tube is connected with the source electrode of following power tube, and the first output end of gate driving circuit connects comparison circuit
Ramp input end, the source level of top power tube powers on PVDDn, and the drain of following pipe is grounded PGNDn；Current sampling module 2331
Input terminal (the sampling input terminal of comparison circuit 233) connection top power tube to acquire top power tube peak point current；Matching
The drain electrode of one end connection top power tube of inductance Ln, the other end junction of the matching inductance Ln of each branch connects external feedback
The input terminal of circuit 220.
Comparison circuit 233, including current sampling module 2331, ramp circuit 2332, first adder 2333 and PWM ratio
Compared with device 2334.
The sampled output of current sampling module 2331 and the output end of ramp circuit 2332 are all connected with first adder
2333 input terminal, the anode of the output end connection PWM comparator 2334 of first adder 2333, the output of external feedback circuit
The negative terminal of end connection PWM comparator 2334.
The input terminal connection top power tube 2322 of current sampling module 2331 is to acquire top power tube peak point current (ratio
Compared with the peak value sampling end of the sampling input terminal connection driving power pipe circuit 232 of circuit 233), the input terminal 2332 of ramp circuit
The first output end and gate driving circuit 2321 of (the ramp input end of comparison circuit 233) connection gate driving circuit 2321
Input terminal (drive output of driving power pipe circuit 232), the output end of PWM comparator 2334 (PWM compares output end)
The end S (the first triggering end of logic trigger circuit 231) for connecting set-reset flip-floop (is driven for acquiring driving top power tube 2322
Dynamic power transistor circuits 232) output peak value sampling electric current, and ramp signal is generated according to the driving current of set-reset flip-floop, will driven
The input current of dynamic power transistor circuits 232 is added as slope comparison signal with ramp signal, and slope comparison signal is inputted
The anode of PWM comparator 2334, the voltage signal Vc of the cathode input of PWM comparator 2334.
External feedback circuit 220 includes the load inductance Ln other end (the driving power pipe circuit for sampling each branch
Voltage output end junction) proportional sampling circuit 221 and first comparator 222, the anode input reference of first comparator 222
Voltage VREF, negative terminal connect the output end of proportional sampling circuit 220, and the output end of first comparator 222 is separately connected each branch
The negative terminal of middle PWM comparator 2334 makes the difference Vc compared with preset reference voltage VREF.
Concrete analysis explanation is done to the course of work of attached drawing 1b as follows:
Working mechanism of each branch under its open phase control, with traditional peak-current mode direct current transducer
Working mechanism is the same.By taking the first branch as an example, when clock CLK1 rising edge arrives, the end S for being connected to rest-set flip-flop to touch
Device set is sent out, Q exports high level, exports PWMP1 by gate driving circuit 2321, top power tube is opened, to the branch
L1 and Cout charging energy-storing, while PWMP1 signal control ramp circuit starts to generate acclivity, the rising edge slope and electricity
The signal adduction that stream sampling obtains is converted to Vramp signal, which is acclivity before PWMP1 does not change always.Electricity
Pressure ring road is connected to the negative input of operational amplifier after sampling VOUT, be compared with benchmark.Top is controlled in PWMP1
During power tube is opened, VOUT voltage is gradually increasing, until slightly more than target set point, operational amplifier comparison at this time is missed
Control output Vc after difference is reduced slightly.At the time of Vramp acclivity just passes through Vc from the bottom up, PWM comparator
Output is got higher by low, is resetted to the end R of rest-set flip-flop, so that output Q becomes low level from high level, through overdrive circuit
Control PWMP1 closes top pipe afterwards, and following pipe is opened after a dead time to inductance afterflow, completes charging energy-storing week
Phase.Control the pulse width of the PWMP1 signal of top pipe, the ratio with the clock cycle, as duty ratio D.
Therefore the inductive current peak of each branch, can be controlled by the Vc in loop.Equation are as follows:
Vc=Vramp(peak)------------------------------------------(1)
Vramp(peak)=(Iramp1(peak)+Ip1(peak))*Rramp1---------------(2)
The similarly inductive current peak of branch 2 and Vramp relationship are as follows:
Vramp(peak)=(Iramp2(peak)+Ip2(peak))*Rramp2---------------(3)
Typical being achieved in that through capacitor charge and discharge for triangle sawtooth wave obtains, i.e. I*t=V*C, therefore, integrates
Can be designed by the Optimized Matching of domain in circuit it is approximate realize Iramp1 (peak)=Iramp2 (peak), in conjunction with (1)~
(3) formula, cooperation Rramp resistance trim means, and the inductive current peak Ip1 and Ip2 of available two branches are approximately equal.
Therefore, current balance strategy of the invention, it is equal dependent on the peak value for guaranteeing inductive current, ignoring every branch
Inductance difference in size in the case where, the mean value electric current that the output of every branch may be implemented is equal.
On the basis of above scheme, further, multi-phase clock control unit 210, including phase control unit 211,
Clock output unit 212, peak value sampling add circuit, ratio circuit 214 and ADC threshold decision circuit 215.The peak of each branch
It is worth the input of the output end connection peak value sampling add circuit of current sampling circuit 216 (the peak value sampling output end of comparison circuit)
End, the input terminal of the output end connection ratio circuit 214 of peak value sampling add circuit, the output end of ratio circuit 214 connect ADC
The input terminal of threshold decision circuit 215, the input of the output end connection phase control unit 211 of ADC threshold decision circuit 215
The clock at end, the output end connection clock output unit 212 of phase control unit 211 generates input terminal CLK, clock output unit
212 output end connects the end S of rest-set flip-flop in each branch.
Phase control unit 211, it is each for being controlled according to the output signal of current threshold comparison result threshold decision circuit
The enabled open state of branch；Clock output unit 212, the branch number N of the unlatching for being inputted according to phase control unit
Phase difference output successively differs the clock signal that is to the end S for the set-reset flip-floop for opening branch.Its output terminal of clock connects each
The end R of the set-reset flip-floop on road, for successively differing the clock signal for being for the branch phase difference output of unlatching, N is the branch opened
There are output voltage in the number on road, one end (voltage output end of driving power pipe circuit) that the branch of unlatching is load inductance Ln
Branch.Wherein one end of matched load connects the voltage output end of driving power pipe circuit in the branch, the matching electricity of each branch
The other end of sense Ln is connected to total voltage output end.
Wherein, peak value sampling add circuit includes the sampling hold circuit 2131 and adder 2132 of each branch, each branch
The peak value sampling output end of comparison circuit 2131 is separately connected the input terminal of the sampling hold circuit 2132 of each branch, and each branch is adopted
The output end of sample holding circuit 2132 is all connected with the input terminal of adder 2131, and the output end of adder 2131 connects ratio circuit
214 input terminal.
Wherein, phase control unit 211 includes power input, accesses external voltage AVDD, N number of series connection divider resistance
Ratio circuit output end is being accessed each current comparator CMP1-CMPN-1 just by RN, N-1 current comparator CMP1-CMPN-1
End, the junction of adjacent two divider resistance connects the negative terminal of each current comparator CMP1-CMPN-1, current comparator CMP1-
The output end of CMPN-1 is all connected with the input terminal of ADC threshold decision circuit 215, the output end connection of ADC threshold decision circuit 215
The input terminal of clock output unit 212.
Such as: by taking four phases in Fig. 2 as an example, load section is divided into (Iload < Ith1), (Ith1 < Iload < Ith2),
(Ith2 < Iload < Ith3), (Ith3 < Iload < Iocp), wherein Iocp is overcurrent protection threshold value, is not unfolded herein with regard to the threshold value
It discusses.
3 hysteresis comparators of subsequent connection and logic control part help through analog threshold to digital controlled signal
Conversion.Number of phases is judged and controlled after being segmented according to load current.Table 1 is illustrated with four phases, and corresponding diagram 2 connects
Mouthful, the logic control table for being extended to N phase is as shown in table 2.EN indicates enabling for entire multiphase BUCK, highest priority, EN 0
When, all modules are closed, while output Phase1EN~Phase4EN output in Fig. 2 is low-level logic 0, indicates all
Road, which is in, closes off position.ENall indicates whether all branches are in unlatching working condition, and priority is higher than segmentation and compares
Device compare come as a result, i.e. ENall be high level logic 1 when, all branches of positive opening, ENall be low-level logic 0
When, segmentation comparator carries out position judgement to load current and just comes into effect, thus the state that control is opened in several branches.
CMP1~CMP3 respectively represents comparator output state, and Phase1EN~Phase4EN respectively represents the unlatching of 1 branch to 4 branches
State of a control.
1 four phase of table enables logic control table
When load current is in the section (Iload < Ith1), CMP1~CMP3 output at this time is low-level logic, corresponding
It is 1 that logic control output, which only has Phase1EN, and only branch 1 opens work, is turned for traditional single-phase peak-current mode direct current
Parallel operation, remaining branch do not work, therefore electric current expends only one branch, reduces dynamic loss, as load efficiency is illustrated
1. section in figure Fig. 3, load current more hour enter PSM operating mode, turn with the direct current of traditional single-phase peak-current mode
Parallel operation is similar, is not described herein.
When load current is in the section (Ith1 < Iload < Ith2), CMP1 is to load current and Reference Design threshold at this time
After value is compared, high level logic 1 is exported, Phase1EN and Phase2EN are height, control the in addition to the 1st branch is opened
2 branches, which increase, to be opened, two branch mistake phase duties, and clock waveform is as shown in figure 4, each clock edge differs 1/2 period, i.e.,
Phase phase difference.If load current decreases below Ith1 at this time, still worked with two phase place, switching power loss increases so that efficiency
It is lower, if the increase of opposite load current exceeds Ith2, since conduction loss accounting increases, two-phase working efficiency can also be lower,
As shown in the 2. section curve in corresponding diagram 3.
When load current is in the section (Ith2 < Iload < Ith3), CMP1 and CMP2 are to load current and Reference Design
After threshold value is compared, high level logic 1 is exported, Phase1EN, Phase2EN and Phase3EN are height, and control removes the 1st
The 2nd branch and the 3rd branch outside the unlatching of road, which increase, to be opened, and three branch mistake phase duties, clock waveform is as shown in figure 5, each
Clock is along 1/3 period of difference, i.e. phase phase difference.Load, phase and efficiency chart are as shown in the 3. section curve in Fig. 3.
When load current is in the section (Ith3 < Iload < Iocp), CMP1, CMP2 and CMP3 are to load current and reference
After design threshold is compared, high level logic 1 is exported, Phase1EN, Phase2EN, Phase3EN and Phase4EN are
Height controls the unlatching of all four branches, and four branch mistake phase duties, each clock is along 1/4 period of difference, i.e. phase phase
Difference.Load, phase and efficiency chart are as shown in the 4. section curve in Fig. 3.
In addition, it is necessary to special suggestion, actual load is not stable electric current, usually dynamic change, especially
It is near waypoint, for example load is equal near Ith1, Ith2, Ith3, is realizing above-mentioned load segment control using comparator
In the embodiment of phase number processed, to prevent the slight dynamic change of load from causing number of phases frequent switching, comparator is used
Hysteresis comparator.CLK signal as shown in Figure 2 using clock signal simultaneously, filters out the burr in judgement, by one
Or after multiple clock cycle stablize, send out stable logic judgment value.Hysteresis comparator and burr is filtered out using the clock cycle be
The common-sense technology of basic analogy and digital circuit, this will not be repeated here.
Multiphase interleaving direct current transducer after this programme is realized is in entire loading range according to load section
Situation automatically controls the increase and decrease of number of phases, to reach the rational configuration of conduction loss and switching loss, the effect finally realized
Rate figure becomes Fig. 6 from Fig. 3, to meet the improved efficiency in entire loading range.
2 N phase of table enables logic
In addition, in the implementation example that this programme is enumerated, because the introducing of hysteresis comparator, and utilize clock week
Phase carries out digital filtering, filters out the burr in load dynamic change, as shown in fig. 7, load is because of disturbance or other reasons at certain
Transient fluctuation in a time, it is undesirable to which number of phases suddenly change therewith avoids frequent switching.Fig. 7 is with 1 clock cycle
For the digital filtering time, transient wave within a clock cycle can all be filtered out as burr.It is carved in figure in t1
The shake of a load has passed through load segment threshold value Ith1, but has returned to normal state immediately, obtains number after comparator judgement
Branch control signal before filtering is made that the logical signal of two-phase branch power supply to be opened, and after digital filtering, (diagram is lifted
Example is 1 clk cycle), the branch control signal actually sent out is the value after stable state, therefore, does not make the 2nd branch of increase and opens
The movement opened, the branch number avoided is because of the frequent switching shaken extremely.
But then, abnormal burr is filtered out due to the present invention program, is become so that changing to true load transients
It obtains insensitive.For example the current spikes in Fig. 7 are one and are really widely varied, as shown in Figure 8.Processor real work field
Scape load, dynamic range is big, and the direct current transducer for needing to power can make quickly judgement in order to avoid output voltage falls
It falls.It loads at the t1 moment from a reduced-current and suddenly becomes a high current, which is not burr.
On the basis of above scheme, multi-phase clock control unit 210 further includes critical comparator 217, critical comparator
The first of 217 compares the output end of end connection proportional sampling circuit, and second compares the default enabled charge threshold level VREF- of end connection
Vav, the end ENall (the full branch of multi-phase clock control unit of the output end connection multi-phase controlling unit 211 of critical comparator 217
Road enable end).The other end (the electricity of the driving power pipe circuit of each branch 230 of one end connection load inductance Ln of capacitor Cout
Press output end), the other end ground connection of capacitor Cout.
Fig. 8 describes another technical detail in the present invention program, quick voltage judgment mechanism.In conjunction with Fig. 1 b present invention
The staggered parallel connection direct converter structure figure of N, the VFB of output voltage VO UT feedback sample is compared with VREF-Vuv, low
The higher ENall signal of priority is sent out in comparator overturning after VREF-Vuv.ENall signal controls phase compared to load segment
The priority of branch number is high, and earlier logic table has been stated, and also shows Fig. 9 Logic Priority grade relationship.It corresponds in fig. 8,
The design of the Vuv can control when VOUT falls the VOUT preset value lower than 97%, and trigger comparator discharges ENall signal,
All phase branches are all turned on, with maximum capacity powering load, further falling for output voltage are avoided, by one section
After stablizing time B, into load segment judgment mechanism, C sections of load section is judged, determine that phase branches need to turn off
Number.
To sum up, it a kind of multiphase interleaving direct current transducer of the present invention: is realized based on peak point current and common voltage circuit
The peak point current of each phase branches is balanced, and then first realizes average current equilibrium in inductance inductance value difference insignificant situation,
Introducing operational amplifier is avoided, hardware spending is saved；The invention proposes using ADC judgement load section, segmentation skill is utilized
Phase number, and control multiphase clock generator are automatically switched in art control, realize and keep more efficient in entire loading range
Rate；The peak point current that the present invention directlys adopt inner upper side power tube sums up calculating, and utilizes the information of peak point current sum
The judgement for carrying out load Concourse Division, when integrated circuit is realized without additional current sample pin；The present invention is in load electricity
On the basis of flowing Discrete control, increases quick voltage and fall supplement of the judgement as load segment control phase number, guarantee phase
On the basis of position number infrequently switches, while the capability of fast response of direct current transducer is not reduced yet；
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (11)
1. a kind of multiphase interleaving direct current transducer characterized by comprising
Multi-phase clock control unit, external feedback circuit and at least two branches parallel with one another；
It include logic trigger circuit, driving power pipe circuit and comparison circuit in each branch；
The comparison circuit, the peak value sampling end of sampling input terminal connection driving power pipe circuit, the connection of ramp input end are driven
The drive output of dynamic power transistor circuits, PWM compares the first triggering end that output end connects the logic trigger circuit, for adopting
Collect the peak value sampling electric current of driving power pipe circuit output, and slope is generated according to the driving current of the driving power pipe circuit
Signal, the voltage that the output electric current of sampled output is added as slope comparison signal with ramp signal, and negative terminal is inputted
Signal is compared with the slope comparison signal carries out PWM；
The external feedback circuit, input terminal connect the voltage output end junction of the driving power pipe circuit of each branch, use
It makes the difference, and exports electric to the comparison compared with preset reference voltage in by the output voltage of the driving power pipe circuit of each branch
The negative terminal on road；
The multi-phase clock control unit, output terminal of clock connect the second triggering end of the logic trigger circuit of each branch, use
Successively differing in the branch phase difference output for unlatching is 2 π/N clock signal, and N is the number for the branch opened, the branch of unlatching
Road is that the voltage output end of driving power pipe circuit has the branch of output voltage；
The output end of the logic trigger circuit connects the driving input terminal of the driving power pipe circuit, when the first triggering end electricity
When pressure is greater than zero and the second triggering end reception rising edge clock signal, which is opened by the output end of logic trigger circuit.
2. a kind of multiphase interleaving direct current transducer according to claim 1, which is characterized in that the driving power pipe
Circuit includes: gate driving circuit, top power tube, following power tube and matching inductance；The logic trigger circuit it is defeated
Outlet connects the input terminal of the gate driving circuit, two output end of the gate driving circuit is separately connected the top power
The grid of the grid of pipe and the following power tube, the drain electrode and the source electrode phase of the following power tube of the top power tube
Even, first output end of gate driving circuit connects the ramp input end of the comparison circuit, on the source level of top power tube
Electricity, the drain ground connection of following power tube；It is described to acquire that the sampling input terminal of the comparison circuit connects the top power tube
Top power tube peak point current；The drain electrode of one end connection top power tube of the matching inductance, the matching inductance of each branch
The input terminal of other end junction connection external feedback circuit.
3. a kind of multiphase interleaving direct current transducer according to claim 1, which is characterized in that external feedback circuit packet
Include the proportional sampling circuit and of the voltage output end junction output voltage of the driving power pipe circuit for sampling each branch
One comparator, the anode input reference voltage of the first comparator, negative terminal connect the output end of the proportional sampling circuit, institute
The output end for stating first comparator is separately connected the negative terminal of PWM comparator in each branch, the output end connection of the PWM comparator
First triggering end of the logic trigger circuit.
4. a kind of multiphase interleaving direct current transducer according to claim 1, which is characterized in that the comparison circuit packet
Include current sampling module, ramp circuit, first adder and PWM comparator；The sampled output of current sampling module and tiltedly
The output end of slope circuit is all connected with the input terminal of first adder, the output end connection PWM comparator of the first adder
Anode, the negative terminal of the output end connection PWM comparator of the external feedback circuit.
5. a kind of multiphase interleaving direct current transducer according to claim 3, which is characterized in that
The multi-phase clock control unit includes phase control unit, clock output unit, peak value sampling add circuit, ratio electricity
Road and ADC threshold decision circuit；The peak value sampling output end of each branch comparison circuit connects the peak value sampling add circuit
Input terminal, the output end of the peak value sampling add circuit connects the input terminal of the ratio circuit, the ratio circuit
Output end connects the input terminal of the ADC threshold decision circuit, and the output end of the ADC threshold decision circuit connects the phase
Control unit, the clock that the output end of the phase control unit connects the clock output unit generates input terminal, when described
Second triggering end of the output end connection logic trigger circuit of clock output unit.
6. a kind of multiphase interleaving direct current transducer according to claim 5, which is characterized in that the multi-phase clock control
Unit processed further includes critical comparator, and the first of the critical comparator compares the output that end connects the proportional sampling circuit
End, second compares the default enabled charge threshold level of end connection, and the output end of the critical comparator connects the multi-phase clock control
The full branch enable end of unit processed.
7. a kind of multiphase interleaving direct current transducer according to claim 5, which is characterized in that the phase controlling list
Member, for controlling the enabled open state of each branch according to the output signal of the ADC threshold decision circuit；The clock output
When the branch number N phase difference output of unit, the unlatching for being inputted according to the phase control unit successively differs 2 π/N
Second triggering end of the clock signal to the logic trigger circuit for opening branch.
8. a kind of multiphase interleaving direct current transducer according to claim 5, which is characterized in that peak value sampling addition electricity
Road includes the sampling hold circuit and adder of each branch, and the peak value sampling output end of each branch comparison circuit is separately connected each
The output end of the input terminal of the sampling hold circuit on road, each branch sampling hold circuit is all connected with the input of the adder
End, the output end of the adder connect the input terminal of the ratio circuit.
9. a kind of multiphase interleaving direct current transducer according to claim 1, which is characterized in that the logical triggering electricity
Road is set-reset flip-floop, and first triggering end is the end R, and second triggering end is the end S, and the output end is the end Q.
10. a kind of multiphase interleaving direct current transducer according to claim 1, which is characterized in that further include capacitor
Cout, one end of capacitor Cout connect the voltage output end junction of the driving power pipe circuit of each branch, and capacitor Cout's is another
One end ground connection.
11. a kind of multiphase interleaving direct current transducer according to claim 5, which is characterized in that the ADC threshold value is sentenced
Deenergizing includes RN, N-1 current comparators of power input and N number of series connection divider resistance, and ratio circuit is exported and is terminated
Enter the anode of each current comparator, the junction of adjacent two divider resistance connects the negative terminal of each current comparator, the electricity
The output end of stream comparator is all connected with the input terminal of the phase control unit, and the output end of the phase control unit connects institute
State the input terminal of clock output unit.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102510671B1 (en) * | 2018-09-21 | 2023-03-20 | 에스케이하이닉스 주식회사 | Ramp signal generator and image sensor including the same |
| CN110333767B (en) * | 2019-06-27 | 2023-04-07 | 南京矽力微电子技术有限公司 | Multiphase power converter |
| CN111884507B (en) * | 2020-06-22 | 2021-12-03 | 杭州艾诺半导体有限公司 | Control circuit for power converter and control method thereof |
| CN112003459B (en) * | 2020-07-30 | 2021-08-10 | 科华恒盛股份有限公司 | Current control method and system of staggered parallel topology |
| CN112332668A (en) * | 2020-10-28 | 2021-02-05 | 中国电子科技集团公司第五十八研究所 | High-precision zero-crossing detection circuit for peak current mode Buck-Boost |
| CN112600421B (en) * | 2020-12-07 | 2021-12-07 | 深圳市蓝德汽车电源技术有限公司 | Current control method of hydrogen fuel cell DC-DC converter device |
| CN112737334B (en) * | 2020-12-29 | 2022-06-10 | 思瑞浦微电子科技（苏州）股份有限公司 | Multiphase DCDC control system and multiphase DCDC conversion circuit |
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