CN104467423A - Secondary switch duty ratio signal time sequence control circuit for single-inductance multi-output switching power supply converter - Google Patents
Secondary switch duty ratio signal time sequence control circuit for single-inductance multi-output switching power supply converter Download PDFInfo
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- CN104467423A CN104467423A CN201410836860.9A CN201410836860A CN104467423A CN 104467423 A CN104467423 A CN 104467423A CN 201410836860 A CN201410836860 A CN 201410836860A CN 104467423 A CN104467423 A CN 104467423A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
Abstract
The invention provides a secondary switch duty ratio signal time sequence control circuit for a single-inductance multi-output switching power supply converter. A secondary switch duty ratio signal time sequence control circuit formed by a duty ratio time sequence signal generating circuit and a non-overlapping duty ratio time sequence signal generating circuit is additionally arranged in a secondary loop control circuit. An output voltage sampling feedback network outputs difference module electricity VDM1, difference module electricity VDM2 and difference module electricity VDM3, the difference module electricity VDM1, the difference module electricity VDM2 and the difference module electricity VDM3 output a signal PWM1, a signal PWM2 and a signal PWM3 respectively after passing through three error amplifiers and three comparators in the secondary loop control circuit, the signal PWM1, the signal PWM2 and the signal PWM3 generate four secondary switch duty ratio signals D1, D2, D3 and D4 through the secondary switch duty ratio signal time sequence control circuit and a secondary switch drive circuit in the secondary loop control circuit, and the secondary switch duty ratio signals D1, D2, D3 and D4 control on-off of four secondary power switch tubes Sn1, Sn2, Sn3 and Sn4 in the switching power supply converter respectively.
Description
Technical field
The present invention relates to switching power converters, particularly one list inductance multiple output switch electric power converter secondary switch duty cycle signals sequential control circuit, belongs to microelectronic.
Background technology
Single inductance multi output (Single-Inductor Multiple-output, SIMO) switching power converters is a kind of novel multi-output switching transformer configuration, utilize each output branch road time-sharing work principle, only use single inductance can realize multiple-channel output voltage, be applicable to the power supply of many-valued electrical voltage system.An inductance shared by each output branch road, and time-sharing work, greatly reduces the number of inductance needed for circuit, thus while realization exports the independent accurately control of branch road to each road, substantially reduces the size of changer system.But each branch road that exports is when time-sharing work, there is serious overlapping conducting between each output branch switch, cause inductive current descending slope mutation problems, add the ripple of each output branch road output voltage, the stability of whole system can be destroyed time serious, converter cannot normally be worked.Therefore, accurately sequencing control is carried out to secondary switch duty cycle signals and become research focus.The secondary switch duty cycle signals sequencing control of single inductance dual output switching power converters only needs an inverter to realize, when exporting branch road and expanding to more than three tunnels and three tunnels, this sequential control method is obviously unworkable, therefore, single inductance multiple output switch electric power converter needs increase secondary switch duty cycle signals sequential control circuit, multichannel secondary switch duty cycle signals sequential is accurately controlled, the stability of the whole switch power supply system of guarantee.
Summary of the invention
For overcoming the defect of prior art, the invention provides a kind of single inductance multiple output switch electric power converter secondary switch duty cycle signals sequential control circuit, utilize simple Digital Logical Circuits accurately to control secondary switch duty cycle signals sequential, solve secondary duty cycle signals and the overlapping thus problem of the system instability caused occurs.
The technical scheme that the present invention takes is as follows: a kind of single inductance multiple output switch electric power converter secondary switch duty cycle signals sequential control circuit, single inductance multiple output switch electric power converter comprises power stage circuit and controlled stage circuit, controlled stage circuit comprises output voltage sampling feedback circuit, peak-current mode-common mode main ring control circuit and voltage mode-differential mode time loop control circuit, the four road output voltage Vo1 ~ Vo4 being input as switching power converters of output voltage sampling feedback network, the output of output voltage sampling feedback network is common-mode voltage Vcm and three differential mode voltage VDM1, VDM2, VDM3, main ring control circuit comprises error amplifier, comparator, rest-set flip-flop and driving and dead zone function circuit, the common-mode voltage Vcm that output voltage sampling feedback network exports produces primary switches duty cycle signals D0 by the main ring control circuit comprising error amplifier, comparator, rest-set flip-flop and driving and dead zone function circuit formation, the break-make of main power switch tube S p0, Sn0 in control switch supply convertor.
It is characterized in that: in secondary loop control circuit, set up secondary switch duty cycle signals sequential control circuit, three differential mode electricity VDM1 that output voltage sampling feedback network exports, VDM2, three pwm signal PWM1 that VDM3 exports respectively after three error amplifiers in secondary loop control circuit and three comparators, PWM2, PWM3 produces four secondary switch duty cycle signals D1 by the secondary switch drive circuit in secondary switch duty cycle signals sequential control circuit and time loop control circuit, D2, D3, D4, four secondary power switching tube Sn1 in control switch supply convertor respectively, Sn2, Sn3, the break-make of Sn4,
The described secondary switch duty cycle signals sequential control circuit set up comprises duty ratio clock signal and produces circuit and non-overlapping duty ratio clock signal generation circuit two parts, the input signal that duty ratio clock signal produces circuit is three pwm signal PWM1, PWM2, PWM3 and clock signal clk, duty ratio clock signal produces circuit and exports four duty ratio clock signal ND_1, ND_2, ND_3, ND_4 connects the input that non-overlapping duty ratio clock signal produces circuit, non-overlapping duty ratio clock signal produces circuit and exports four non-overlapping duty ratio clock signal ND1, ND2, ND3, ND4, wherein:
Duty ratio clock signal produces circuit and comprises two NOR gate NOR1 and NOR2, ten not gate NOT1 ~ NOT10 and four rest-set flip-flop 1 ~ rest-set flip-flops 4; The reset terminal R of rest-set flip-flop 1 connects clock signal clk, and set end S connects PWM1 signal, output Q1 after not gate NOT1 and NOT2, output duty cycle clock signal ND_1; Two inputs of NOR gate NOR1 connect PWM2 signal and clock signal clk respectively, the output of NOR gate NOR1 connects the set end S of rest-set flip-flop 2 through not gate NOT3, reset terminal R connects PWM1 signal, output Q2 after not gate NOT4 and NOT5, output duty cycle clock signal ND_2; Two inputs of NOR gate NOR2 connect PWM3 signal and clock signal clk respectively, the output of NOR gate NOR2 connects the set end S of rest-set flip-flop 3 through not gate NOT6, reset terminal R connects PWM2 signal, output Q3 after not gate NOT7 and NOT8, output duty cycle clock signal ND_3; The set end S of trigger RS4 connects clock signal clk, and reset terminal R connects PWM3 signal, output Q4 after not gate NOT9 and NOT10, output duty cycle clock signal ND_4;
Non-overlapping duty ratio clock signal produces circuit and comprises eight NOR gate NOR3 ~ NOR10, four not gate NOT11 ~ NOT14, two inputs of NOR gate NOR3 connect duty ratio clock signal ND_1 and ND_4 respectively, the output of NOR gate NOR3 connects an input of NOR gate NOR4, another input of NOR gate NOR4 connects duty ratio clock signal ND_1, and the output of NOR gate NOR4 exports non-overlapping duty ratio clock signal ND1 through not gate NOT11; Two inputs of NOR gate NOR5 connect duty ratio clock signal ND_1 and ND_2 respectively, the output of NOR gate NOR5 connects an input of NOR gate NOR6, another input of NOR gate NOR6 connects duty ratio clock signal ND_2, and the output of NOR gate NOR6 exports non-overlapping duty ratio clock signal ND2 through not gate NOT12; Two inputs of NOR gate NOR7 connect duty ratio clock signal ND_2 and ND_3 respectively, the output of NOR gate NOR7 connects an input of NOR gate NOR8, another input of NOR gate NOR8 connects duty ratio clock signal ND_3, and the output of NOR gate NOR8 exports non-overlapping duty ratio clock signal ND3 through not gate NOT13; Two inputs of NOR gate NOR9 connect duty ratio clock signal ND_3 and ND_4 respectively, the output of NOR gate NOR9 connects an input of NOR gate NOR10, another input of NOR gate NOR10 connects duty ratio clock signal ND_4, and the output of NOR gate NOR10 exports non-overlapping duty ratio clock signal ND4 through not gate NOT14.
Advantage of the present invention and remarkable result: there is serious overlapping conducting between each branch road that the present invention is directed to time-sharing work exports and cause inductive current descending slope mutation problems, each branch road output voltage ripple coefficient is caused to increase this defect, set up secondary switch duty cycle signals sequential control circuit, accurately control the switching sequence of each output branch road, reduce the ripple coefficient of each output branch road output voltage, improve the stability of whole system.
Accompanying drawing explanation
Fig. 1 is integrated circuit figure of the present invention;
Fig. 2 is secondary switch duty cycle signals sequential control circuit schematic diagram in the present invention;
Fig. 3 is a) timing waveform and the inductive current oscillogram that duty ratio clock signal produces each point in circuit;
Fig. 3 b) be the timing waveform that non-overlapping duty ratio clock signal produces each point in circuit.
Embodiment
As Fig. 1, known single inductance four output switch power source converter comprises power stage circuit and controlled stage circuit, controlled stage circuit comprises output voltage sampling feedback network, main ring control circuit adopts peak-current mode-common mode configuration, determine converter four road load current sum, namely flow through the total current I of inductance L
l; Secondary loop control circuit adopts voltage mode-differential mode structure, determines inductive current I
lthe distribution in branch road is exported on four tunnels.The four road output voltage Vo1 ~ Vo4 being input as switching power converters of output voltage sampling feedback network, export as common-mode voltage Vcm and three differential mode voltage VDM1, VDM2, VDM3.Main ring control circuit comprises error amplifier, comparator, rest-set flip-flop and driving and dead zone function circuit, and secondary loop control circuit comprises three error amplifiers, three comparators and secondary switch drive circuit.The common-mode voltage Vcm that output voltage sampling feedback network exports produces primary switches duty cycle signals D0 by main ring control circuit, the break-make of main power switch tube S p0, Sn0 in control switch supply convertor; Three differential mode voltages VDM1, VDM2, VDM3 that output voltage sampling feedback network exports produce the break-make of secondary power switching tube Sn1, Sn2, Sn3, Sn4 in secondary switch duty cycle signals control switch supply convertor by time loop control circuit.
The present invention is on the basis of above-mentioned available circuit, secondary switch duty cycle signals sequential control circuit has been set up in secondary ring, after this circuit is connected to secondary ring three comparators, before secondary switch drive circuit, its input signal is three pwm signal PWM1, PWM2, PWM3 and clock signal clk, output is four non-overlapping duty ratio clock signal ND1, ND2, ND3, ND4, then four secondary switch duty cycle signals D1 are produced through secondary switch drive circuit, D2, D3, D4, for four secondary power switching tube Sn1 in difference control switch supply convertor, Sn2, Sn3, the break-make of Sn4.
As shown in Figure 2, secondary switch duty cycle signals sequential control circuit produces circuit by duty ratio clock signal and non-overlapping duty ratio clock signal generation circuit two parts form, wherein, duty ratio clock signal produces circuit and comprises two NOR gate NOR1 and NOR2, ten not gate NOT1 ~ NOT10 and four rest-set flip-flop 1 ~ rest-set flip-flops 4.The reset terminal R of trigger RS1 connects clock signal clk, and set end S connects PWM1 signal, output Q1 after not gate NOT1 and NOT2, output duty cycle clock signal ND_1.Two inputs of NOR gate NOR1 connect PWM2 signal and clock signal clk respectively, put 1 to when ensureing that each clock cycle starts output Q2.The output of NOR gate NOR1 connects the set end S of rest-set flip-flop 2 through not gate NOT3, and reset terminal R connects PWM1 signal, output Q2 after not gate NOT4 and NOT5, output duty cycle clock signal ND_2.Two inputs of NOR gate NOR2 connect PWM3 signal and clock signal clk respectively, put 1 to when ensureing that each clock cycle starts output Q3.The output of NOR gate NOR2 connects the set end S of rest-set flip-flop 3 through not gate NOT6, and reset terminal R connects PWM2 signal, output Q3 after not gate NOT7 and NOT8, output duty cycle clock signal ND_3.The set end S of trigger RS4 connects clock signal clk, gives to export Q4 and put 1 when ensureing that each clock cycle starts, and reset terminal R connects PWM3 signal, output Q4 after not gate NOT9 and NOT10, output duty cycle clock signal ND_4.
Non-overlapping duty ratio clock signal produces circuit and comprises eight NOR gate NOR3 ~ NOR10, four not gate NOT11 ~ NOT14, two inputs of NOR gate NOR3 connect duty ratio clock signal ND_1 and ND_4 respectively, the output of NOR gate NOR3 connects an input of NOR gate NOR4, another input of NOR gate NOR4 connects duty ratio clock signal ND_1, and the output of NOR gate NOR4 exports non-overlapping duty ratio clock signal ND1 through not gate NOT11; Two inputs of NOR gate NOR5 connect duty ratio clock signal ND_1 and ND_2 respectively, the output of NOR gate NOR5 connects an input of NOR gate NOR6, another input of NOR gate NOR6 connects duty ratio clock signal ND_2, and the output of NOR gate NOR6 exports non-overlapping duty ratio clock signal ND2 through not gate NOT12; Two inputs of NOR gate NOR7 connect duty ratio clock signal ND_2 and ND_3 respectively, the output of NOR gate NOR7 connects an input of NOR gate NOR8, another input of NOR gate NOR8 connects duty ratio clock signal ND_3, and the output of NOR gate NOR8 exports non-overlapping duty ratio clock signal ND3 through not gate NOT13; Two inputs of NOR gate NOR9 connect duty ratio clock signal ND_3 and ND_4 respectively, the output of NOR gate NOR9 connects an input of NOR gate NOR10, another input of NOR gate NOR10 connects duty ratio clock signal ND_4, and the output of NOR gate NOR10 exports non-overlapping duty ratio clock signal ND4 through not gate NOT14.
In the i-th (i=1,2,3,4), when bar exports branch road conducting, inductive current descending slope is-Voi/L, if now there is jth (j=1,2,3,4, j ≠ i) the also conducting simultaneously of bar output branch road, inductive current descending slope will become-(Voi*ri+Voj*rj)/(ri+rj), wherein, and Voi, Voj is respectively the output voltage of i-th and jth bar output branch road, ri and rj is respectively the conducting resistance of i-th and jth bar output branch switch pipe.Therefore inductive current descending slope is undergone mutation in secondary switch duty cycle signals overlap branch, causes output voltage ripple to increase, and also can break the stability of meeting whole system time serious.Above-mentioned duty ratio clock signal produces circuit and non-overlapping duty ratio clock signal generation circuit two parts are simple Digital Logical Circuits, accurately can control the secondary switch duty cycle signals sequential of single inductance multiple output switch electric power converter.Output voltage is by output voltage sampling feedback network, voltage mode-differential mode control circuit, produce pwm signal, then the pwm signal exported is carried out to the adjustment in sequential logic and obtains accurate secondary switch duty cycle signals D1 by secondary switch drive circuit, D2, D3, D4, control the break-make of secondary switch pipe, ensure that the situation of conducting simultaneously can not occur each secondary switch.
Fig. 3 is timing waveform and the inductive current oscillogram of circuit each point in Fig. 2.During list inductance four output switch power source converter work of the present invention, first inductance exports branch road to Article 1 and charges, after output voltage Vo1 charges to set point, turn off the power switch tube S n1 that Article 1 exports branch road, open the power switch tube S n2 that Article 2 exports main road, by that analogy, until clock cycle Mo, power switch tube S n4 Article 4 being exported branch road turns off, and opens Sn1 simultaneously.As Fig. 3 a), when each cycle starts, CLK signal to rest-set flip-flop 1 export be reset to 0, namely Q1 is 0, and Article 1 exports branch power switching tube Sn1 conducting, when Article 1 branch road output voltage reaches set point, produce PWM1 signal, Q1 is set to 1, until next cycle starts.The output Q2 of rest-set flip-flop 2 is reset to 0 by PWM1 signal simultaneously, Article 2 exports branch power switching tube Sn2 conducting, inductance exports branch road charging to Article 2, when Article 2 branch road output voltage reaches set point, produce PWM2 signal, Q2 is put 1, Q3 is reset to 0, Article 2 exports branch power switching tube Sn2 and turns off, Article 3 exports branch power switching tube Sn3 conducting, inductance exports branch road charging to Article 3, when Article 3 branch road output voltage reaches set point, produce PWM3 signal, Q3 is put 1, Q4 is reset to 0, Article 3 exports branch power switching tube Sn3 and turns off, Article 4 exports branch power switching tube Sn4 conducting, inductance exports branch road charging until the next cycle starts to Article 4.As Fig. 3 b), have low level overlapping between ND_1 and ND_2, after NOR gate, the output of NOR gate and ND_2 signal are again through NOR gate and a not gate, and between ND_1 and ND_2, low level overlapping part becomes high level, export as ND2; Have low level overlapping between ND_2 and ND_3, after NOR gate, the output of NOR gate and ND_3 signal are again through NOR gate and a not gate, and between ND_2 and ND_3, low level overlapping part becomes high level, export as ND3; Have low level overlapping between ND_3 and ND_4, after NOR gate, the output of NOR gate and ND_4 signal are again through NOR gate and a not gate, and between ND_3 and ND_4, low level overlapping part becomes high level, export as ND4; Have low level overlapping between ND_4 and ND_1, after NOR gate, the output of NOR gate and ND_1 signal are again through NOR gate and a not gate, and between ND_4 and ND_1, low level overlapping part becomes high level, exports as ND1.
The feature of this patent and content disclose as above, but those skilled in the art may do all substitutions and modifications not deviating from invention spirit based on explanation of the present invention.Therefore; protection scope of the present invention should be not limited to the secondary switch duty cycle signals sequencing control that single inductance four exports Buck type switching power converters; the secondary switch duty cycle signals sequencing control of all single inductance multiple output switch electric power converters should be comprised; should comprise and variously not deviate from substitutions and modifications of the present invention, and be contained by claims.
Claims (1)
1. a single inductance multiple output switch electric power converter secondary switch duty cycle signals sequential control circuit, single inductance multiple output switch electric power converter comprises power stage circuit and controlled stage circuit, controlled stage circuit comprises output voltage sampling feedback circuit, peak-current mode-common mode main ring control circuit and voltage mode-differential mode time loop control circuit, the four road output voltage Vo1 ~ Vo4 being input as switching power converters of output voltage sampling feedback network, the output of output voltage sampling feedback network is common-mode voltage Vcm and three differential mode voltage VDM1, VDM2, VDM3; Main ring control circuit comprises error amplifier, comparator, rest-set flip-flop and driving and dead zone function circuit, the common-mode voltage Vcm that output voltage sampling feedback network exports produces primary switches duty cycle signals D0 by the main ring control circuit comprising error amplifier, comparator, rest-set flip-flop and driving and dead zone function circuit formation, the break-make of main power switch tube S p0, Sn0 in control switch supply convertor;
It is characterized in that: in secondary loop control circuit, set up secondary switch duty cycle signals sequential control circuit, three differential mode electricity VDM1 that output voltage sampling feedback network exports, VDM2, three pwm signal PWM1 that VDM3 exports respectively after three error amplifiers in secondary loop control circuit and three comparators, PWM2, PWM3 produces four secondary switch duty cycle signals D1 by the secondary switch drive circuit in secondary switch duty cycle signals sequential control circuit and time loop control circuit, D2, D3, D4, four secondary power switching tube Sn1 in control switch supply convertor respectively, Sn2, Sn3, the break-make of Sn4,
The described secondary switch duty cycle signals sequential control circuit set up comprises duty ratio clock signal and produces circuit and non-overlapping duty ratio clock signal generation circuit two parts, the input signal that duty ratio clock signal produces circuit is three pwm signal PWM1, PWM2, PWM3 and clock signal clk, duty ratio clock signal produces circuit and exports four duty ratio clock signal ND_1, ND_2, ND_3, ND_4 connects the input that non-overlapping duty ratio clock signal produces circuit, non-overlapping duty ratio clock signal produces circuit and exports four non-overlapping duty ratio clock signal ND1, ND2, ND3, ND4, wherein:
Duty ratio clock signal produces circuit and comprises two NOR gate NOR1 and NOR2, ten not gate NOT1 ~ NOT10 and four rest-set flip-flop 1 ~ rest-set flip-flops 4; The reset terminal R of rest-set flip-flop 1 connects clock signal clk, and set end S connects PWM1 signal, output Q1 after not gate NOT1 and NOT2, output duty cycle clock signal ND_1; Two inputs of NOR gate NOR1 connect PWM2 signal and clock signal clk respectively, the output of NOR gate NOR1 connects the set end S of rest-set flip-flop 2 through not gate NOT3, reset terminal R connects PWM1 signal, output Q2 after not gate NOT4 and NOT5, output duty cycle clock signal ND_2; Two inputs of NOR gate NOR2 connect PWM3 signal and clock signal clk respectively, the output of NOR gate NOR2 connects the set end S of rest-set flip-flop 3 through not gate NOT6, reset terminal R connects PWM2 signal, output Q3 after not gate NOT7 and NOT8, output duty cycle clock signal ND_3; The set end S of trigger RS4 connects clock signal clk, and reset terminal R connects PWM3 signal, output Q4 after not gate NOT9 and NOT10, output duty cycle clock signal ND_4;
Non-overlapping duty ratio clock signal produces circuit and comprises eight NOR gate NOR3 ~ NOR10, four not gate NOT11 ~ NOT14, two inputs of NOR gate NOR3 connect duty ratio clock signal ND_1 and ND_4 respectively, the output of NOR gate NOR3 connects an input of NOR gate NOR4, another input of NOR gate NOR4 connects duty ratio clock signal ND_1, and the output of NOR gate NOR4 exports non-overlapping duty ratio clock signal ND1 through not gate NOT11; Two inputs of NOR gate NOR5 connect duty ratio clock signal ND_1 and ND_2 respectively, the output of NOR gate NOR5 connects an input of NOR gate NOR6, another input of NOR gate NOR6 connects duty ratio clock signal ND_2, and the output of NOR gate NOR6 exports non-overlapping duty ratio clock signal ND2 through not gate NOT12; Two inputs of NOR gate NOR7 connect duty ratio clock signal ND_2 and ND_3 respectively, the output of NOR gate NOR7 connects an input of NOR gate NOR8, another input of NOR gate NOR8 connects duty ratio clock signal ND_3, and the output of NOR gate NOR8 exports non-overlapping duty ratio clock signal ND3 through not gate NOT13; Two inputs of NOR gate NOR9 connect duty ratio clock signal ND_3 and ND_4 respectively, the output of NOR gate NOR9 connects an input of NOR gate NOR10, another input of NOR gate NOR10 connects duty ratio clock signal ND_4, and the output of NOR gate NOR10 exports non-overlapping duty ratio clock signal ND4 through not gate NOT14.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634279A (en) * | 2016-03-25 | 2016-06-01 | 东南大学 | Method for improving load transient response of single-inductor multi-output power converter |
| CN105790582A (en) * | 2016-03-08 | 2016-07-20 | 中山大学 | Single-inductor multi-output DC-DC converter and control method thereof |
| CN105846678A (en) * | 2016-03-25 | 2016-08-10 | 东南大学 | Secondary-ring control system for single-inductor multiple-output switch power converter |
| CN107086777A (en) * | 2016-02-12 | 2017-08-22 | 德克萨斯仪器股份有限公司 | Single input and multi-output (SIMO) DC DC converters and SIMO DC DC converter control circuits |
| CN107546977A (en) * | 2016-06-24 | 2018-01-05 | 联芯科技有限公司 | A kind of multiphase interleaving direct current transducer |
| CN107769552A (en) * | 2016-08-23 | 2018-03-06 | 炬芯（珠海）科技有限公司 | A kind of control method, device and the converter of single inductance multi output converter |
| CN112911757A (en) * | 2021-01-27 | 2021-06-04 | 上汽大众汽车有限公司 | Multifunctional LED driving system and driving method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202261022U (en) * | 2011-09-23 | 2012-05-30 | 东南大学 | Control circuit for single-inductor dual-output DC-DC (direct current-to-direct current) switching power supply |
| CN202309521U (en) * | 2011-09-23 | 2012-07-04 | 东南大学 | Control circuit for single-inductance dual-output switching power supply |
| CN103683923A (en) * | 2014-01-03 | 2014-03-26 | 东南大学 | Control circuit of single-inductor four-output step-down switching power supply |
| CN103813589A (en) * | 2014-01-24 | 2014-05-21 | 东南大学 | Isolation type high-power light emitting diode (LED) driving power source with multi-output current sharing |
-
2014
- 2014-12-29 CN CN201410836860.9A patent/CN104467423B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202261022U (en) * | 2011-09-23 | 2012-05-30 | 东南大学 | Control circuit for single-inductor dual-output DC-DC (direct current-to-direct current) switching power supply |
| CN202309521U (en) * | 2011-09-23 | 2012-07-04 | 东南大学 | Control circuit for single-inductance dual-output switching power supply |
| CN103683923A (en) * | 2014-01-03 | 2014-03-26 | 东南大学 | Control circuit of single-inductor four-output step-down switching power supply |
| CN103813589A (en) * | 2014-01-24 | 2014-05-21 | 东南大学 | Isolation type high-power light emitting diode (LED) driving power source with multi-output current sharing |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107086777B (en) * | 2016-02-12 | 2020-07-31 | 德克萨斯仪器股份有限公司 | Single Input Multiple Output (SIMO) DC-DC converter and SIMO DC-DC converter control circuit |
| CN107086777A (en) * | 2016-02-12 | 2017-08-22 | 德克萨斯仪器股份有限公司 | Single input and multi-output (SIMO) DC DC converters and SIMO DC DC converter control circuits |
| CN105790582B (en) * | 2016-03-08 | 2019-01-15 | 中山大学 | A kind of list inductance multiple output DC-DC converter and its control method |
| CN105790582A (en) * | 2016-03-08 | 2016-07-20 | 中山大学 | Single-inductor multi-output DC-DC converter and control method thereof |
| CN105634279B (en) * | 2016-03-25 | 2018-03-20 | 东南大学 | A kind of method for improving single inductor multi-output power converter load transient response |
| CN105634279A (en) * | 2016-03-25 | 2016-06-01 | 东南大学 | Method for improving load transient response of single-inductor multi-output power converter |
| CN105846678B (en) * | 2016-03-25 | 2018-04-24 | 东南大学 | A kind of secondary ring control system of list inductance multiple output switch electric power converter |
| CN105846678A (en) * | 2016-03-25 | 2016-08-10 | 东南大学 | Secondary-ring control system for single-inductor multiple-output switch power converter |
| CN107546977A (en) * | 2016-06-24 | 2018-01-05 | 联芯科技有限公司 | A kind of multiphase interleaving direct current transducer |
| CN107546977B (en) * | 2016-06-24 | 2019-12-03 | 辰芯科技有限公司 | A kind of multiphase interleaving direct current transducer |
| CN107769552A (en) * | 2016-08-23 | 2018-03-06 | 炬芯（珠海）科技有限公司 | A kind of control method, device and the converter of single inductance multi output converter |
| CN107769552B (en) * | 2016-08-23 | 2019-09-17 | 炬芯（珠海）科技有限公司 | A kind of control method, device and the converter of list inductance multi output converter |
| CN112911757A (en) * | 2021-01-27 | 2021-06-04 | 上汽大众汽车有限公司 | Multifunctional LED driving system and driving method |
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