CN104465674B - Low temperature polycrystalline silicon (LTPS) product structure and manufacture method - Google Patents
Low temperature polycrystalline silicon (LTPS) product structure and manufacture method Download PDFInfo
- Publication number
- CN104465674B CN104465674B CN201410852082.2A CN201410852082A CN104465674B CN 104465674 B CN104465674 B CN 104465674B CN 201410852082 A CN201410852082 A CN 201410852082A CN 104465674 B CN104465674 B CN 104465674B
- Authority
- CN
- China
- Prior art keywords
- layer
- cabling
- pad
- nmos
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 95
- 239000002184 metal Substances 0.000 claims abstract description 95
- 239000012212 insulator Substances 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 31
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 29
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims description 361
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 239000011229 interlayer Substances 0.000 claims description 31
- 239000011241 protective layer Substances 0.000 claims description 29
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 235000012239 silicon dioxide Nutrition 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 14
- 238000000926 separation method Methods 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 4
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000009412 basement excavation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Manufacturing & Machinery (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of low temperature polycrystalline silicon (LTPS) product structure and manufacture method, structure to include:Base material, the N-type metal-oxide semiconductor (NMOS) on the base material and p-type metal-oxide semiconductor (PMOS), the first metal layer, on a NMOS and PMOS gate insulator, the first metal layer is used to form a grid and for forming at least one first cabling；One second metal layer, for forming the NMOS and the PMOS drain electrode and source electrode and at least one second cabling；Interbedded insulating layer, on the first metal layer and the gate insulator；An at least grooving, to expose the end point of first cabling to the open air, the interference between cabling is avoided, to lift the quality of product.
Description
【Technical field】
The present invention relates to Liquid crystal production technical field, more particularly to a kind of low temperature polycrystalline silicon product structure for lifting yield
And its manufacture method.
【Background technology】
There is high-resolution, anti-using the LCD Panel (LCD) of low-temperature polysilicon film transistor (LTPS TFT)
The advantages that answering fast speed, high brightness, high aperture, plus the silicon crystalline arrangement more amorphous silicon due to LTPS-TFT LCD
(Amorphous silicon, A-Si) orderliness so that electron mobility is relatively high more than 100 times, can be by peripheral driver electricity
Road makes simultaneously on the glass substrate, to be reached the target of system combination, save space and drives IC cost.But LTPS work
Skill flow for non-crystalline silicon (Amorphous silicon, A-Si) relative to becoming unusual complexity, the requirement for technique
Become unusual harshness.Therefore the optimization for low temperature polycrystalline silicon (LTPS) technological design is also particularly important.
Fig. 2 is refer to, is that flatness layer (Planarization, PLN) excavation region is illustrated in prior art LTPS structures
Figure.In low temperature polycrystalline silicon (LTPS) technique, typically flatness layer (Planarization, PLN) dig a hole to be formed it is one big by
Two groovings 40 are by the pad (Pad) 34 of whole or the pin or whole soft with multiple tie points of the integrated circuit (IC) 33 of whole
Property circuit board 32 exposes.The pad 34 (Pad) is formed at the end points of the tip of the second cabling 35 in structure.
Because flatness layer (Planarization, PLN) is thicker, tin indium oxide (ITO) exposure of transparency conducting layer is being carried out
When, because photoresistance is thicker at this, exposure is incomplete, and photoresistance has residual, causes short-circuit between the second cabling 35 or pin
(short) transmitted signal, is disturbed, influences Display panel.
It refer to Fig. 2, in structure, a plurality of second cabling 35 formed by second metal layer 20, the end points of each cabling includes one
Pad 34.The pin of some pad 34 circuit connectable units (Cell Test) test cells, pad 34 can be with integrated circuit 33 in addition
(IC) pin or more several contacts of flexible circuit board (Flexible Print Circuit, FPC) 32 connects.Integrated electricity
Road 33 (IC) pin, can via second metal layer 20 or directly with flexible circuit board 32 (Flexible Print Circuit,
FPC contact) engages, such as the pad 34 of integrated circuit 33 (IC) pin can be via the second cabling 35 and flexible circuit board 32
(Flexible Print Circuit, FPC) is engaged.
In prior art, typically by (IC) pin of integrated circuit 33 and (the Flexible Print of flexible circuit board 32
Circuit, FPC) contact whole region corresponding to flatness layer 21 (Planarization, PLN) scrape out one big grooving 40,
Or the whole region of corresponding more several pads 34 is scraped out into one big grooving 40.Due to flatness layer 21 (Planarization,
When PLN) forming grooving 40, there is the residual of excessive photoresistance in pointed cone (Taper) angle part so that exposed portion is not thorough, is formed
During transparency conducting layer, tin indium oxide (ITO) is caused in the residual of trench portions.The tin indium oxide of the transparency conducting layer of residual
(ITO) together with adjacent cabling (such as signal wire and data wire) short circuit the display of whole panel can be caused abnormal.
【The content of the invention】
To solve the above problems, according to the present invention, connect the pad of circuit unit test pin, connect the pin of integrated circuit
With the pad for padding and connect flexible circuit board pin it is combined with the first cabling of the first metal layer, and forms grooving to expose
Reveal the pad at the end point of first cabling, the grooving extends only through the flatness layer and the interlayer insulating film, Yi Jisuo
State grooving and extend only through at least one of first transparency conducting layer, the protective layer and second transparency conducting layer layer.
(such as NMOS and PMOS drain electrode and source electrode and at least 1 second walk in the distributed area that the grooving does not need guiding through the second metal
Line), then enter the bonding (Bonding) of line integrated circuit or flexible circuit board again, second is used so as to avoid prior art
The problem of short circuit of metal is with interference.
A preferred embodiment of the present invention provides one embodiment of the invention, is a kind of low temperature polycrystalline silicon (LTPS) product knot
Structure, a base material；At least a N-type metal-oxide semiconductor (NMOS) is located on the base material；An at least p-type metal-oxide semiconductor
(PMOS) on the base material；One the first metal layer, it is described on a NMOS and PMOS gate insulator
The first metal layer is used to form a grid and for forming at least one first cabling；One second metal layer, it is described for being formed
NMOS and PMOS drain electrode and source electrode and at least one second cabling；Interbedded insulating layer, positioned at the first metal layer
And on the gate insulator；One flatness layer is located above the NMOS and PMOS；One first transparency conducting layer position
Above the flatness layer and cover the flatness layer at least partially；One protective layer is located at the flatness layer and described first saturating
Above bright conductive layer；One second transparency conducting layer is located above the protective layer, and second transparency conducting layer is via through institute
Drain electrode and source electrode of the through hole of protective layer and the flatness layer with the NMOS is stated to be connected；An at least grooving, the grooving
Through the flatness layer and the interlayer insulating film, and the grooving through first transparency conducting layer, the protective layer,
And at least one of described second transparency conducting layer layer is to expose the end point of first cabling to the open air.
The N-type metal-oxide semiconductor includes:One shielding layer is located on the base material with covering part base material；One barrier
Layer is on the shielding layer and base material；One silicon dioxide layer is located on barrier layer；One N channel layer is located at silicon dioxide layer
On, the N channel layer has a polysilicon layer, two N+Type layer, two N+The inner side of type layer is each engaged in the N channel layer
Two outsides, two N-The both ends of type layer are each engaged in the polysilicon layer outboard end and two N+The medial extremity of type layer；The grid
Insulating barrier, on the N channel layer and the silicon dioxide layer；The first metal layer, via the gate insulator
With the N channel layer dielectric separation；Interbedded insulating layer, positioned at N-type metal-oxide semiconductor (NMOS) the superiors；And
Drain electrode and source electrode, are formed by the second metal layer, each link the N via through hole+Type layer, the through hole are arranged in described
Interlayer insulating film and the gate insulator.
The p-type metal-oxide semiconductor, including:One barrier layer is located on the base material；One silicon dioxide layer is positioned at resistance
On interlayer；In one P channel layer position silicon dioxide layer, the P channel layer has a polysilicon layer, two P+Type layer, two P+Type layer
Inner side is each engaged in two outsides of the polysilicon layer；The gate insulator, positioned at the P channel layer and the dioxy
On SiClx layer；The first metal layer, via the gate insulator and the P channel layer and dielectric separation；One layer insulation
Layer, positioned at p-type metal-oxide semiconductor (PMOS) the superiors；And drain electrode and source electrode, formed by the second metal layer,
Each link the P of the p-type metal-oxide semiconductor via through hole+Type layer, the through hole are arranged in the layer insulation
Layer and the gate insulator.
The end points of the cabling includes one first pad, and first pad is and an electrical phase of circuit unit test pin
Even, the grooving is to expose first pad.
The end points of the cabling includes one first pad, and first pad is electrical connected with an IC chip,
The grooving is to expose first pad.
The end points of the cabling includes one first pad, and first pad is electrical connected with a flexible circuit board, institute
It is to expose first pad to state grooving.
Another embodiment of the present invention, it is a kind of manufacture method of low temperature polycrystalline silicon product, including:One base material is provided；Formed
NMOS and PMOS is on the base material；The first metal layer is formed on the NMOS and the PMOS gate insulator, and
It is patterned to form the NMOS and the PMOS grid and at least one first cabling；Form second metal layer and add
The NMOS and PMOS drain electrode and source electrode and at least one second cabling are formed to pattern；Shape interbedded insulating layer
In on the first metal layer and the gate insulator；Flatness layer is formed on NMOS and PMOS, the flatness layer covers
The NMOS and PMOS drain electrode and source electrode and second cabling；The first transparency conducting layer is formed in the flatness layer
On with covering at least a portion flatness layer；Protective layer is formed on the first transparency conducting layer and the flatness layer；Form the
Two transparency conducting layers are on the protective layer；Dig a hole to form an at least grooving, first grooving passes through the flatness layer and institute
State interlayer insulating film, and the grooving transparent is led through first transparency conducting layer, the protective layer and described second
At least one of electric layer layer is to expose the end point of first cabling to the open air.
The end points of first cabling includes one first pad, and first cabling and a circuit unit test pin are electrical
It is connected, first grooving is formed at the top of first pad.
The end points of first cabling includes one first pad, and first cabling and the electrical phase of an IC chip
Even, the grooving be formed at the first top for stating pad.
The end points of first cabling includes one first pad, and first cabling is electrical connected with a flexible circuit board,
The top dug grooving and be formed at first pad.
Grooving of the present invention do not need guiding through the second metal distributed area (such as NMOS and PMOS drain electrode and source electrode and
At least one second cabling), and the first cabling is only formed by the first metal in grooving, then enters line integrated circuit or soft electricity again
The bonding (Bonding) of road plate, interbedded insulating layer of the present invention, positioned at the first metal layer and the gate insulator
On layer, therefore the first cabling (the first metal layer is formed) is via interlayer insulating film and the tin indium oxide of the transparency conducting layer of residual
(ITO) isolation separation is formed, specifically solves prior art, when digging the second grooving of flatness layer, second metal layer is transparent because residual
The tin indium oxide (ITO) of conductive layer can be adjacent cabling short circuit together, the shortcomings that causing the display exception of whole panel.
For the above of the present invention can be become apparent, preferred embodiment cited below particularly, Bing coordinates institute's accompanying drawings, makees
Describe in detail as follows：
【Brief description of the drawings】
Fig. 1 is low temperature polycrystalline silicon (LTPS) structural representation.
Fig. 2 is flatness layer (Planarization, PLN) excavation region schematic diagram in prior art LTPS structures.
Fig. 3 is according to the groovings of the LTPS product structures of embodiments of the present invention and forms first by the first metal layer and walk
The schematic diagram of line.
The second metal layer that Fig. 4 is Fig. 3 is distributed in schematic diagram in the first metal layer structure.
【Embodiment】
The explanation of following embodiment is with reference to additional schema, to illustrate the particular implementation that the present invention can be used to implementation
Example.
It refer to shown in Fig. 1, (be not covered by the present invention's for the structural profile illustration of low-temperature polysilicon film (LTPS)
Grooving 50), the structure has base material 11, N-type metal-oxide semiconductor (NMOS) 41, p-type metal-oxide semiconductor (PMOS)
42 are formed on base material 11, and the transparency conducting layer 22,24 of tin indium oxide (ITO).The base material 11 can be glass, masking
Layer 12 is generally made up of on base material 11 amorphous silicon layer or molybdenum (A-Si/Mo).Wall is located on glass baseplate 11 and covered
Shielding layer 12, wall are generally made up of the barrier layer 13 of silicon nitride layer (SiNx), and silicon dioxide layer 14.NMOS 41 N
Channel layer 15 or PMOS 42 P channel layer 16 are located in silicon dioxide layer 14.Two outboard ends of N channel layer 15, respectively with N+
Type layer 151 and N-Type layer 152, N+Type layer 151 is located at the outermost side of N channel layer 15, N-Type layer 152 is adjacent to N+Type layer
151, the inside of N channel layer 15, be N channel layer 15 polysilicon layer 153 (Poly).Two outboard ends of P channel layer 16, there is P+
Type layer 161, the inside of P channel layer 16, be P channel layer 16 polysilicon layer 162 (Poly).The first metal layer 19 is formed as NMOS
41 and PMOS 42 grid (Gate Electrode, GE), on gate insulator 17, leads to N channel layer 15 or P respectively
Channel layer 16 insulate.Interlayer insulating film 18 (inter-level dielectric, ILD) is located at the first metal layer 19 and grid is exhausted
In edge layer 17.Flatness layer 21 (Planarization, PLN) is located on interlayer insulating film 18.Second metal layer 20 is by passing through layer
Between insulating barrier 18, and gate insulator 17 through hole respectively with N+Type layer 151 and P+Type layer 161 connects.Second metal layer 20
Be formed as the source/drain electrode layer of N-type metal-oxide semiconductor 41 (NMOS) and p-type metal-oxide semiconductor 42 (PMOS)
(Source/Drain,SD).Second transparency conducting layer 24 is located on flatness layer 21.Protective layer 23 (Protective Layer,
PV) on the second transparency conducting layer 24.First transparency conducting layer 22, positioned at protective layer 23 (Protective Layer, PV)
On.First transparency conducting layer 22 and the second transparency conducting layer 24 are typically to be made with tin indium oxide (ITO).First electrically conducting transparent
Layer 22 links through protective layer 23 and flatness layer 21 with second metal layer 20.
Under said structure, as described above, in prior art, as shown in Fig. 2 flatness layer 21 is in the upper of second metal layer 20
Layer, flatness layer 21 are dug a hole after the second grooving 40 of generation, and prior art digs the exposed scope in a hole, generally covers second metal layer
20 formed the second cablings 35, the second pad 34 and with the other parts of second metal layer 20 (such as the NMOS 41 with it is described
PMOS 42 drain electrode and source electrode) intersection.
According to one embodiment of the invention, there is provided a kind of low temperature polycrystalline silicon product structure for lifting yield, as shown in figure 3,
Form grooving 50.Low temperature polycrystalline silicon (LTPS) structure vertical in above-mentioned Fig. 1 is dug a hole the layer that the grooving 50 to be formed passed through, is
The layer being formed on silicon dioxide layer 14 and the first metal layer 19.The first metal layer 19 in addition to forming grid simultaneously
Form the first cabling 55.The grooving 50 extends only through the flatness layer 21 and the interlayer insulating film 18, and the grooving 50
Extend only through at least one of first transparency conducting layer 22, the protective layer 23 and second transparency conducting layer 24 layer
To expose the end point of first cabling 55 to the open air, the first pad 54 for being advantageous to connection is typically formed at the end points.It is vertical to dig
The grooving 50 in hole do not need guiding through the second metal 20 distributed area (such as NMOS 41 and PMOS 42 drain electrode and source electrode and
At least one second cabling 35).
In the present embodiment, the first pad 54 positioned at the end points of the first cabling 55 and circuit unit are surveyed respectively for the grooving 50
First pad 54 of test tube pin connection, the first pad 54 being connected with integrated circuit 33, the first pad 54 being connected with flexible circuit board 32
Go up and expose first pad 54.In the present embodiment, each grooving 50 does not need guiding through the distributed area of second metal layer 20.
As described above, a kind of low temperature polycrystalline silicon (LTPS) product structure of the present invention, is in the low temperature polycrystalline silicon shown in Fig. 1
(LTPS) multiple groovings 50 such as Fig. 3 are dug in structure, so overall structure includes:Base material 11；N-type metal-oxide semiconductor 41
(NMOS) it is located at institute positioned at (base material 11 can be glass) on the base material 11, and p-type metal-oxide semiconductor 42 (PMOS)
State on base material 11；The first metal layer 19, on the NMOS 41 and the PMOS 42 gate insulator 17, described the
One metal level 19 is used for the grid for forming NMOS 41 and PMOS 42 and for forming at least one first cabling 55；
Second metal layer 20, for forming the NMOS 41 and the PMOS 42 drain electrode and source electrode and at least 1
Two cablings 35, some of second cablings 35 can be connected with drain electrodes of the NMOS 41 with the PMOS 42 and source electrode；One
Interlayer insulating film 18, on the first metal layer 19 and the gate insulator 17, therefore (the first gold medal of the first cabling 55
Category layer 19 is formed) isolation separation is formed via the tin indium oxide (ITO) of interlayer insulating film 18 and the transparency conducting layer of residual, specifically
When solving prior art 21 grooving of flatness layer, it is adjacent short-circuit caused by second metal layer 20 the problem of.
Flatness layer 21 is located at the NMOS 41 and the tops of the PMOS 42；First transparency conducting layer 22 is positioned at described flat
The smooth top of layer 21 simultaneously covers described at least a portion of flatness layer 21；Protective layer 23 is located at the flatness layer 21 and described first transparent
The top of conductive layer 22；Second transparency conducting layer 24 is positioned at the top of the protective layer 23, and second transparency conducting layer 24 is via wearing
Drain electrode and source electrode of the through hole of the protective layer 23 and the flatness layer 21 with the NMOS 41 is crossed to be connected.
An at least grooving 50 passes through the flatness layer 21 and the interlayer insulating film 18, and the grooving 50 is described in
At least one of first transparency conducting layer 22, the protective layer 23 and second transparency conducting layer 24 layer is described to expose to the open air
The end point of first cabling 55.
It is that second metal layer 20 is formed to have drain electrode and source electrode in NMOS 41 and PMOS 42 structure, NMOS's 41
Drain electrode and source electrode link the second transparency conducting layer 24, are the basic modules that NMOS 41 and PMOS 42 is Display panel driving,
Second cabling 35 is also formed by second metal layer 20, and some of second cablings 35 can link drain electrode and source electrode with one end, and can
Include other cablings.Fig. 1 and Fig. 3 is refer to, the second metal layer 20 of patterning is located at flatness layer 21 and interlayer insulating film 18
Between, second metal layer 20 is connected with the second transparency conducting layer 24, and second metal layer 20 is to form NMOS 41 and PMOS 42
Source/drain electrode layer (Source/Drain, SD) and the second cabling 35, these parts may be adjacent to each other.In this implementation
In example, as shown in figure 3, at the specific endpoints that the first cabling 55 (the first metal layer 19 is formed) of the patterning in each grooving 50 is stretched
The first pad 54 on, it is possible to reduce adjacent NMOS 41 and the source/drain electrode layer (Source/ of PMOS 42 in prior art
Drain, SD) and the second cabling 35 between it is interfering with each other.
The N-type metal-oxide semiconductor (NMOS) 41, it is by shielding layer 12, silicon dioxide layer 14, N channel layer 15, grid
Pole insulating barrier 17, the first metal layer 19, interlayer insulating film 18, the structure successively covered from lower floor toward upper strata.Wherein N channel layer 15
Have a polysilicon layer 153, two N+ types layers 151, the inner side of the two N+ types layer 151 is each engaged in the two of the N channel layer 15
Outside, the both ends of two N-type layers 152 are each engaged in the medial extremity of the outboard end of polysilicon layer 153 and two N+ types layers 151.
And drain electrode and source electrode, formed by the second metal layer 20, each link the N+ types layer 151 via through hole, the through hole is worn
Located at the interlayer insulating film 18 and the gate insulator 17.
The p-type metal-oxide semiconductor (PMOS) 42, it is by barrier layer 13, silicon dioxide layer 14, P channel layer 16, grid
Pole insulating barrier 17, the first metal layer 19, interlayer insulating film 18, the structure successively covered from lower floor toward upper strata.Wherein P channel layer 16
Have a polysilicon layer 162, two P+ type layers 161, the inner side of the two P+ types layer 161 is each engaged in the polysilicon layer 162
Two outsides.And drain electrode and source electrode, formed by the second metal layer 20, each link the p-type metal oxidation half via through hole
The P+ type layer 161 of conductor 42, the through hole are arranged in the interlayer insulating film 18 and the gate insulator 17.
As described above, Fig. 3 is refer to, to form the first cabling schematic diagram by the first metal in grooving.The present embodiment is specific
In the specific distribution area that the first metal layer 19 that grooving 50 is confined to patterning respectively is extended.The present invention is due to the grooving 50
The flatness layer 21 and the interlayer insulating film 18 are extended only through, and the grooving 50 extends only through first transparency conducting layer
22nd, at least one of the protective layer 23 and second transparency conducting layer 24 layer are to expose the one of first cabling 55 to the open air
End points.The grooving 50 does not need guiding through distributed area (such as NMOS 41 and PMOS 42 drain electrode and the source electrode of second metal layer 20
And at least one second cabling 35).
Fig. 4 is refer to, is the to be distributed in schematic diagram in the structure of the first metal layer 19 for Fig. 3 second metal layer 20.This hair
The end points that bright structure is formed the first cabling 55 by the first metal layer 19 includes one first pad 54, and grooving 50 does not need guiding through the second metal
The distributed area of layer 20, and there is interlayer insulating film 18 to be located on the first metal layer 19 and the gate insulator 17, because
Only expose the grooving 50 of the first pad 54 of the first cabling 55 in this embodiments of the present invention, the groovings of no known techniques exposes the to the open air
Short circuit caused by two metal levels 20 and interference shortcoming.
The present invention provides a kind of manufacture method of low temperature polycrystalline silicon product, refers to Fig. 1 and Fig. 3, methods described includes
Following steps.
A base material 11 is provided, the base material 11 can be glass baseplate 11.
N-type metal-oxide semiconductor (NMOS) 41 is formed with p-type metal-oxide semiconductor (PMOS) 42 in the base material 11
On.The N-type metal-oxide semiconductor (NMOS) 41, it is by shielding layer 12, silicon dioxide layer 14, N channel as shown in fig. 1
Layer 15, gate insulator 17, the first metal layer 19, interlayer insulating film 18, the structure successively covered from lower floor toward upper strata.Wherein N
Channel layer 15 has a polysilicon layer 153, two N+ types layers 151, and the inner side of the two N+ types layer 151 is each engaged in the N channel
Two outsides of layer 15, the both ends of two N-type layers 152 are each engaged in the outboard end of polysilicon layer 153 and two N+ types layers 151
Medial extremity.And drain electrode and source electrode are formed by second metal layer 20, as be described hereinafter, each link the N+ types layer via through hole
151, the through hole is arranged in the interlayer insulating film 18 and the gate insulator 17.The p-type metal-oxide semiconductor
(PMOS) 42, it is as shown in Figure 1, it is barrier layer 13, silicon dioxide layer 14, P channel layer 16, gate insulator 17, the first metal
Layer 19, interlayer insulating film 18, the structure successively covered from lower floor toward upper strata.Wherein P channel layer 16 has a polysilicon layer 162, two P
+ type layer 161, the inner side of the two P+ types layer 161 are each engaged in two outsides of the polysilicon layer 162.And drain electrode and source electrode
It is to be formed by the second metal layer 20, as be described hereinafter, each links via through hole described in the p-type metal-oxide semiconductor 42
P+ type layer 161, the through hole are arranged in the interlayer insulating film 18 and the gate insulator 17.
The first metal layer 19 is formed on the NMOS 41 and the PMOS 42 gate insulator 17, and is subject to figure
Case is to form the NMOS 41 and the PMOS 42 grid and at least one first cabling 55.
Form second metal layer 20 and be patterned to form the NMOS 41 and the PMOS 42 drain electrode and source
Pole and at least one second cabling 35, wherein the second cabling 35 can connect the NMOS 41 and the PMOS 42 drain electrode with
Source electrode；
Flatness layer 21 is formed on NMOS 41 and PMOS 42, the flatness layer 21 cover the NMOS 41 with it is described
PMOS 42 drain electrode and source electrode and second cabling 35.
Formed the first transparency conducting layer 22 on the flatness layer 21 with covering at least a portion flatness layer 21.
Protective layer 23 is formed on the first transparency conducting layer 22 and the flatness layer 21.
The second transparency conducting layer 24 is formed on the protective layer 23.
It is that second metal layer 20 is formed to have drain electrode and source electrode in NMOS 41 and PMOS 42 structure, NMOS's 41
Drain electrode and source electrode link the second transparency conducting layer 24, are the basic modules that NMOS 41 and PMOS 42 is Display panel driving,
What the second cabling 35 was also formed by second metal layer 20, some of second cablings 35 can link drain electrode and source electrode with one end, please
With reference to figure 1 and Fig. 3, the second metal layer 20 of patterning is between flatness layer 21 and interlayer insulating film 18, second metal layer
20 are connected with the second transparency conducting layer 24, and second metal layer 20 forms NMOS 41 and the source/drain electrode layers of PMOS 42
(Source/Drain, SD) and the second cabling 35, these parts may be adjacent to each other.
Then, dig a hole to form an at least grooving 50, the grooving 50 passes through the flatness layer 21 and the interlayer insulating film
18, and the grooving 50 passes through first transparency conducting layer 22, the protective layer 23 and second transparency conducting layer
At least one of 24 layers are to expose the end point of first cabling 55 to the open air.
The first pad 54 can be formed at the end points of first cabling 55, and first cabling 55 can be surveyed with a circuit unit
Test tube pin is electrical connected, or is electrical connected with the chip of an integrated circuit 33, or is electrical connected with a flexible circuit board 32.The digging
Groove 50 is formed at the top of the first pad pad 54.
The embodiment of structures and methods of the present invention provides the technological process beneficial effect of low-temperature polysilicon film (LTPS), by
In there is interlayer insulating film 18 to be located on the first metal layer 19 and the gate insulator 17, therefore the first cabling 55 (
One metal level 19 is formed) isolation separation is formed via the tin indium oxide (ITO) of interlayer insulating film 18 and the transparency conducting layer of residual,
Grooving substantially only exposes the end points for the first cabling 55 that the first metal layer 19 is formed, and the specific prior art flatness layer 21 that solves is dug
During groove, reduce because transparency conducting layer (ITO) second cabling 35, second caused by the residual of the distributed areas of second metal layer 20
Pad 34 and the intersection short circuit with the other parts of second metal layer 20, lift the quality of Display panel.
The mask set of grooving 50 provided by the invention, the only non-display area in periphery are only exposed to specific endpoints,
Wherein grooving 50 does not need guiding through distributed area (such as NMOS 41 and PMOS 42 drain electrode and the source electrode and at least of the second metal 20
One second cabling 35).Therefore only the first pad 54 and the first cabling of part 55 of the first cabling 55 are exposed, it is not necessary to will
Second metal layer 20, which exposes, to be come, and avoids prior art configurations because exposed at the distributed areas that grooving 40 makes the second metal belong to 20
The defects of causing.Therefore according to the present invention, when entering bonding (Bonding) of line integrated circuit 33 or flexible circuit board 32, just
Adjacent signals line will not be caused short-circuit due to the residual of transparency conducting layer (ITO), so as to reduce the display of whole panel exception.
Embodiments of the invention can apply low temperature polycrystalline silicon liquid crystal display (LCD), be useful in wide viewing angle technology
On (Advanced Fringe Field Switching, AFFS), it can also apply in Organic Light Emitting Diode (Organic
Light-Emitting Diode, OLED) on.
In summary, although the present invention is disclosed above with preferred embodiment, above preferred embodiment Bing is not used to limit
The system present invention, one of ordinary skill in the art, without departing from the spirit and scope of the present invention, it can make various changes and profit
Decorations, therefore protection scope of the present invention is defined by the scope that claim defines.
Claims (4)
1. a kind of low temperature polycrystalline silicon (LTPS) product structure, including:
One base material；
At least a N-type metal-oxide semiconductor (NMOS) is located on the base material；
At least a p-type metal-oxide semiconductor (PMOS) is located on the base material；
One the first metal layer, on a NMOS and PMOS gate insulator, the first metal layer is used for shape
Into a grid and for forming at least one first cabling；
One second metal layer, for forming the NMOS and the PMOS drain electrode and source electrode and at least one second cabling；
Interbedded insulating layer, on the first metal layer and the gate insulator；
One flatness layer is located above the NMOS and PMOS；
One first transparency conducting layer is located above the flatness layer and covers described flatness layer at least a portion；
One protective layer is located above the flatness layer and first transparency conducting layer；
One second transparency conducting layer is located above the protective layer, second transparency conducting layer via through the protective layer with
And drain electrode and source electrode of the through hole of the flatness layer with the NMOS are connected；
An at least grooving, the grooving pass through the flatness layer and the interlayer insulating film, and the grooving is through described the
At least one of one transparency conducting layer, the protective layer and second transparency conducting layer layer is to expose first cabling to the open air
End point；
The end points of wherein described first cabling includes one first pad, and first pad is and circuit unit test pin electricity
Property be connected, the grooving be expose it is described first pad；
The end points of first cabling includes one first pad, and first pad is electrical connected with an IC chip,
The grooving is to expose first pad；And
The end points of first cabling includes one first pad, and first pad is electrical connected with a flexible circuit board, institute
It is to expose first pad to state grooving.
2. low temperature polycrystalline silicon product structure according to claim 1, wherein, the N-type metal-oxide semiconductor includes:
One shielding layer is located on the base material with covering part base material；
One barrier layer is located on the shielding layer and base material；
One silicon dioxide layer is located on barrier layer；
One N channel layer is located in silicon dioxide layer, and the N channel layer has a polysilicon layer, two N+Type layer, two N+Type layer
Inner side is each engaged in two outsides of the N channel layer, two N-The both ends of type layer are each engaged in the polysilicon layer outboard end
And two N+The medial extremity of type layer；
The gate insulator, on the N channel layer and the silicon dioxide layer；
The first metal layer, via the gate insulator and the N channel layer dielectric separation；
Interbedded insulating layer, positioned at N-type metal-oxide semiconductor (NMOS) the superiors；And
Drain electrode and source electrode, are formed by the second metal layer, each link the N via through hole+Type layer, the through hole are arranged in
The interlayer insulating film and the gate insulator.
3. low temperature polycrystalline silicon product structure according to claim 1, wherein, the p-type metal-oxide semiconductor, including:
One barrier layer is located on the base material；
One silicon dioxide layer is located on barrier layer；
In one P channel layer position silicon dioxide layer, the P channel layer has a polysilicon layer, two P+Type layer, two P+Type layer it is interior
Side is each engaged in two outsides of the polysilicon layer；
The gate insulator, on the P channel layer and the silicon dioxide layer；
The first metal layer, via the gate insulator and the P channel layer and dielectric separation；
Interbedded insulating layer, positioned at p-type metal-oxide semiconductor (PMOS) the superiors；And
Drain electrode and source electrode, are formed by the second metal layer, and the institute of the p-type metal-oxide semiconductor is each linked via through hole
State P+Type layer, the through hole are arranged in the interlayer insulating film and the gate insulator.
4. a kind of manufacture method of low temperature polycrystalline silicon product, including:
One base material is provided；
NMOS and PMOS is formed on the base material；
The first metal layer is formed on the NMOS and the PMOS gate insulator, and is patterned with described in composition
NMOS and PMOS grid and at least one first cabling；
Form second metal layer and be patterned to form the NMOS and PMOS drain electrode and source electrode and at least one
Second cabling；
Shape interbedded insulating layer is on the first metal layer and the gate insulator；
Flatness layer is formed on NMOS and PMOS, the flatness layer cover the NMOS and PMOS drain electrode and source electrode and
Second cabling；
Formed the first transparency conducting layer on the flatness layer with covering at least a portion flatness layer；
Protective layer is formed on the first transparency conducting layer and the flatness layer；
The second transparency conducting layer is formed on the protective layer；
Dig a hole to form an at least grooving, the grooving passes through the flatness layer and the interlayer insulating film, and the grooving to wear
It is described to expose to the open air to cross at least one of first transparency conducting layer, the protective layer and second transparency conducting layer layer
The end point of first cabling；
The end points of wherein described first cabling includes one first pad, and first cabling and a circuit unit test pin are electrical
It is connected, the grooving is formed at the top of first pad；
The end points of first cabling includes one first pad, and first cabling is electrical connected with an IC chip, institute
State grooving be formed at the first top for stating pad；And
The end points of first cabling includes one first pad, and first cabling is electrical connected with a flexible circuit board, described
Grooving is formed at the top of the pad.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410852082.2A CN104465674B (en) | 2014-12-31 | 2014-12-31 | Low temperature polycrystalline silicon (LTPS) product structure and manufacture method |
| PCT/CN2015/070524 WO2016106828A1 (en) | 2014-12-31 | 2015-01-12 | Low temperature poly-silicon product structure and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410852082.2A CN104465674B (en) | 2014-12-31 | 2014-12-31 | Low temperature polycrystalline silicon (LTPS) product structure and manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104465674A CN104465674A (en) | 2015-03-25 |
| CN104465674B true CN104465674B (en) | 2018-01-02 |
Family
ID=52911464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410852082.2A Active CN104465674B (en) | 2014-12-31 | 2014-12-31 | Low temperature polycrystalline silicon (LTPS) product structure and manufacture method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104465674B (en) |
| WO (1) | WO2016106828A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106920812B (en) * | 2015-12-25 | 2019-10-25 | 上海和辉光电有限公司 | A kind of OLED display panel and preparation method thereof |
| KR102460997B1 (en) * | 2016-02-16 | 2022-11-01 | 삼성디스플레이 주식회사 | Display substrate, methods of manufacturing the same and display devices including the same |
| CN106653814B (en) * | 2016-12-28 | 2020-02-14 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
| CN109407434B (en) * | 2018-11-22 | 2020-11-24 | 武汉华星光电技术有限公司 | Liquid crystal display device having a plurality of pixel electrodes |
| CN112542086B (en) * | 2019-09-23 | 2023-03-31 | 上海和辉光电股份有限公司 | Display panel and display device |
| CN112086576B (en) * | 2020-09-07 | 2022-09-09 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1254948A (en) * | 1998-11-19 | 2000-05-31 | 三星电子株式会社 | Thin-film transistor array panel and its making method |
| CN101008750A (en) * | 2006-01-26 | 2007-08-01 | 爱普生映像元器件有限公司 | Liquid crystal apparatus and electronic device |
| CN101110430A (en) * | 2006-07-18 | 2008-01-23 | 统宝光电股份有限公司 | System for displaying images including thin film transistor device and method for fabricating the same |
| CN102411239A (en) * | 2010-09-20 | 2012-04-11 | 乐金显示有限公司 | Liquid crystal display device and method for manufacturing the same |
| CN103681488A (en) * | 2013-12-16 | 2014-03-26 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4662647B2 (en) * | 2001-03-30 | 2011-03-30 | シャープ株式会社 | Display device and manufacturing method thereof |
| TWI290006B (en) * | 2002-05-03 | 2007-11-11 | Ritdisplay Corp | A method for fabricating LTPS-OLED |
| KR101775726B1 (en) * | 2010-11-26 | 2017-09-07 | 엘지디스플레이 주식회사 | Method for fabricating Liquid Crystal Display Device |
-
2014
- 2014-12-31 CN CN201410852082.2A patent/CN104465674B/en active Active
-
2015
- 2015-01-12 WO PCT/CN2015/070524 patent/WO2016106828A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1254948A (en) * | 1998-11-19 | 2000-05-31 | 三星电子株式会社 | Thin-film transistor array panel and its making method |
| CN101008750A (en) * | 2006-01-26 | 2007-08-01 | 爱普生映像元器件有限公司 | Liquid crystal apparatus and electronic device |
| CN101110430A (en) * | 2006-07-18 | 2008-01-23 | 统宝光电股份有限公司 | System for displaying images including thin film transistor device and method for fabricating the same |
| CN102411239A (en) * | 2010-09-20 | 2012-04-11 | 乐金显示有限公司 | Liquid crystal display device and method for manufacturing the same |
| CN103681488A (en) * | 2013-12-16 | 2014-03-26 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016106828A1 (en) | 2016-07-07 |
| CN104465674A (en) | 2015-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104465674B (en) | Low temperature polycrystalline silicon (LTPS) product structure and manufacture method | |
| US11456321B2 (en) | Method for manufacturing display substrate, display substrate and display device | |
| US10288925B2 (en) | Liquid crystal display device and manufacturing method thereof | |
| CN106558594A (en) | Array base palte, display floater, display device and preparation method | |
| US9947691B2 (en) | Array substrate, manufacturing method thereof and display panel | |
| CN108376688A (en) | A kind of photosensory assembly and preparation method thereof, array substrate, display device | |
| CN109742113A (en) | A kind of array substrate, preparation method and relevant apparatus | |
| CN103165540B (en) | Array substrate and manufacturing method thereof | |
| CN104218019A (en) | Thin film transistor array substrate and method of manufacturing the same | |
| CN108511465A (en) | Embedded touch array substrate, display panel and manufacturing method | |
| KR102333563B1 (en) | Organic Light Emitting Display Device and Method For Repairing Of Pixel | |
| CN106920836A (en) | A kind of thin film transistor (TFT) and preparation method thereof, array base palte, display device | |
| CN102044557A (en) | Organic light emitting diode display device and method of fabricating the same | |
| CN104600030A (en) | Array substrate, manufacturing method of array substrate and display device | |
| CN103187423A (en) | Oxide thin film transistor array substrate, manufacturing method of array substrate, and display panel | |
| CN112310119A (en) | Display panel and preparation method | |
| CN108054140A (en) | FFS mode array substrate and its manufacturing method | |
| KR20050048835A (en) | Thin film transistor array panel | |
| CN102779830B (en) | Metallic oxide display device and manufacturing method thereof | |
| CN104022124B (en) | A kind of flexible display substrates and preparation method thereof, flexible display apparatus | |
| CN102709283A (en) | Low temperature polysilicon thin film transistor (LTPS TFT) array substrate and manufacturing method thereof | |
| US20150011055A1 (en) | Manufacturing method of low temperature poly-silicon tft array substrate | |
| CN104538353B (en) | Low temperature polycrystalline silicon (LTPS) product structure and manufacture method | |
| CN203134810U (en) | Array substrate and display device | |
| CN206584934U (en) | A kind of thin film transistor (TFT), array base palte, display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |