CN102709283A - Low temperature polysilicon thin film transistor (LTPS TFT) array substrate and manufacturing method thereof - Google Patents
Low temperature polysilicon thin film transistor (LTPS TFT) array substrate and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a low temperature polysilicon thin film transistor (LTPS TFT) array substrate and a manufacturing method thereof. The array substrate comprises a substrate, an active layer, source and drain electrodes, a gate insulating layer, a gate electrode, a pixel electrode and a protective layer, wherein an LTPS TFT is a top gate TFT; and the active layer and a conducting structure thereon are formed by a half tone or gray tone primary composition process. By the method, the process of manufacturing the LTPS TFT array substrate can be simplified.
Description
Technical field
The present invention relates to the manufacturing technology of thin-film transistor (TFT) array base palte, relate in particular to a kind of low-temperature polysilicon film transistor (LTPS TFT) array base palte and preparation method thereof.
Background technology
Because the defect problem of amorphous silicon (a-Si) itself, as, the ON state current that defect state causes more is low, mobility is low, poor stability, makes amorphous silicon be restricted in the application in a lot of fields.In order to remedy the defective of amorphous silicon itself, enlarge the application of Related product in association area, low temperature polycrystalline silicon (LTPS is called for short p-Si) technology is arisen at the historic moment.
Fig. 1 is the structural representation of LTPS tft array substrate in the prior art.As shown in Figure 1, the LTPSTFT array base palte comprises: substrate 1, resilient coating 2, active layer 3, gate insulation layer (GI) 4, gate electrode 5, first insulating barrier 6, source-drain electrode 7, second insulating barrier 8, pixel electrode 9, protective layer 10.In order to make this LTPS tft array substrate, need utilize seven mask plates to carry out composition technology seven times, be respectively:
1, utilize active layer mask plate (a-Si Mask) to form active layer 3 through composition technology;
2, utilize gate electrode mask plate (Gate Mask) to form gate electrode 5 through composition technology;
3, utilize contact hole mask plate (Contact Mask) to be formed for connecting the contact hole of source-drain electrode 7 and active layer 3 through composition technology;
4, utilize source-drain electrode mask plate (S/D Mask) to form source-drain electrode 7 through composition technology;
5, utilize via hole mask plate (VIA Hole Mask) to form the bridge joint via hole between pixel electrode 9 and the source-drain electrode 7 through composition technology;
6, utilize pixel electrode mask plate (ITO Mask) to form pixel electrode 9 through composition technology;
7, utilize protective layer mask plate (Resin Mask) to form protective layer 10 through composition technology; Wherein, the material of protective layer is generally resin, and this procedure is mainly used in Organic Light Emitting Diode (OLED) device and forms planarization layer.
Can find out, the manufacture craft more complicated of this LTPS tft array substrate in the prior art, the making flow process is various, and cost of manufacture is high, therefore is difficult to be at war with the non-crystalline silicon tft product, thereby makes the LTPS technical development slow.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of LTPS tft array substrate and preparation method thereof, simplifies the making flow process of LTPS tft array substrate.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of LTPS tft array substrate comprises: substrate, active layer, source-drain electrode, gate insulation layer, gate electrode, pixel electrode and protective layer; Wherein, said LTPS TFT is top gate type TFT; The conductive structure of said active layer and its top forms through halftoning or composition technology of gray tone.
Wherein, the conductive structure above the said active layer is a source-drain electrode.
Wherein, the conductive structure of said active layer top is the data wire metal level p-wire in the neighboring area of said array base palte, and said data wire metal level p-wire contacts with gate electrode metal layer p-wire in the said neighboring area or do not contact.
Wherein, the conductive structure of said active layer top is the data cable lead wire in the neighboring area of said array base palte, and said data wire metal level p-wire does not contact with gate electrode metal layer p-wire in the said neighboring area.
Wherein, has transparency conducting layer above the said gate electrode metal layer p-wire.
Wherein, said array base palte also comprises resilient coating, and said resilient coating is positioned at the below of top, active layer and the gate insulation layer of substrate.
A kind of manufacture method of LTPS tft array substrate is produced substrate, active layer, source-drain electrode, gate insulation layer, gate electrode, pixel electrode and protective layer; Wherein, said LTPS TFT is top gate type TFT, and said method comprises:
Form the conductive structure of said active layer and its top through halftoning or composition technology of gray tone.
Wherein, the conductive structure above the said active layer is a source-drain electrode.
Wherein, the conductive structure of said active layer top is the data wire metal level p-wire in the neighboring area of said array base palte, and said data wire metal level p-wire contacts with gate electrode metal layer p-wire in the said neighboring area or do not contact.
Wherein, the conductive structure of said active layer top is the data cable lead wire in the neighboring area of said array base palte, and said data wire metal level p-wire does not contact with gate electrode metal layer p-wire in the said neighboring area.
Wherein, has transparency conducting layer above the said gate electrode metal layer p-wire.
Said method also comprises: make resilient coating, said resilient coating is positioned at the below of top, active layer and the gate insulation layer of substrate.
Can find out by above technical scheme; Because active layer and utilize same mask plate through making with a composition technology with the conductive structure of its top, like this, the making of LTPS tft array substrate of the present invention has only utilized five mask plates and has only carried out composition technology five times; Therefore; Compared with prior art, the present invention has simplified the making flow process of LTPS tft array substrate, has saved the production time of LTPS tft array substrate; Reduce the cost of manufacture of LTPS tft array substrate, improved the quality of LTPS tft array substrate.
Description of drawings
Fig. 1 is the structural representation of LTPS tft array substrate in the prior art;
Fig. 2 is the structural representation of the embodiment of the invention one LTPS tft array substrate;
Fig. 3 utilizes first mask plate for the embodiment of the invention one and forms the sketch map of active layer, source-drain electrode and data wire metal level p-wire;
Fig. 4 utilizes second mask plate for the embodiment of the invention one and forms the sketch map of gate insulation layer contact hole;
Fig. 5 utilizes the 3rd mask plate for the embodiment of the invention one and forms the sketch map of gate electrode and gate electrode metal layer p-wire;
Fig. 6 utilizes the 4th mask plate for the embodiment of the invention one and forms the sketch map of pixel electrode;
Fig. 7 is the structural representation of the embodiment of the invention two LTPS tft array substrates;
Fig. 8 is the structural representation of the embodiment of the invention three LTPS tft array substrates;
Fig. 9 is the structural representation of the embodiment of the invention four LTPS tft array substrates.
Embodiment
Basic thought of the present invention is: in order to reduce mask plate quantity; Improve the involutory precision of active layer and source-drain electrode; Utilize gray mask plate (GTM; Gray Tone Mask) or half-tone mask plate (HTM, Half Tone Mask) directly produce active layer and source-drain electrode through a composition technology.
LTPS TFT of the present invention is top gate type TFT, and LTPS tft array substrate of the present invention comprises: substrate, active layer, source-drain electrode, gate insulation layer, gate electrode, pixel electrode and protective layer; The conductive structure of wherein said active layer and its top forms through halftoning or composition technology of gray tone.
Wherein, the conductive structure above the said active layer is a source-drain electrode.
Wherein, the conductive structure of said active layer top is the data wire metal level p-wire in the neighboring area of said array base palte.
Said data wire metal level p-wire contacts with gate electrode metal layer p-wire in the said neighboring area.Said gate electrode metal layer p-wire top also can have transparency conducting layer; Transparency conducting layer on the one hand can grill-protected electrode metal layer p-wire; Also can form parallel resistance on the other hand, reduce the resistance of gate electrode metal layer p-wire with gate electrode metal layer p-wire.
Said data wire metal level p-wire does not contact with gate electrode metal layer p-wire in the said neighboring area.Said gate electrode metal layer p-wire top also can have transparency conducting layer, connects data wire metal level p-wire and gate electrode metal layer p-wire to realize both conductings through transparency conducting layer.
Wherein, the conductive structure of said active layer top is the data cable lead wire in the neighboring area of said array base palte, and said data wire metal level p-wire does not contact with gate electrode metal layer p-wire in the said neighboring area.Said gate electrode metal layer p-wire top also can have transparency conducting layer, with grill-protected electrode metal layer p-wire.
For obtaining above-mentioned LTPS tft array substrate, the corresponding manufacture method that a kind of LTPS tft array substrate is provided of the present invention, said method comprises: the conductive structure that forms said active layer and its top through halftoning or composition technology of gray tone.
The present invention is further specified through several embodiment below in conjunction with accompanying drawing.Need to prove that before this zone shown in dotted line the right is the neighboring area of LTPS tft array substrate in the application institute drawings attached, is not to obtain through dissecing same plane with the pixel region shown in the dotted line left side; But can obtain the figure of two regional equivalent layers in order to explain simultaneously with one deck here, so both are drawn in together through etching.
Embodiment one
Shown in the left area of Fig. 2 dotted line; The LTPS TFT of the embodiment of the invention one is top gate type TFT, and the LTPS tft array substrate of embodiment one comprises: substrate 1, active layer 3, source-drain electrode 7, gate insulation layer 4, gate electrode 5, pixel electrode 9 and protective layer 10;
Wherein, active layer 3 is positioned at the top of substrate 1; Source-drain electrode 7 is positioned at the top of active layer 3; Gate insulation layer 4 is positioned at the top of active layer 3, source-drain electrode 7 and substrate 1; Gate electrode 5 is positioned at the top of gate insulation layer 4; Pixel electrode 9 is positioned at the top of gate insulation layer 4 and source-drain electrode 7; Protective layer 10 is positioned at the top of gate insulation layer 4, gate electrode 5 and partial pixel electrode 9.
Wherein, active layer 3 forms through halftoning or composition technology of gray tone with source-drain electrode 7.
The LTPS tft array substrate can also comprise buffering (Buffer) layer 2, is positioned at the below of top, active layer 3 and the gate insulation layer 4 of substrate 1.
Shown in the zone, the right of Fig. 2 dotted line; LTPS tft array substrate of the present invention also has the neighboring area, and this neighboring area comprises: substrate 1, active layer 3, data wire metal level p-wire 7 ', gate insulation layer 4, gate electrode metal layer p-wire 5 ' and protective layer 10.Wherein, the active layer 3 in the active layer in the neighboring area 3 and data wire metal level p-wire 7 ' and the pixel region forms through halftoning or composition technology of gray tone with source-drain electrode 7.As can beappreciated from fig. 2; Data wire metal level p-wire 7 ' contacts with gate electrode metal layer p-wire 5 ', this be because: in some product, or in the zones of different with a kind of product; Some place in the peripheral circuit of array base palte; As the place that exists two fence electrode metal level p-wires to intersect, may gate electrode metal layer p-wire and data wire metal level p-wire be linked together, form path.
The manufacture method of the LTPS tft array substrate of the embodiment of the invention one may further comprise the steps:
Step 101 deposits resilient coating 2 and a-Si layer successively on substrate 1, and utilizes crystallization method to make the a-Si crystallization form p-Si; Then carry out p-Si and mix, so that the type of decision TFT channel region (Channel); Again at the data wire metal level that is used to form source-drain electrode and data wire metal level p-wire through deposition on the substrate 1 of aforementioned processing; Utilize HTM or GTM that p-Si layer and data wire metal level are carried out composition technology one time at last, obtain active layer 3, source-drain electrode 7 and data wire metal level p-wire 7 ', as shown in Figure 3.
Here, said HTM or GTM are first mask plate; Utilize HTM or GTM directly to produce source-drain electrode 7 and active layer 3, and source-drain electrode 7 is positioned at the top of active layer 3, therefore realized being connected of source-drain electrode 7 and active layer 3, so also just saved the contact hole mask plate of mentioning in the background technology.And utilize HTM or GTM directly to produce source-drain electrode 7 and can improve the involutory precision of active layer 3 and source-drain electrode 7, and then improved the quality of LTPS tft array substrate with active layer 3.
Alternatively, in order to save the activity duration (Tact Time), can not deposit resilient coating 2.
Wherein, said crystallization method has quasi-molecule laser annealing (ELA), solid phase crystallization (SPC) etc.
In addition, how to utilize HTM or GTM to be lithographically prior art, repeat no more at this.
Step 102; At the substrate of handling through step 101 2 deposition gate insulation layers 4; And utilize the via hole mask plate that gate insulation layer is carried out photoetching, form first grid insulating barrier contact hole (GI Contact Hole) 11 in needs source-drain electrode 7 and pixel electrode 9 contacted places, form the second gate insulation layer contact hole 11 ' in needs data wire metal level p-wire 7 ' and gate electrode metal layer p-wire 5 ' the contacted place; Carry out the TFT channel region then and mix,, thereby make TFT constitute metal-oxide semiconductor (MOS) (MOS) construction of switch so that make TFT channel region and source-drain electrode district form the P-N knot, as shown in Figure 4.
Here, said via hole mask plate is second mask plate.
Step 103 at the substrate of handling through step 102 2 deposition gate electrode metal layers, and utilizes the gate electrode mask plate that the gate electrode metal layer is carried out photoetching, obtains gate electrode 5 and gate electrode metal layer p-wire 5 '.
Wherein, gate electrode metal layer p-wire 5 ' is positioned at that the second gate insulation layer contact hole 11 ' is located and the top of the gate insulation layer 4 that the second gate insulation layer contact hole 11 ' links to each other; Because gate electrode metal layer p-wire 5 ' contacts with data wire metal level p-wire 7 ', so realized both conductings, can be used for testing as shown in Figure 5.
Here, said gate electrode mask plate is the 3rd mask plate.
Step 104, deposit transparent conductive layer on the substrate of handling through step 103 1, and utilize the pixel electrode mask plate that transparency conducting layer is carried out composition technology, obtain pixel electrode 9.
Wherein, pixel electrode 9 is positioned at the top of the gate insulation layer 4 that first grid insulating barrier contact hole 11 places and first grid insulating barrier contact hole 11 link to each other, and is as shown in Figure 6.
Wherein, the material of transparency conducting layer can be tin indium oxide (ITO).
Here, said pixel electrode mask plate is the 4th mask plate.
Step 105; Deposition protective layer 10 on the substrate of handling through step 104 1 behind the deposition protective layer 10, utilizes the protective layer mask plate that protective layer 10 is carried out photoetching; Need tapping to form protective layer via hole 12 at pixel electrode 9; Pixel electrode 9 just can directly contact the OLED device material as the male or female of OLED device like this, and is as shown in Figure 2.
Wherein, the protective layer 10 that is deposited is used for protecting gate electrode 5, gate electrode metal layer p-wire 5 ' and the grid line lead-in wire (not shown) that exposes, and also is used for protecting the irregular to prevent that it from causing damage to the OLED device of ITO edge; The material of said protective layer is insulating material such as resin.
Here, said protective layer mask plate is the 5th mask plate.
Embodiment two
As shown in Figure 7; The difference of the LTPS tft array substrate of embodiment two and the LTPS tft array substrate of embodiment one is: gate electrode metal layer p-wire 5 ' only is positioned at the top of gate insulation line 4; Gate electrode metal layer p-wire 5 ' do not contact with data wire metal level p-wire 7 '; Because in some product, do not need gate electrode metal layer p-wire 5 ' and the 7 ' conducting of data wire metal level p-wire.
The LTPS tft array substrate of making embodiment two is with the difference of the LTPS tft array substrate of making embodiment one: in step 102; Only, be not formed for making data wire metal level p-wire 7 ' and gate electrode metal layer p-wire 5 ' the contacted second gate insulation layer contact hole 11 at needs source-drain electrode 7 and the pixel electrode 9 contacted local first grid insulating barrier contact holes 11 that form.
In addition, in this embodiment, Reference numeral 5 ' also can be represented the grid line lead-in wire, and Reference numeral 7 ' also can be represented data cable lead wire.Should be appreciated that grid line lead-in wire and not conducting of data cable lead wire.
Embodiment three
As shown in Figure 8, the LTPS tft array substrate of embodiment three and the difference of the LTPS tft array substrate of embodiment one only are: transparency conducting layer 9 also is positioned at gate electrode metal layer p-wire 5 ' top.
The LTPS tft array substrate of making embodiment three only is with the difference of the LTPS tft array substrate of making embodiment one: in step 104; Transparency conducting layer on can reserve part gate electrode metal layer p-wire 5 ' when carrying out composition technology; On the one hand can grill-protected electrode metal layer p-wire 5 '; Transparency conducting layer also can form parallel resistance with gate electrode metal layer p-wire 5 ' on the other hand, reduces the resistance of gate electrode metal layer p-wire 5 '.
Embodiment four
As shown in Figure 9; The difference of the LTPS tft array substrate of embodiment four and the LTPS tft array substrate of embodiment three is: gate electrode metal layer p-wire 5 ' only is positioned at the top of gate insulation line 4, and gate electrode metal layer p-wire 5 ' do not contact with data wire metal level p-wire 7 '.
The LTPS tft array substrate of making embodiment four is with the difference of the LTPS tft array substrate of making embodiment three: in step 102; Only, be not formed for making data wire metal level p-wire 7 ' and gate electrode metal layer p-wire 5 ' the contacted second gate insulation layer contact hole 11 at needs source-drain electrode 7 and the pixel electrode 9 contacted local first grid insulating barrier contact holes 11 that form.
In the present embodiment, can connect data wire metal level p-wires 7 ' and gate electrode metal layer p-wire 5 ' to realize both conductings through transparency conducting layer 9.
In addition, in this embodiment, Reference numeral 5 ' also can be represented the grid line lead-in wire, and Reference numeral 7 ' also can be represented data cable lead wire.Should be appreciated that grid line lead-in wire and not conducting of data cable lead wire.
The LTPS tft array substrate that the present invention makes can be applied to association areas such as LCD (LCD), OLED.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.
Claims (12)
1. low-temperature polysilicon film transistor LTPS tft array substrate, said array base palte comprises: substrate, active layer, source-drain electrode, gate insulation layer, gate electrode, pixel electrode and protective layer; Wherein, said LTPS TFT is top gate type TFT; It is characterized in that the conductive structure of said active layer and its top forms through halftoning or composition technology of gray tone.
2. LTPS tft array substrate according to claim 1 is characterized in that, the conductive structure of said active layer top is a source-drain electrode.
3. LTPS tft array substrate according to claim 1; It is characterized in that; The conductive structure of said active layer top is the data wire metal level p-wire in the neighboring area of said array base palte, and said data wire metal level p-wire contacts with gate electrode metal layer p-wire in the said neighboring area or do not contact.
4. LTPS tft array substrate according to claim 1; It is characterized in that; The conductive structure of said active layer top is the data cable lead wire in the neighboring area of said array base palte, and said data wire metal level p-wire does not contact with gate electrode metal layer p-wire in the said neighboring area.
5. according to claim 3 or 4 described LTPS tft array substrates, it is characterized in that said gate electrode metal layer p-wire top has transparency conducting layer.
6. LTPS tft array substrate according to claim 1 is characterized in that said array base palte also comprises resilient coating, and said resilient coating is positioned at the below of top, active layer and the gate insulation layer of substrate.
7. the manufacture method of a LTPS tft array substrate is produced substrate, active layer, source-drain electrode, gate insulation layer, gate electrode, pixel electrode and protective layer; Wherein, said LTPS TFT is top gate type TFT, it is characterized in that, said method comprises:
Form the conductive structure of said active layer and its top through halftoning or composition technology of gray tone.
8. the manufacture method of LTPS tft array substrate according to claim 7 is characterized in that, the conductive structure of said active layer top is a source-drain electrode.
9. the manufacture method of LTPS tft array substrate according to claim 7; It is characterized in that; The conductive structure of said active layer top is the data wire metal level p-wire in the neighboring area of said array base palte, and said data wire metal level p-wire contacts with gate electrode metal layer p-wire in the said neighboring area or do not contact.
10. the manufacture method of LTPS tft array substrate according to claim 7; It is characterized in that; The conductive structure of said active layer top is the data cable lead wire in the neighboring area of said array base palte, and said data wire metal level p-wire does not contact with gate electrode metal layer p-wire in the said neighboring area.
11. the manufacture method according to claim 9 or 10 described LTPS tft array substrates is characterized in that, said gate electrode metal layer p-wire top has transparency conducting layer.
12. the manufacture method of LTPS tft array substrate according to claim 7 is characterized in that, said method also comprises: make resilient coating, said resilient coating is positioned at the below of top, active layer and the gate insulation layer of substrate.
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| CN201110140282.1A CN102709283B (en) | 2011-05-27 | 2011-05-27 | Low temperature polysilicon thin film transistor (LTPS TFT) array substrate and manufacturing method thereof |
| US13/481,002 US8883572B2 (en) | 2011-05-27 | 2012-05-25 | Manufacturing method of low temperature poly-silicon TFT array substrate |
| US14/495,039 US9349759B2 (en) | 2011-05-27 | 2014-09-24 | Manufacturing method of low temperature poly-silicon TFT array substrate |
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| CN111493865A (en) * | 2020-05-06 | 2020-08-07 | 浙江大学 | Cortical electroencephalogram electrode and array capable of being used for multi-modal observation of brain |
| CN111493865B (en) * | 2020-05-06 | 2021-05-14 | 浙江大学 | Cortical electroencephalogram electrode and array capable of being used for multi-modal observation of brain |
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