CN206584934U - A kind of thin film transistor (TFT), array base palte, display device - Google Patents
A kind of thin film transistor (TFT), array base palte, display device Download PDFInfo
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- CN206584934U CN206584934U CN201720324359.3U CN201720324359U CN206584934U CN 206584934 U CN206584934 U CN 206584934U CN 201720324359 U CN201720324359 U CN 201720324359U CN 206584934 U CN206584934 U CN 206584934U
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- 239000010409 thin film Substances 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 230000004888 barrier function Effects 0.000 claims abstract description 64
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 47
- 239000000463 material Substances 0.000 claims description 24
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 description 28
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 239000010408 film Substances 0.000 description 13
- 239000000758 substrate Substances 0.000 description 13
- 238000000059 patterning Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000002161 passivation Methods 0.000 description 7
- 229910021419 crystalline silicon Inorganic materials 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 230000018199 S phase Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- JZLMRQMUNCKZTP-UHFFFAOYSA-N molybdenum tantalum Chemical compound [Mo].[Ta] JZLMRQMUNCKZTP-UHFFFAOYSA-N 0.000 description 1
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Abstract
The utility model embodiment provides a kind of thin film transistor (TFT), array base palte, display device, is related to technical field of semiconductors, in TFT manufacturing process, can reduce the probability that defect is produced in semiconductor active layer.The thin film transistor (TFT) includes bottom-gate, and bottom gate insulating barrier, semiconductor active layer, the first insulating barrier being set in turn in bottom-gate.Thin film transistor (TFT) also includes being arranged at source electrode and drain electrode of first insulating barrier away from bottom-gate side.First insulating barrier is respectively arranged with via in the position of correspondence source electrode and drain electrode.The ohmic contact layer of covering semiconductor active layer is provided with semiconductor active layer in the position of the above-mentioned via of correspondence.Source electrode, drain electrode are in contact by different vias with ohmic contact layer respectively.The thin film transistor (TFT) is used to play a part of switch or driving load in circuit.
Description
Technical field
The utility model is related to technical field of semiconductors, more particularly to a kind of thin film transistor (TFT), array base palte, display dress
Put.
Background technology
Liquid crystal display device (Liquid Crystal Display, LCD) or Organic Light Emitting Diode (Organic
Light Emitting Diode, OLED) display device array base palte on be provided with multiple thin film transistor (TFT)s (Thin Film
Transistor, TFT) it is used to be driven the sub-pix of above-mentioned display device.Prior art in TFT manufacturing process,
Influenceed by manufacture craft, TFT semiconductor active layer can be caused to produce more defect, so that cause TFT in conducting, ditch
The carrier produced in road is easily captured in transmitting procedure by drawbacks described above, so that carrier mobility is reduced, to TFT's
Performance is impacted.
Utility model content
Embodiment of the present utility model provides a kind of thin film transistor (TFT), array base palte, display device, in TFT making
Cheng Zhong, can reduce the probability that defect is produced in semiconductor active layer.
To reach above-mentioned purpose, embodiment of the present utility model is adopted the following technical scheme that：
The one side of the utility model embodiment is there is provided a kind of thin film transistor (TFT), including bottom-gate, and is set in turn in
Bottom gate insulating barrier, semiconductor active layer, the first insulating barrier in the bottom-gate；The thin film transistor (TFT) also includes being arranged at institute
State source electrode and drain electrode of first insulating barrier away from the bottom-gate side；First insulating barrier is in the correspondence source electrode and described
The position of drain electrode is respectively arranged with via；It is provided with the semiconductor active layer in the position of the above-mentioned via of correspondence described in covering
The ohmic contact layer of semiconductor active layer；The source electrode, the drain electrode pass through different vias and the ohmic contact layer respectively
It is in contact.
It is preferred that, in addition to positioned at first insulating barrier deviate from the bottom-gate side top-gated pole；Described first is exhausted
Edge layer is top-gated insulating barrier.
It is preferred that, the top-gated pole is with the source electrode, drain electrode with the same material of layer.
It is preferred that, the bottom-gate is extremely non-electric-connecting with the top-gated.
It is preferred that, constituting the material of the semiconductor active layer includes amorphous silicon hydride；Constitute the ohmic contact layer
Material includes n-type heavy doping amorphous silicon hydride.
The another aspect of the utility model embodiment includes any one film as described above there is provided a kind of array base palte
Transistor.
It is preferred that, including multiple sub-pixs arranged in matrix form；It is provided with each sub-pix described at least one
Thin film transistor (TFT)；When the thin film transistor (TFT) includes bottom-gate and top-gated pole, the top-gated pole of same thin film transistor (TFT) and bottom
Grid connects different signal wires.
The another aspect of the utility model embodiment is there is provided a kind of display device, including any one battle array as described above
Row substrate.
The utility model embodiment provides a kind of thin film transistor (TFT), array base palte, display device.The thin film transistor (TFT) includes
Bottom-gate, and bottom gate insulating barrier, semiconductor active layer, the first insulating barrier being set in turn in the bottom-gate.It is above-mentioned thin
Film transistor also includes being arranged at source electrode and drain electrode of first insulating barrier away from bottom-gate side.First insulating barrier is in correspondence source electrode
Via is respectively arranged with the position of drain electrode.The position of the above-mentioned via of correspondence is provided with covering semiconductor on semiconductor active layer
The ohmic contact layer of active layer.Source electrode, drain electrode are in contact by different vias with ohmic contact layer respectively.From the foregoing,
First insulating barrier is located above semiconductor active layer, and via on first insulating barrier position respectively with the thin film transistor (TFT)
Source electrode with drain electrode position it is corresponding.Therefore semiconductor active layer upper surface except the position corresponding with above-mentioned via with
Outside, remainder is covered by the first insulating barrier.So, it is ensured that the semiconductor at the thin film transistor channel position
Active layer upper surface is covered by the first insulating barrier.Based on this, covering semiconductor active layer is formed at the position of above-mentioned via
During ohmic contact layer, when being patterned to ohmic contact layer, due to the channel location of correspondence thin film transistor (TFT)
Semiconductor active layer is covered by the first insulating barrier, therefore the upper surface will not be influenceed and become by ohmic contact layer etching technics
Obtain coarse, so as to reduce the probability that defect is produced in semiconductor active layer.So the film crystal that the utility model is provided
In the structure of pipe, the smooth defect in upper surface of the semiconductor active layer at thin film transistor channel position is few, is favorably improved thin
The mobility of film transistor.
Brief description of the drawings
, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art
Or the accompanying drawing used required in description of the prior art is briefly described, it should be apparent that, drawings in the following description are only
It is some embodiments of the present utility model, for those of ordinary skill in the art, is not paying the premise of creative work
Under, other accompanying drawings can also be obtained according to these accompanying drawings.
A kind of structural representation for TFT that Fig. 1 provides for the utility model embodiment；
The structural representation for another TFT that Fig. 2 provides for the utility model embodiment；
A kind of structural representation for bigrid TFT that Fig. 3 provides for the utility model embodiment；
The structural representation for the array base palte with TFT as shown in Figure 3 that Fig. 4 provides for the utility model embodiment；
A kind of preparation method flow chart for TFT that Fig. 5 provides for the utility model embodiment；
Each process schematic for making TFT as shown in Figure 2 that Fig. 6-Figure 12 provides for the utility model embodiment；
Figure 13 has the structural representation of TFT as shown in Figure 3 array base palte for the making that the utility model embodiment is provided
Figure.
Reference：
01- underlay substrates；100- sub-pixs；101- pixel electrodes；10- semiconductor active layers；11- ohmic contact layers；20-
Source electrode；21- drains；30- bottom-gates；31- top-gateds pole；41- bottom gate insulating barriers；The insulating barriers of 42- first；43- passivation layers；110-n
Type heavy doping hydrogenated amorphous silicon layer；111- photoresists；112- mask plates；A-TFT raceway groove；Via on the insulating barriers of B- first.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belongs to the scope of the utility model protection.
The utility model embodiment provides a kind of thin film transistor (TFT) (hereinafter referred to as TFT), as shown in Fig. 2 including bottom-gate
30 (Bottom Gate, BG), and bottom gate insulating barrier 41, the semiconductor active layer 10, first being set in turn in bottom-gate 30
Insulating barrier 42.
It should be noted that the material for constituting above-mentioned bottom gate insulating barrier 41 can be silicon nitride or silica.Or it is above-mentioned
Bottom gate insulating barrier 41 can also be made up of at least two film layers.By taking two film layers as an example, what is be in contact with bottom-gate 30 is thin
Film layer is silicon nitride layer or silicon oxynitride layer.The film layer can be avoided in impurity or bottom-gate 30 in underlay substrate 01
Metal ion diffuses to semiconductor active layer 10, and can prevent bottom-gate 30 from aoxidizing.In addition, connecting with semiconductor active layer 10
Tactile film layer is silicon oxide layer or silicon oxynitride layer.The film layer can improve the adaptation of semiconductor active layer 10.Or
Person, when above-mentioned bottom gate insulating barrier 41 is made up of three-layer thin-film layer, the film layer being in contact with bottom-gate 30 is silicon nitride layer, with
The film layer that semiconductor active layer 10 is in contact is silicon oxide layer, is silicon oxynitride layer between silicon nitride layer and silicon oxide layer.When
So, it is above-mentioned be only to bottom gate insulating barrier 41 by multi-layer thin film layer constitute progress for example, other examples are not another herein
One repeats.
In addition, TFT also includes being arranged at the first insulating barrier 42 away from the source electrode 20 (Source) of bottom-gate side and drain electrode
21(Drain).First insulating barrier 21 is respectively arranged with via B in the position of correspondence source electrode 20 and drain electrode 21.
Ohm that correspondence via B position is provided with covering semiconductor active layer 10 on above-mentioned semiconductor active layer 10 connects
Contact layer 11.Source electrode 20, drain electrode 21 are in contact by different via B with ohmic contact layer 11 respectively.In the case, ohm connects
Contact layer 11 21 can electrically connect source electrode 20, drain electrode with semiconductor active layer 10 respectively, and can be with by the ohmic contact layer 11
Reduce contact resistance of the source electrode 20 (or drain electrode 21) between semiconductor active layer 10.
Based on this, the material for constituting above-mentioned semiconductor active layer 10 can be non-crystalline silicon (a-Si) or amorphous silicon hydride
(a-Si：H).The material for constituting ohmic contact layer 11 can be that n-type heavily doped amorphous silicon (n+a-Si) or n-type heavy doping are hydrogenated
Non-crystalline silicon (n+a-Si：H).Wherein, ohmic contact layer 11 can be by non-crystalline silicon (a-Si) or amorphous silicon hydride (a-Si：
H) material layer progress n-type particle heavy doping technique is formed.It is wherein preferred, at least using amorphous silicon hydride (a-Si：H) in composition
Semiconductor active layer 10 is stated, or at least uses n-type heavy doping amorphous silicon hydride (n+a-Si：H above-mentioned ohmic contact layer) is constituted
11.So, by introducing hydrogen atom in semiconductor active layer 10 and/or ohmic contact layer 11, it is possible to reduce in film
The quantity of hanging key defect, reduces the capture probability of carrier, so as to reach the purpose for improving carrier mobility.For convenience
Illustrate, the material that above-mentioned semiconductor active layer 10 is constituted below is amorphous silicon hydride (a-Si：H), ohmic contact layer 11 is constituted
Material is n-type heavy doping amorphous silicon hydride (n+a-Si：H).
In summary, as shown in Fig. 2 the first insulating barrier 42 is located at the top of semiconductor active layer 10, and first insulating barrier
The position of via B on 42 is corresponding with the source electrode 20 of the TFT and the position of drain electrode 21 respectively.Therefore semiconductor active layer 10
Upper surface is in addition to the position corresponding with above-mentioned via B, and remainder is covered by the first insulating barrier 42.So,
It can ensure that the upper surface of semiconductor active layer 10 at the TFT channel position is covered by the first insulating barrier 42.Based on this, above-mentioned
During the ohmic contact layer 11 that covering semiconductor active layer 10 is formed at via B position, enter when to ohmic contact layer 11
During row patterning, because the semiconductor active layer 10 of correspondence TFT channel location is covered by the first insulating barrier 42, therefore the upper table
Face will not be influenceed by the etching technics of ohmic contact layer 11 and become coarse, lack so as to reduce in semiconductor active layer 10
Fall into the probability produced.So in the structure for the TFT that the utility model is provided, semiconductor active layer 10 at TFT channel position
The smooth defect in upper surface is few, is favorably improved TFT mobility.
On this basis, in order to further enhance TFT performance, it is preferred that as shown in figure 3, the TFT also includes being located at the
One insulating barrier 42 deviates from the top-gated pole 31 (Top Gate, TG) of the side of bottom-gate 30.First insulating barrier 42 is top-gated insulating barrier.
It should be noted that when the upper surface of first insulating barrier 42 sets bottom-gate 31, first insulating barrier 42 is
Top-gated insulating barrier refers to that first insulating barrier 42 needs to have gate insulator (Gate Insulator, GI) function, its matter
Ground is more fine and close for general insulating barrier.Wherein, the top-gated insulating barrier and above-mentioned bottom-gate insulating barrier 41 are set
Put mode identical, here is omitted.
In addition, those skilled in the art are typically directed to research in semiconductor active layer by amorphous indium gallium zinc oxide at present
Double-gate structure is used in the TFT that (a-Indium Gallium Zinc Oxide, a-IGZO) is constituted, because can so obtain
Significant achievement, such as on the problem of solving peroxide threshold voltage drift (Oxide Vth Shift).But in display skill
Art field non-crystalline silicon (a-Si) is still the main material for constituting semiconductor active layer.But those skilled in the art but seldom exist
Double-gate structure is used in the TFT (hereinafter referred to as a-Si TFT) that semiconductor active layer is made up of non-crystalline silicon (a-Si).Therefore have big
When amount correlative study shows that double-gate structure is applied to a-Si TFT, lifting slightly can only be brought to the performance of the TFT.
However, the application has found that the a-Si TFT of double-gate structure performance is unable to reach what is effectively lifted by further investigation
Reason is, as shown in figure 1, short-circuit, it is necessary to right in order to avoid occurring between source electrode 20 and drain electrode 21 during making TFT
The ohmic contact layer 11 on the surface of semiconductor active layer 10 carries out over etching, to ensure the Ohmic contact of source electrode 20 and the lower section of drain electrode 21
Layer 11 is fully disconnected.However, above-mentioned over etching process can be impacted to the upper surface topography of semiconductor active layer 10, cause
The upper surface of semiconductor active layer 10 at TFT channel location A is coarse, there is more defect.So, when TFT is in conducting
When, the carrier produced in raceway groove is easily captured in transmitting procedure by drawbacks described above, so that carrier mobility is reduced, it is right
TFT performance is impacted.
Based on this, on the one hand, because the upper surface of semiconductor active layer 10 in the application at the TFT channel location A is by
One insulating barrier 42 is covered, so ohmic contact layer 11 is not deposited directly at the back of the body raceway groove of the TFT, therefore ohmic contact layer 11
Etching technics the flatness of the upper surface of semiconductor active layer 10 at TFT channel location A will not also be impacted so that should
TFT back of the body raceway groove has higher conduction property.On the other hand, TFT is double-gate structure, therefore can improve TFT semiconductors and have
Carrier quantity in active layer 10, and make it that Carrier Profile is more uniform.In addition, the semiconductor at the TFT channel position has
Active layer 10 is smooth on the surface on the surface close to bottom-gate 30 and close top-gated pole 31, and defect is few.So the TFT's partly leads
Body active layer 10 has stronger electric conductivity, so as to reach the purpose for significantly lifting two grid a-Si TFT performances.
In summary, the application breaches the traditional design mindset of this area, by improving TFT structure and manufacture craft,
And bigrid is introduced in the TFT structure after improving so that two grid a-Si TFT equally have preferable performance.So as to
Improve the two grid a-Si TFT scope of application.
On this basis, in the application, above-mentioned top-gated pole 31 can be electrically connected with bottom-gate 30, such as by making via
Bottom-gate 30 is electrically connected with top-gated pole 31.Or, above-mentioned bottom-gate 30 and top-gated pole 31 are electrically connected by same signal wire
Connect.In addition, above-mentioned top-gated pole 31 can also be disconnected with bottom-gate 30.The utility model is to top-gated pole 31 and the company of bottom-gate 30
Mode is connect not limit.However, because the factors such as different manufacture crafts, production line or production material can cause diverse location
TFT mobility there is difference.Therefore the application is preferred, and above-mentioned bottom-gate 30 and top-gated pole 31 are non-electric-connecting.Such one
Come, those skilled in the art can be as needed, the voltage applied to bottom-gate 30 and top-gated pole 31 is carried out respectively independent
Control and debugging, so that the two grid a-Si TFT performances reach most preferably.
In addition, the material for constituting top-gated pole 31 can be identical with constituting the material of bottom-gate 30, for example, crome metal (Cr),
Evanohm, molybdenum tantalum (Mo Ta) alloy, metallic aluminium (Al) or aluminium alloy etc..Or the material of this composition top-gated pole 31 can be with
It is identical with the material for constituting source electrode 20 and drain electrode 21, for example, crome metal (Cr), metallic aluminium (Al) or aluminium alloy.Wherein, it is
Simplified manufacture craft, above-mentioned top-gated pole 31 so, can pass through one with source electrode 20 and drain electrode 21 with the same material of layer
Secondary patterning processes prepare above-mentioned top-gated pole 31, source electrode 20 and drain electrode 21.
It should be noted that the patterning processes in the utility model, can refer to including photoetching process (MASK), or, including
Photoetching process and etch step, while including printing, ink-jet etc. other technique for forming predetermined pattern can also to be used for.Its
In, photoetching process refers to include the formation such as utilization photoresist, mask plate, exposure machine of the technical process such as film forming, exposure, development
The technique of figure.Corresponding patterning processes of structure choice that can be according to formed in the utility model.In addition, the utility model is real
Apply a patterning processes in example, be to form different exposure areas by mask, exposure, a developing process, it is then right
Different exposure areas carries out the removal technique such as multiple etching, ashing and finally gives the explanation carried out exemplified by expected pattern.
The utility model embodiment, which provides a kind of array base palte, includes any one TFT as described above.With with it is foregoing
The beneficial effect for the TFT that embodiment is provided, here is omitted.
Wherein, above-mentioned array base palte is as shown in figure 4, including multiple sub-pixs 100 arranged in matrix form.Each Asia picture
The grid line Gate and data wire Data that element is intersected by transverse and longitudinal, which intersect, to be defined.
Based on this it should be noted that the application is not limited to the scope of application of above-mentioned array base palte.For example, above-mentioned battle array
Row substrate can apply to LCD, and now each sub-pix 100 is usually provided with a TFT as shown in Figure 4, the grid of the TFT with
Grid line Gate is connected, and source electrode is connected with data wire Data, and drains and be connected with pixel electrode 101.Or, above-mentioned array
Substrate can also be applied to OLED display.Now, be provided with each sub-pix for drive luminescent device (LED or
OLED pixel-driving circuit).The drive circuit includes multiple TFT.
In the case, when TFT includes bottom-gate 30 and top-gated pole 31 as shown in Figure 3, same TFT top-gated pole 31
Different signal wires are connected with bottom-gate 30.Specifically, for example, being provided with one and the grid near every grid line Gate in Fig. 4
Additional signal lines S parallel line Gate.Now, same TFT top-gated pole 31 and bottom-gate 30 can respectively with grid line Gate
With the connection of additional signal lines S-phase.So, by grid line Gate and additional signal lines S, respectively to apply to bottom-gate 30 with
And top-gated pole 31 voltage carry out individually control and debug so that the two grid a-Si TFT performances reach most preferably, from
And bottom-gate 30 can be overcome to be electrically connected with top-gated pole 31, and the mobility difference that can not solve the TFT of diverse location causes TFT
Performance the problem of there is difference.
The utility model embodiment provides a kind of display device, including any one array base palte as described above.Have
The array base palte identical beneficial effect provided with previous embodiment, here is omitted.
The utility model embodiment provides a kind of TFT preparation method, as shown in figure 5, including：
S101, as shown in fig. 6, on underlay substrate 01, bottom-gate 30, bottom gate insulating barrier are sequentially formed by patterning processes
41 and semiconductor active layer 10.
Wherein, the material for constituting above-mentioned semiconductor active layer 10 can be non-crystalline silicon (a-Si) or preferably hydrogenated amorphous
Silicon (a-Si：H).
S102, as shown in fig. 7, being formed with the underlay substrate 01 of semiconductor active layer 10, formed by patterning processes
First insulating barrier 42, and the position in corresponding source electrode area to be formed and the area to be formed that drains was formed respectively on the first insulating barrier 42
Hole B.
Specifically, above-mentioned via can be by carrying out one of photoetching process to the first insulating barrier 42 so that exhausted with first
The region of source electrode 20 to be produced and the region of drain electrode to be produced 21 are not covered by photoresist on the underlay substrate 01 of edge layer 42.Connect down
Come, the first insulating barrier 42 of photoresist uncovered area is performed etching by dry etching, so as to form above-mentioned via B.
S103, it is being formed with the underlay substrate 01 of the first insulating barrier 42, by patterning processes in above-mentioned via B location
Place, forms the ohmic contact layer 11 of covering semiconductor active layer 10 as shown in Figure 2.
Wherein, the material for constituting ohmic contact layer 11 can be n-type heavily doped amorphous silicon (n+a-Si), or preferably n
Type heavy doping amorphous silicon hydride (n+a-Si：H).
So that the material for constituting ohmic contact layer 11 is n-type heavy doping amorphous silicon hydride as an example, to above-mentioned ohmic contact layer 11
Manufacturing process be described in detail.
Specifically, first as shown in figure 8, being formed with one layer of n-type weight of deposition on the underlay substrate 01 of the first insulating barrier 42
Doped hydrogenated amorphous silicon layer 110.
Next, covering one layer of photoresist 111 in above-mentioned n-type heavy doping hydrogenated amorphous silicon layer 110.Then mask plate is passed through
112 pairs of photoresists 111 carry out mask exposure.
Wherein, above-mentioned photoresist 111 can be positive photoresist, or negtive photoresist.The application is by taking positive photoresist as an example.Now such as Fig. 9
Shown, the transparent area of mask plate 112 is in requisition for needing developed position on photoresist 111.Based on this, by one of photoetching
After technique, the n-type heavy doping hydrogenated amorphous silicon layer 110 at via B location as shown in Figure 10 is covered by photoresist.
Next, as shown in figure 11, being carried out to the n-type heavy doping hydrogenated amorphous silicon layer 110 of the uncovered area of photoresist 111
Etching.Then photoresist 11 is peeled off, forms ohmic contact layer 11 as shown in Figure 2.
S104, as shown in Fig. 2 being formed with the underlay substrate 01 of ohmic contact layer 11, form position by patterning processes
In the first insulating barrier 42 away from the source electrode 20 of the side of bottom-gate 30 and drain electrode 21.
Wherein, source electrode 20, drain electrode 21 are in contact by different via B with ohmic contact layer 11 respectively.
Above-mentioned TFT preparation method has the TFT identical beneficial effects provided with previous embodiment, no longer goes to live in the household of one's in-laws on getting married herein
State.
On this basis, in order to further enhance TFT performance, it is preferred that above-mentioned TFT preparation method also includes, such as
Shown in Fig. 3, it is being formed with the underlay substrate 01 of source electrode 20 and drain electrode 21, is passing through patterning processes formation top-gated pole 31.
So, on the one hand, due to the upper surface quilt of semiconductor active layer 10 in the application at the TFT channel location A
First insulating barrier 42 is covered, so ohmic contact layer 11 is not deposited directly at the back of the body raceway groove of the TFT, therefore ohmic contact layer
11 etching technics will not also be impacted to the flatness of the upper surface of semiconductor active layer 10 at TFT channel location A so that should
TFT back of the body raceway groove has higher conduction property.On the other hand, TFT is double-gate structure, therefore can improve TFT semiconductors and have
Carrier quantity in active layer 10, and make it that Carrier Profile is more uniform.In addition, the semiconductor at the TFT channel position has
Active layer 10 is smooth on the surface on the surface close to bottom-gate 30 and close top-gated pole 31, and defect is few.So the TFT's partly leads
Body active layer 10 has stronger electric conductivity, so as to reach the purpose for significantly lifting two grid a-Si TFT performances.
In summary, the application has broken the traditional design thinking of this area, by improving TFT structure and making work
Skill, and bigrid is introduced in the TFT structure after improving so that two grid a-Si TFT equally have preferable performance.
So as to improve the two grid a-Si TFT scope of application.
On this basis, in order to simplify manufacture craft, above-mentioned top-gated pole 31 be able to can pass through with source electrode 20 and drain electrode 21
One time patterning processes are formed.
Based on this, when array base palte includes above-mentioned TFT, the preparation method of the array base palte also includes above-mentioned TFT system
Make method.It is formed with addition, the preparation method of array base palte is additionally included on the underlay substrate 01 of source electrode 20 and drain electrode 21 successively
Form passivation layer 43 (Passivation, PVX) and pixel electrode (not shown in Figure 13).The pixel electrode passes through passivation layer
43 upper via is electrically connected with drain electrode 21.
Wherein, the material of above-mentioned passivation layer 43 is constituted with constituting the material of bottom gate insulating barrier 41 and the first insulating barrier 42 substantially
It is identical, it can for example include silicon nitride or silica.Specific passivation layer 43 and bottom gate insulating barrier 41 can by etc. from
It is prepared by sub- chemical vapor deposition (Plasma Chemical Vapor Deposition, PCVD) technique.Simply bottom gate is exhausted
The consistency of edge layer 41 is typically larger than the consistency of passivation layer 43.Therefore the parameter by adjusting PCVD techniques is needed, to be formed
Film with different consistency.
It is described above, embodiment only of the present utility model, but protection domain of the present utility model do not limit to
In this, any one skilled in the art can readily occur in change in the technical scope that the utility model is disclosed
Or replace, it should all cover within protection domain of the present utility model.Therefore, protection domain of the present utility model should be with the power
The protection domain that profit is required is defined.
Claims (8)
1. a kind of thin film transistor (TFT), it is characterised in that including bottom-gate, and the bottom gate being set in turn in the bottom-gate are exhausted
Edge layer, semiconductor active layer, the first insulating barrier；
The thin film transistor (TFT) also includes being arranged at source electrode and drain electrode of first insulating barrier away from the bottom-gate side；Institute
State the first insulating barrier and be respectively arranged with via in the position of the correspondence source electrode and the drain electrode；
It is provided with the semiconductor active layer in the position of the above-mentioned via of correspondence and covers ohm of the semiconductor active layer and connect
Contact layer；The source electrode, the drain electrode are in contact by different vias with the ohmic contact layer respectively.
2. thin film transistor (TFT) according to claim 1, it is characterised in that also including deviating from institute positioned at first insulating barrier
State the top-gated pole of bottom-gate side；First insulating barrier is top-gated insulating barrier.
3. thin film transistor (TFT) according to claim 2, it is characterised in that the top-gated pole and the source electrode, the same layer of drain electrode
Same material.
4. thin film transistor (TFT) according to claim 2, it is characterised in that the bottom-gate with the top-gated is extremely non-is electrically connected
Connect.
5. thin film transistor (TFT) according to claim 1, it is characterised in that constituting the material of the semiconductor active layer includes
Amorphous silicon hydride；Constituting the material of the ohmic contact layer includes n-type heavy doping amorphous silicon hydride.
6. a kind of array base palte, it is characterised in that including the thin film transistor (TFT) as described in claim any one of 1-5.
7. array base palte according to claim 6, it is characterised in that including multiple sub-pixs arranged in matrix form；
At least one described thin film transistor (TFT) is provided with each sub-pix；
When the thin film transistor (TFT) includes bottom-gate and top-gated pole, the top-gated pole of same thin film transistor (TFT) and bottom-gate connection
Different signal wires.
8. a kind of display device, it is characterised in that including array base palte as claimed in claims 6 or 7.
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| CN201720324359.3U CN206584934U (en) | 2017-03-29 | 2017-03-29 | A kind of thin film transistor (TFT), array base palte, display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720324359.3U CN206584934U (en) | 2017-03-29 | 2017-03-29 | A kind of thin film transistor (TFT), array base palte, display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108873520A (en) * | 2018-06-28 | 2018-11-23 | 武汉华星光电技术有限公司 | A kind of liquid crystal display panel |
| US11335709B2 (en) | 2020-03-30 | 2022-05-17 | Xiamen Tianma Micro-Electronics Co., Ltd. | Array substrate, display panel, display device and method for forming array substrate |
| WO2023108811A1 (en) * | 2021-12-17 | 2023-06-22 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and manufacturing method of array substrate |
-
2017
- 2017-03-29 CN CN201720324359.3U patent/CN206584934U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108873520A (en) * | 2018-06-28 | 2018-11-23 | 武汉华星光电技术有限公司 | A kind of liquid crystal display panel |
| CN108873520B (en) * | 2018-06-28 | 2021-07-13 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
| US11335709B2 (en) | 2020-03-30 | 2022-05-17 | Xiamen Tianma Micro-Electronics Co., Ltd. | Array substrate, display panel, display device and method for forming array substrate |
| WO2023108811A1 (en) * | 2021-12-17 | 2023-06-22 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and manufacturing method of array substrate |
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