CN104465663A - Structure and manufacturing method of SONOS flash memory - Google Patents
Structure and manufacturing method of SONOS flash memory Download PDFInfo
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- CN104465663A CN104465663A CN201410853040.0A CN201410853040A CN104465663A CN 104465663 A CN104465663 A CN 104465663A CN 201410853040 A CN201410853040 A CN 201410853040A CN 104465663 A CN104465663 A CN 104465663A
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- polysilicon gate
- polysilicon
- oxide
- thickness
- silica
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- 230000015654 memory Effects 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 claims abstract description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000003860 storage Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a manufacturing method of an SONOS flash memory. The manufacturing method comprises the steps that firstly, gate oxide grows on a substrate; secondly, polycrystalline silicon and silicon oxide deposit, a selectron polysilicon gate is formed in a photoetching mode, and a polysilicon gate in a logic area is reserved; thirdly, an ONO layer deposits; fourthly, polycrystalline silicon deposits, memotron polysilicon gates are formed in a dry etching mode, are arranged on the two sides of the selectron polysilicon gate in a mirror image mode and are isolated from the selectron polysilicon gate and the substrate through the ONO layer; fifthly, the polysilicon gate in the logic area is etched. The invention further discloses an SONOS flash memory structure manufactured through the method. Two memotrons are arranged on the two sides of a selectron in a mirror image mode and isolated from the seletron through the ONO layer. By means of the mirror image position structure, the area of an SONOS storage array is greatly reduced. If the design rule of a 0.13 micron node is used, the area of each storage unit can be about 0.1 square micron.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to structure and the manufacture method of SONOS (the English acronym of polysilicon-oxide-nitride-oxide-polysilicon, also known as nonvolatile memory) flash memories.
Background technology
As shown in Figure 1, ONO (oxide-nitride-oxide) layer and polysilicon gate composition storage tube, middle pressure oxide layer and polysilicon gate composition select pipe to the structure of existing SONOS flash memories.The shortcoming of the memory cell of this structure is that structure is compact not, and area is larger.
Summary of the invention
One of the technical problem to be solved in the present invention is to provide a kind of manufacture method of SONOS flash memories, and it can reduce the area of memory cell.
For solving the problems of the technologies described above, the manufacture method of SONOS flash memories of the present invention, the forming step of its memory physical structure comprises:
1) at Grown grid oxygen;
2) depositing polysilicon and silica, and chemical wet etching forms selection pipe polysilicon gate, logic region polysilicon gate retains;
3) silicon oxide deposition-silicon nitride-silicon oxide silicon layer;
4) depositing polysilicon, and dry etching forms storage tube polysilicon gate; Described storage tube polysilicon gate is that mirror image is arranged on selection pipe polysilicon gate both sides, and by oxide-nitride-oxide layer and selection pipe polysilicon gate and substrate isolation;
5) logic region polysilicon gate etching.
Step 1) thickness of described grid oxygen is
Step 2) thickness of described polysilicon is
the thickness of described silica is
Step 3) thickness of described oxide-nitride-oxide layer is followed successively by from top to bottom: silica
silicon nitride
silica
Step 4) thickness of described polysilicon is
Two of the technical problem to be solved in the present invention is to provide the structure of the SONOS flash memories manufactured with said method, and its 2 storage tubes are that mirror image is arranged on selection pipe both sides, and are isolated with selecting pipe by oxide-nitride-oxide rete.
The present invention, by adopting Mirror bit (mirror-bit) structure, greatly reduces the area of SONOS flash memories storage array.If with the design rule of 0.13 μm of node, about the area of every memory cell can accomplish 0.1 square micron.
Accompanying drawing explanation
Fig. 1 is the structure chart of the SONOS flash memories of traditional 2 pipe units.
Fig. 2 is the structure chart of SONOS flash memories of the present invention.
Fig. 3 ~ Fig. 9 is the manufacturing process flow schematic diagram of SONOS flash memories of the present invention.
In figure, description of reference numerals is as follows:
1: substrate
2: grid oxygen
3,6: polysilicon
4: silica
5:ONO (oxide-nitride-oxide) layer
Embodiment
Understand more specifically for having technology contents of the present invention, feature and effect, now by reference to the accompanying drawings, details are as follows:
The SONOS flash memories of the present embodiment, the main forming step of its physical structure (see Fig. 2) comprising:
Step 1, grows grid oxygen 2, as shown in Figure 3 on substrate 1.
The growing method of grid oxygen 2 can adopt the method for the routine growth oxide layers such as the oxidation of hot oxygen or chemical vapor deposition.The thickness of grid oxygen 2 is about
Step 2, depositing polysilicon 3 and silica 4, as shown in Figure 4.
Polysilicon 3 generally adopts the methods such as chemical vapor deposition to be formed.The thickness of polysilicon 3 is about
The growing method of silica 4 can adopt the method for the routine growth oxide layers such as the oxidation of hot oxygen or chemical vapor deposition.The thickness of silica 4 is about
Step 3, chemical wet etching polysilicon 3 and silica 4, formed and select pipe polysilicon gate, and logic region polysilicon gate retains, as shown in Figure 5.
Step 4, deposit ONO layer 5, as shown in Figure 6.
The deposit of ONO layer 5 can adopt oxidation or chemical gas-phase deposition method, and thickness is followed successively by from top to bottom: silica
silicon nitride
silica
Step 5, depositing polysilicon 6, as shown in Figure 7.Polysilicon 6 can adopt the methods such as chemical vapor deposition to be formed, and thickness is about
Step 6, dry etching polysilicon 6 and ONO layer 5, form storage tube polysilicon gate, as shown in Figure 8.This step dry etching can a step etch polysilicon 6 and ONO layer 5, also can first etch polysilicon 6, then etches ONO layer 5.
Step 7, logic region polysilicon gate etching, as shown in Figure 9.
Above processing step is mainly used to the physical structure forming SONOS flash memories, if form the electrology characteristic of whole memory device, at processing step 1) and processing step 3) threshold voltage that ion implantation step adjusts selection pipe and storage tube respectively can be added above as required, processing step 5) ion implantation step can be added afterwards to do the source and drain injection of whole memory.
Claims (7)
- The manufacture method of 1.SONOS flash memories, is characterized in that, the forming step of the physical structure of this SONOS flash memories comprises:1) at Grown grid oxygen;2) depositing polysilicon and silica, and chemical wet etching forms selection pipe polysilicon gate, logic region polysilicon gate retains;3) silicon oxide deposition-silicon nitride-silicon oxide silicon layer;4) depositing polysilicon, and dry etching forms storage tube polysilicon gate; Described storage tube polysilicon gate is that mirror image is arranged on selection pipe polysilicon gate both sides, and by oxide-nitride-oxide layer and selection pipe polysilicon gate and substrate isolation;5) logic region polysilicon gate etching.
- 2. method according to claim 1, is characterized in that, step 1) thickness of described grid oxygen is
- 3. method according to claim 1, is characterized in that, step 2) thickness of described polysilicon is
- 4. method according to claim 1, is characterized in that, step 2) thickness of described silica is
- 5. method according to claim 1, is characterized in that, step 3) thickness of described oxide-nitride-oxide layer is followed successively by from top to bottom: silica silicon nitride silica
- 6. method according to claim 1, is characterized in that, step 4) thickness of described polysilicon is
- 7. by the structure of the SONOS flash memories of method manufacture described in any one of claim 1 to 6, it is characterized in that, 2 storage tubes are that mirror image is arranged on and selects pipe both sides, storage tube and select between pipe and isolated by oxide-nitride-oxide rete between storage tube and substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410853040.0A CN104465663A (en) | 2014-12-31 | 2014-12-31 | Structure and manufacturing method of SONOS flash memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410853040.0A CN104465663A (en) | 2014-12-31 | 2014-12-31 | Structure and manufacturing method of SONOS flash memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104465663A true CN104465663A (en) | 2015-03-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410853040.0A Pending CN104465663A (en) | 2014-12-31 | 2014-12-31 | Structure and manufacturing method of SONOS flash memory |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118833A (en) * | 2015-07-30 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | Structure and manufacturing method of 3D tunneling floating gate memory |
| CN110504273A (en) * | 2019-08-13 | 2019-11-26 | 上海华虹宏力半导体制造有限公司 | 1.5T SONOS flush memory device and process |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW513789B (en) * | 2001-12-28 | 2002-12-11 | Vanguard Int Semiconduct Corp | Manufacturing method of flash memory with floating gate, control gate and erase gate |
| US20050202631A1 (en) * | 2003-10-15 | 2005-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Poly-etching method for split gate flash memory cell |
| CN101442076A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Device structure of SONOS memory tube and method for producing the same |
| CN103855163A (en) * | 2012-12-05 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Two-bit SONOS flash memory and manufacturing method thereof |
-
2014
- 2014-12-31 CN CN201410853040.0A patent/CN104465663A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW513789B (en) * | 2001-12-28 | 2002-12-11 | Vanguard Int Semiconduct Corp | Manufacturing method of flash memory with floating gate, control gate and erase gate |
| US20050202631A1 (en) * | 2003-10-15 | 2005-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Poly-etching method for split gate flash memory cell |
| CN101442076A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Device structure of SONOS memory tube and method for producing the same |
| CN103855163A (en) * | 2012-12-05 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Two-bit SONOS flash memory and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118833A (en) * | 2015-07-30 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | Structure and manufacturing method of 3D tunneling floating gate memory |
| CN105118833B (en) * | 2015-07-30 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | The structure and manufacture method of 3D tunneling floating-gate memories |
| CN110504273A (en) * | 2019-08-13 | 2019-11-26 | 上海华虹宏力半导体制造有限公司 | 1.5T SONOS flush memory device and process |
| CN110504273B (en) * | 2019-08-13 | 2022-03-08 | 上海华虹宏力半导体制造有限公司 | 1.5T SONOS flash memory device and process method |
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Application publication date: 20150325 |