CN105470261A - Sonos memory and manufacturing method thereof - Google Patents
Sonos memory and manufacturing method thereof Download PDFInfo
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- CN105470261A CN105470261A CN201510992684.2A CN201510992684A CN105470261A CN 105470261 A CN105470261 A CN 105470261A CN 201510992684 A CN201510992684 A CN 201510992684A CN 105470261 A CN105470261 A CN 105470261A
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- storage tube
- pipe
- polysilicon
- layer
- silicon nitride
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The present invention discloses a SONOS memory. The memory is of a structure that a storage tube and a selection tube are formed on a silicon substrate separately, and the storage tube and the selection tube are separated by inter-polysilicon silicon nitride; side walls are formed at side ends of the storage tube and the selection tube separately; inter-layer oxide layers are formed on the upper ends of the storage tube and the selection tube, and contact holes are respectively formed at side ends of the side walls; the storage tube uses an ONO layer structure; a storage tube polysilicon gate is formed on the upper end of the ONO layer structure, and a storage tube gate upper silicon nitride layer is formed on the upper end of the storage tube polysilicon gate; the selection tube comprises a selection tube gate oxide layer formed on the silicon substrate, and a selection tube polysilicon gate located on the upper end of the selection tube gate oxide layer; and a lightly doped drain region is formed on the lower end of the side wall at one side of the selection tube and in the silicon substrate, and source/drain implantation regions are formed in the silicon substrate at the lower ends of the contact holes. The present invention also discloses a manufacturing method of the SONOS memory. According to the SONOS memory and the manufacturing method thereof, the area of a memory array can be greatly reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of SONOS (flash memories) memory.The invention still further relates to a kind of manufacture method of SONOS memory.
Background technology
As shown in Figure 1, it comprises the memory construction of existing 2 pipe units: silicon nitride, side wall 8, lightly doped drain 9, source and drain injection region 10, contact hole 11 and interlevel oxide layer 12 on substrate 1, ONO layer 2, storage tube polysilicon gate, selection pipe gate oxide 5, selection pipe polysilicon gate 6, storage tube grid.
The memory construction of existing 2 pipe units according to Fig. 1, can find out at storage tube and select to leave certain distance as isolation between pipe, it exists shortcoming is the area that can increase storage array, is unfavorable for improving integrated level.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of SONOS memory, greatly can reduce the area of storage array; For this reason, the present invention also will provide a kind of manufacture method of described SONOS memory.
For solving the problems of the technologies described above, SONOS memory of the present invention, comprising:
One silicon substrate, this silicon substrate is formed storage tube respectively and selects pipe, described storage tube and selecting between pipe by the inter polysilicon silicon nitride isolation being positioned at storage tube two side ends and being formed; Side wall is formed with respectively at the side of described storage tube and selection pipe; Be formed with interlevel oxide layer in the upper end of described storage tube and selection pipe, be formed with contact hole respectively at the side of described side wall;
Described storage tube adopts ONO (oxide-nitride-oxide oxide layer-nitride layer-oxide layer) Rotating fields; Be formed with storage tube polysilicon gate in the upper end of this ONO Rotating fields, the upper end being positioned at storage tube polysilicon gate is formed with silicon nitride layer on storage tube grid;
Described selection pipe comprises the selection pipe gate oxide formed on a silicon substrate, is positioned at the selection pipe polysilicon gate of this selection pipe gate oxide upper end;
Be positioned at silicon substrate in the side wall lower end of described selection pipe side and be formed with lightly doped drain, the lower end silicon substrate being positioned at contact hole is formed with source and drain injection region.
The manufacture method of described SONOS memory, comprises the steps:
The ONO layer of step 1, on a silicon substrate deposit storage tube;
Step 2, on described ONO layer deposit one deck first polysilicon and one deck silicon nitride successively;
Step 3, etch described ONO layer, the first polysilicon layer and silicon nitride layer, silicon nitride layer on the storage tube grid forming storage tube polysilicon gate and be located thereon end;
Step 4, on described silicon substrate and storage tube grid silicon nitride between depositing polysilicon on silicon nitride layer, etch this inter polysilicon silicon nitride, form the inter polysilicon silicon nitride layer being positioned at silicon nitride layer two side ends on storage tube polysilicon gate and storage tube grid;
Step 5, described silicon substrate grows one deck select pipe gate oxide;
Step 6, at described selection pipe gate oxide upper end deposit one deck second polysilicon layer;
Step 7, carry out first time second polysilicon layer etching, between adjacent two storage tubes, form window, but the second polysilicon layer between adjacent two storage tubes is not exclusively removed;
The described second polysilicon layer etching of step 8, second time of carrying out, is formed and selects pipe polysilicon gate;
Step 9, select to carry out lightly doped drain injection between pipes at adjacent two, form the lightly doped drain being positioned at silicon substrate;
Step 10, remove unnecessary selection pipe gate oxide, at described storage tube with select the side of pipe carry out silicon nitride deposition and etch, form the side wall being positioned at storage tube and selecting pipe side;
Step 11, select to carry out source and drain injection between pipe side walls at adjacent two, form the source and drain injection region being positioned at silicon substrate;
Step 12, at storage tube with select pipe and silicon substrate upper end deposit interlevel oxide layer, and chemico-mechanical polishing is carried out to interlevel oxide layer;
Step 13, etch described interlevel oxide layer, between adjacent two storage tubes and adjacent two select to form contact hole respectively between pipes;
Step 14, in described contact hole, carry out tungsten deposit, fill up contact hole, then carry out the chemico-mechanical polishing of tungsten.
The present invention replaces this distance by one deck nitration case thus realizes buffer action, can reduce the area of storage array so greatly.At the design rule of 0.13 μm of node, the area of every memory cell can accomplish that 0.15 square micron is even less.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the memory construction figure of existing 2 pipe units;
Fig. 2 is described SONOS memory construction figure;
Fig. 3 is the memory of SONOS shown in Fig. 2 generalized section;
Fig. 4-16 is described SONOS memory manufacturing flow charts.
Embodiment
Shown in composition graphs 2, in the following embodiments, described SONOS memory is the flash memories of the three-dimensional floating gate structure of a kind of two novel bits, and it comprises: a silicon substrate 1, this silicon substrate 1 is formed storage tube respectively and selects pipe.
Described storage tube adopts ONO layer 2 structure.This ONO layer 2 from top to bottom, is followed successively by
oxide layer,
nitration case,
oxide layer.The upper end of this ONO layer 2 structure is formed with storage tube polysilicon gate 3, and thickness is
the upper end being positioned at storage tube polysilicon gate 3 is formed with silicon nitride layer 7 on storage tube grid, and its thickness is
described selection pipe is included in the selection pipe gate oxide 5 that silicon substrate 1 is formed, and is positioned at the selection pipe polysilicon gate 6 of this selection pipe gate oxide 5 upper end; Select pipe gate oxide 5 to be middle pressure oxide layer, thickness is
Described storage tube and select to isolate by being positioned at the inter polysilicon silicon nitride 4 that storage tube two side ends formed between pipe; Be formed with silicon nitride spacer 8 respectively at the side of described storage tube and selection pipe, its thickness is
be formed with interlevel oxide layer 12 in the upper end of described storage tube and selection pipe, be formed with contact hole 11 respectively at the side of described side wall 8.Be positioned at silicon substrate 1 in the side wall lower end of described selection pipe side and be formed with lightly doped drain 9, the lower end silicon substrate being positioned at contact hole is formed with source and drain injection region 10.
See Fig. 3, adjacent two memory cell are placed back-to-back, select pipe to share a contact hole 11, two storage tubes for two and share a contact hole 11.
The manufacture method of described SONOS memory, in the following embodiments, comprises the steps:
Shown in step 1, composition graphs 4, the ONO layer 2 of deposit storage tube on silicon substrate 1; This ONO layer 2 deposit is followed successively by from top to bottom:
oxide layer,
nitration case,
oxide layer.
Shown in step 2, composition graphs 5, deposit one ground floor polysilicon 3 (thickness successively on described ONO layer 2
) and one deck silicon nitride 7 (thickness
).
Shown in step 3, composition graphs 6, etch described ONO layer 2, first polysilicon layer 3 and silicon nitride layer 7, silicon nitride layer 7 on the storage tube grid forming storage tube polysilicon gate 3 and be located thereon end.
Shown in step 4, composition graphs 7, silicon nitride between depositing polysilicon on silicon nitride layer 7 on described silicon substrate 1 and storage tube grid, thickness is about
etch this inter polysilicon silicon nitride, form the inter polysilicon silicon nitride layer 4 being positioned at silicon nitride layer two side ends on storage tube polysilicon gate and storage tube grid.
Shown in step 5, composition graphs 8, described silicon substrate 1 grows one deck and selects pipe gate oxide 5, thickness is about
Shown in step 6, composition graphs 9, at described selection pipe gate oxide 5 upper end deposit one deck second polysilicon layer 6, thickness is about
Step 7, in conjunction with shown in Figure 10, carry out first time second polysilicon layer and 6 to etch, between adjacent two storage tubes, form window, but the second polysilicon layer 6 between adjacent two storage tubes is not exclusively removed.
Step 8, in conjunction with shown in Figure 11, carry out the described second polysilicon layer etching of second time, formed and select pipe polysilicon gate 6.
Step 9, in conjunction with shown in Figure 12, select to carry out lightly doped drain injection between pipes at adjacent two, form the lightly doped drain 9 being positioned at silicon substrate 1.
Step 10, in conjunction with shown in Figure 13, remove unnecessary selection pipe gate oxide 5, at described storage tube with select the side of pipe carry out silicon nitride deposition and etch, form the side wall 8 being positioned at storage tube and selecting pipe side.
Step 11, in conjunction with shown in Figure 14, select to carry out source and drain injection between pipe side walls 8 at adjacent two, form the source and drain injection region 10 being positioned at silicon substrate.
Step 12, in conjunction with shown in Figure 15, storage tube and select pipe and silicon substrate upper end deposit interlevel oxide layer 12, thickness is about
and chemico-mechanical polishing is carried out to interlevel oxide layer 12, residual film is about
Step 13, in conjunction with shown in Figure 16, etch described interlevel oxide layer 12, between adjacent two storage tubes and adjacent two select to form contact hole 11 respectively between pipes.
Shown in step 14, composition graphs 3, in described contact hole 11, carry out tungsten deposit, fill up contact hole 11, then carry out the chemico-mechanical polishing of tungsten.
New type of S ONOS memory construction of the present invention, its operation is consistent with 2 traditional pipe unit memories.
Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (9)
1. a SONOS memory, is characterized in that, comprising:
One silicon substrate, this silicon substrate is formed storage tube respectively and selects pipe, described storage tube and selecting between pipe by the inter polysilicon silicon nitride isolation being positioned at storage tube two side ends and being formed; Side wall is formed with respectively at the side of described storage tube and selection pipe; Be formed with interlevel oxide layer in the upper end of described storage tube and selection pipe, be formed with contact hole respectively at the side of described side wall;
Described storage tube adopts ONO Rotating fields; Be formed with storage tube polysilicon gate in the upper end of this ONO Rotating fields, the upper end being positioned at storage tube polysilicon gate is formed with silicon nitride layer on storage tube grid;
Described selection pipe comprises the selection pipe gate oxide formed on a silicon substrate, is positioned at the selection pipe polysilicon gate of this selection pipe gate oxide upper end;
Be positioned at silicon substrate in the side wall lower end of described selection pipe side and be formed with lightly doped drain, the lower end silicon substrate being positioned at contact hole is formed with source and drain injection region.
2. memory as claimed in claim 1, is characterized in that: adjacent two memory cell are placed back-to-back, and select pipe to share a contact hole for adjacent two, adjacent two storage tubes share a contact hole.
3. memory as claimed in claim 1, is characterized in that: described storage tube polysilicon gate thickness is
4. memory as claimed in claim 1, is characterized in that: silicon nitride layer on described storage tube grid, its thickness is
5. memory as claimed in claim 1, is characterized in that: deposition tungsten in described contact hole, fills up this contact hole.
6. a manufacture method for SONOS memory described in claim 1, is characterized in that, comprise the steps:
The ONO layer of step 1, on a silicon substrate deposit storage tube;
Step 2, on described ONO layer deposit one deck first polysilicon and one deck silicon nitride successively;
Step 3, etch described ONO layer, the first polysilicon layer and silicon nitride layer, silicon nitride layer on the storage tube grid forming storage tube polysilicon gate and be located thereon end;
Step 4, on described silicon substrate and storage tube grid silicon nitride between depositing polysilicon on silicon nitride layer, etch this inter polysilicon silicon nitride, form the inter polysilicon silicon nitride layer being positioned at silicon nitride layer two side ends on storage tube polysilicon gate and storage tube grid;
Step 5, described silicon substrate grows one deck select pipe gate oxide;
Step 6, at described selection pipe gate oxide upper end deposit one deck second polysilicon layer;
Step 7, carry out first time second polysilicon layer etching, between adjacent two storage tubes, form window, but the second polysilicon layer between adjacent two storage tubes is not exclusively removed;
The described second polysilicon layer etching of step 8, second time of carrying out, is formed and selects pipe polysilicon gate;
Step 9, select to carry out lightly doped drain injection between pipes at adjacent two, form the lightly doped drain being positioned at silicon substrate;
Step 10, remove unnecessary selection pipe gate oxide, at described storage tube with select the side of pipe carry out silicon nitride deposition and etch, form the side wall being positioned at storage tube and selecting pipe side;
Step 11, select to carry out source and drain injection between pipe side walls at adjacent two, form the source and drain injection region being positioned at silicon substrate;
Step 12, at storage tube with select pipe and silicon substrate upper end deposit interlevel oxide layer, and chemico-mechanical polishing is carried out to interlevel oxide layer;
Step 13, etch described interlevel oxide layer, between adjacent two storage tubes and adjacent two select to form contact hole respectively between pipes;
Step 14, in described contact hole, carry out tungsten deposit, fill up contact hole, then carry out the chemico-mechanical polishing of tungsten.
7. manufacture method as claimed in claim 6, is characterized in that: adjacent two memory cell are placed back-to-back, and select pipe to share a contact hole for adjacent two, adjacent two storage tubes share a contact hole.
8. manufacture method as claimed in claim 6, is characterized in that: described storage tube polysilicon gate thickness is
9. manufacture method as claimed in claim 6, is characterized in that: silicon nitride layer on described storage tube grid, its thickness is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510992684.2A CN105470261A (en) | 2015-12-25 | 2015-12-25 | Sonos memory and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510992684.2A CN105470261A (en) | 2015-12-25 | 2015-12-25 | Sonos memory and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878440A (en) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | SONOS non-volatility memorizer and its manufacturing method |
| CN109148464A (en) * | 2018-07-26 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Divide the manufacturing method of grid SONOS |
| CN109545792A (en) * | 2018-11-29 | 2019-03-29 | 上海华力微电子有限公司 | A kind of SONOS storage organization and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070278564A1 (en) * | 2006-05-30 | 2007-12-06 | Renesas Technology Corp. | Semiconductor device |
| CN104538363A (en) * | 2014-12-29 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | SONOS flash memory memorizer structure and manufacturing method |
-
2015
- 2015-12-25 CN CN201510992684.2A patent/CN105470261A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070278564A1 (en) * | 2006-05-30 | 2007-12-06 | Renesas Technology Corp. | Semiconductor device |
| CN104538363A (en) * | 2014-12-29 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | SONOS flash memory memorizer structure and manufacturing method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878440A (en) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | SONOS non-volatility memorizer and its manufacturing method |
| CN109148464A (en) * | 2018-07-26 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Divide the manufacturing method of grid SONOS |
| CN109545792A (en) * | 2018-11-29 | 2019-03-29 | 上海华力微电子有限公司 | A kind of SONOS storage organization and its manufacturing method |
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