TW513789B - Manufacturing method of flash memory with floating gate, control gate and erase gate - Google Patents

Abstract

The present invention discloses a manufacturing method of a flash memory, which comprises the steps of: forming a gate dielectric layer on a substrate; then, depositing a first doped polysilicon layer on a tunnel dielectric layer; next, forming an inner polysilicon dielectric layer, a second polysilicon layer and a cap layer on the first polysilicon layer; afterwards, etching the polysilicon layer, cap layer and inner polysilicon dielectric layer to form a control gate; then, performing a thermal oxidizing process to form an oxide spacer on the sidewall of the control gate, and form a oxide layer on the exposed surface of the floating gate; removing the oxide layer on the first polysilicon layer; then, using the cap layer and oxide spacer as an etching mask to etch the first polysilicon layer for forming a floating gate, thereby exposing the sidewall of the floating gate; then, forming a thermal oxide layer on the exposed sidewall of the floating gate; forming a polysilicon tunnel oxide layer by the thermal oxide layer; next, forming a polysilicon spacer on the side of the control gate and floating gate; then, using plasma etching to remove the polysilicon spacer on the source edge, thereby forming an erase gate on the drain edge.

Description

513789 V. Description of the invention (1) Field of the invention: The present invention relates to a semiconductor device, particularly a method for manufacturing a flash memory. Background of the Invention: The prior art has disclosed various flash memories, such as ...

Mitrochel lx proposed EPROMs with self-aligned planar array cells. In this technique, a buried diffusion layer is used as a bit line and self-aligned (sel f — al igned) on the floating gate. Which revealed the cross-shaped dot array technology. Self-aligned sources and electrodes allow components to be efficiently programmed faster. Please refer to AT Mitchell X in IEDM, Tech. Ρρ · 5 48-5 53, 1 987 ', A new self-aligned planar cell for ultra high density EPROMs " 0 Flash memory is a non-volatile memory device. One. Such elements include a floating gate that stores charge and a control gate that removes charge from the floating gate. One application of flash memory is the BI 0S ° of computers. Typical high-density non-volatile memory can be used as a mass storage device for portable handy terminals, solid state cameras, and PC cards. use. This is due to the many advantages of non-volatile memory, such as fast read times and low energy consumption. Furthermore,

513789 V. Description of Invention (2) It is also used to replace disk memory. Bergmnt proposed another cell array for mobile computers and telecommunications (te ecommunicate), published in IEEE Trans. Electronic Components, 乂 〇1. £ 1) -43 ,? .1510, 1996, "1 ^ 111〇111: Low-voltage nvgth proposed by others: a high-performance 3V / 5V flash memory technology used in portable computer use and telecommunications. This cell structure introduces a fast Low voltage NOR virtual ground (NVG) flash memory with access time. In this flash memory array, a field oxide layer (FOX) is formed between each unit cell. The polysilicon layer extending on the FOX provides an appropriate coupling rate. Bergmont also mentioned that portable computers and telecommunications have become a major driving force in the field of integrated circuits. In this paper, access time is low for low Voltage read operation is one of the important considerations. The NVG array uses a select element to achieve the purpose of fast access time. It uses a single segment to replace the all-bit line to reduce the pre-charge time. Non-volatile memory The trend is toward low power supply and fast access, because these requirements are necessary for mobile computer system applications. Flash memory requires the charge to be stored in the floating gate for a long period of time. Therefore, dielectrics used for insulation in floating gates need to be of very high quality. At present, low-voltage flash memories are applied to floating gates with a voltage of about 3 V or 5 V during charging or discharging. . According to the conventional technology, tunneling (tu ηn e 1 i ng) is caused by

513789 V. Description of the invention (3) Basic mechanism of charging or discharging. To achieve high tunneling efficiency, the thickness of the dielectric layer between the floating gate and the substrate must be reduced proportionally as the supply voltage is reduced. U.S. Patent 6,180,45 9 is entitled "Method for fabricating a flash memory with shallow trench isolation" and was filed by Sheu on January 8, 1999. Chen et al. Disclosed a method named `` Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby '' in U.S. Patent No. 6, 1 72, 3 9 5 and let it pass through Taiwan Semi conductor Manufacturing Company (Hs i-Chu, TW). In addition, related US patent 4,794, 565, disclosed by Wu et al. In 1988, is named n Electrically programmable memory device source side injection1.

U.S. Patent Nos. 5,712,179, disclosed by Yuan et al., Erase gates are formed in individual trenches between rows of floating gates. The erase gate is located along one of the sides of the ditch and fits into the floating gate adjacent to the ditch, but is separated from the other ditch rows. In this way, a separate erase gate can be provided to each row of floating gates without increasing the size of the array. Another conventional technology is U.S. Patent 5, 5 34, 4 5 6. The above-mentioned conventional technology describes a new EEPROM

513789 V. Description of the invention (4) Element, which is a non-contact virtual array (c ο n t a c 11 e s s v i r t u a 1 g r o u n d a r r a y), a separate gate flash memory. Object and summary of the invention: The object of the present invention is to form a flash memory with a floating gate, a control gate and an erase gate. Another object of the present invention is to form a control gate and a MOS transistor at the same time. The invention discloses a method for manufacturing a stacked flash memory, which includes the following steps: providing a semiconductor substrate, forming a thin tunneling dielectric layer on the substrate, and then depositing a first doped polycrystalline silicon layer on the tunneling On top of the dielectric layer, an inner polycrystalline silicon dielectric layer, a second polycrystalline silicon layer, and a cover layer are formed on the first polycrystalline silicon layer. It must be noted that the inner polycrystalline silicon dielectric layer, A second polycrystalline silicon layer and a capping layer are also formed on the regions where the PMOS and NMOS are formed. Thereafter, a standard lithography and etching step is used to etch the polycrystalline silicon layer, the capping layer and the inner polycrystalline silicon dielectric layer to form The gate is controlled, and a transistor is formed on the PMOS and NMOS at the same time. Then, a thermal oxidation process is performed to form an oxide layer barrier on the sidewall of the control gate, and a first thermal oxide layer is formed on the first polycrystalline silicon. Layer of exposed surface

513789 V. Description of the invention (5) The upper 0 layers are broken, and the most electrically covered crystal wall is broken on the sides, covering the multi-sided side crystals. The pole material, the gate is carved, and the remaining poles are connected to the floating gate, and the polar gate is exposed to the floating layer, and the step mask is exposed. The oxygen-carved fruit layer on the oxygen-floating layer is implanted on the eroded junction electrode formed with the slurry, and the oxygen-cutting electrode and the sub-layer are used as extremely hot thyristors to separate. The first interstitial gap of the second wall of the silicon barrier gate is controlled by the first interstitial gap, which is formed by the micro-interval and formed by the micro-transmission and the first layer. After the wall and the layer are removed, the crystals are detailed after the invention. The invention proposes a novel method for manufacturing non-volatile flash memory. In this method, PMOS, NMOS and control gate are formed in one step at the same time. The detailed description is as follows. The present invention first provides a semiconductor substrate, such as a semiconductor substrate 2 of a first conductivity type (P-type), in which a well having a second conductivity type (N-type) is formed. In a preferred embodiment, '' as shown in FIG. 1 is a single-crystal silicon substrate 2 having a crystal orientation < 100 > or < 1 1 1 >. Next, a package is formed on the substrate 2

513789 V. Description of the invention (6) Thin tunnel dielectric layer 4 containing silicon oxide. A typical oxide layer 4 can be formed with oxygen in an environment at a temperature of about 700 to 110 ° C. The tunnel oxide layer 4 may also be formed by chemical vapor deposition (CVD). In this embodiment, the thickness of the silica dioxide layer 4 is about 15 to 250 angstroms. Then, a first doped polycrystalline silicon layer 6 is formed on the tunneling dielectric layer 4. In general, the polycrystalline silicon layer 6 is formed from doped polycrystalline silicon or in-situ polycrystalline silicon. For an embodiment, the doped polycrystalline silicon layer 6 is formed by using phosphorus to form a doped polycrystalline silicon layer, and the source of phosphorus is PH3. Next, as shown in FIG. 1, a polycrystalline silicon layer 6 is etched using a standard lithography and etching process. This etching step can also be omitted and not performed. Next, an inner polycrystalline silicon dielectric layer 8, a second polycrystalline silicon layer 10 and a cover layer 12 are formed on the first polycrystalline silicon layer 6. It must be noted that the inner polycrystalline silicon dielectric layer 8, the second polycrystalline silicon layer 10, and the cover layer 12 are also formed on the area where the PMOS and NMOS are made. Then, a standard lithography and #engraving steps are used to engrav the inner polycrystalline silicon dielectric layer 8, the second polycrystalline silicon layer 10, and the cover layer 12 to form a control gate. In the above steps, the transistors over the PMOS and NMOS regions are also formed at the same time. The plasma etching stoppage is stopped on the first polycrystalline silicon layer 6, and the composition of the inner polycrystalline silicon dielectric layer 8 includes but is not limited to oxide / nitride / oxide (oxide / nitride / oxide: 0N0) or nitride / Oxide (NO).

Page 513789 V. Description of the invention (7) Next, a thermal oxidation process is performed to form an oxide layer spacer on the sidewall of the control gate 14 and the oxide layer 1 4 b is formed on the exposed surface of the floating gate electrode 6 . The optimum temperature range for forming the oxide layer 16 is about 70 ° C to 110 ° C. The width of the oxide barrier wall 14 a can be accurately controlled by the thermal oxidation process, and the thickness of the thermal oxide layer is about 200 to 2000 angstroms. The thermal oxide layers 14a and 14b are formed in an environment containing nitrogen and oxygen, and the temperature range is about 700 ~ 1100 ° C. Please refer to FIG. Next, the oxide layer 1 4b on the first polycrystalline silicon layer is removed by plasma etching, and then the cover layer 12 and the oxide layer spacer 14a are used as an etching mask to etch the first polycrystalline silicon layer 6 The floating gate 6 is formed, and the sidewall of the floating gate 6 is exposed. Then, referring to FIG. 3, a thermal oxide layer 16 is formed on the exposed sidewall of the floating gate to form a polycrystalline silicon-tunneling oxide. Floor. A third polycrystalline silicon layer 18 is then deposited on the surface of the structure constructed by the control gate and the floating gate. The third polycrystalline silicon layer 18 is formed from doped polycrystalline silicon or synchronous (i η-s i t u) polycrystalline silicon, and the third polycrystalline silicon layer 18 is used as the material for erasing the gate. After that, the polycrystalline silicon layer 18 is removed by anisotropic etching to form a polycrystalline silicon spacer on the sides of the control idler electrode 10 and the floating gate electrode 6. The above

513789

V. Description of the Invention (8) The optimal width of the spar spacer wall 18 is 0. 5 to 0. The chemical layer 16 is formed at f containing nitrogen and oxygen. The thermal oxygen range is approximately 700 ~ 1 1 0 ° C. Brother ’s temperature range Next, please refer to Figure 4, using a lithographic mask and a technique to remove the polycrystalline silicon spacers on the source side, and use the technique of water to etch on the drain side. Then, the source and the drain of the transistor formed in the gate substrate 2 are erased by using conventional ion implantation. In this step, a gate structure is used as a mask, and dopants are doped and sub-implanted into the substrate 2. The gate electrode 18 and the floating gate are known as source channel heat. The erased gate oxide layer 16 is formed between the erase electrode 6. The unit cell (ce 1 1) is a source-side channel-hot-electron-injection mechanism (Prgram). Its purpose is to achieve a high critical voltage (more than VCC). high). In order to write the unit cell, the gate is controlled with a certain bias voltage, and the erased gate electrode 18 is also biased at the critical threshold, 7, and near the 'no pole, the bias voltage is close to 0 volts. Under such a bias / attachment, 'channel hot electrons are generated from erasing the gate electrode depletion region' and are injected onto the floating gate due to the existence of high control. Wiping of the unit cell is achieved by poly-to-poly tunneling through the polycrystalline silicon tunneling through the polycrystalline silicon tunneling layer 16 to the polycrystalline silicon. The dielectric layer 介 between the dielectric 16 and the control gate 10 is thick enough to eliminate

513789 V. Description of the invention (9) In addition to the leakage current in between. For those skilled in the art, although the present invention is explained above with a preferred example, it is not intended to limit the spirit of the present invention. Modifications and similar arrangements made without departing from the spirit and scope of the present invention should be included in the scope of patent applications described below, and such scope should be consistent with the broadest interpretation covering all modifications and similar structures. Therefore, clarifying a preferred embodiment of the present invention as described above can be used to identify various changes made without departing from the spirit and scope of the present invention.

Page 513789 Brief description of the drawings Brief description of the drawings: Through the following detailed description combined with the attached drawings, the above content and many advantages of this invention can be easily understood, of which: Figure 1 is a cross-sectional view of a semiconductor wafer , Shows the step of forming the control gate and the gap between the nitride layer according to the present invention. FIG. 2 is a cross-sectional view of a semiconductor wafer, showing a step of forming a floating gate electrode according to the present invention. FIG. 3 is a cross-sectional view of a semiconductor wafer, showing a step of forming a gate electrode according to the present invention. Fig. 4 is a cross-sectional view of a semiconductor wafer, showing a step of removing polysilicon spacers on the source side according to the present invention. Symbol comparison table: Substrate 2 Oxidation layer 14a, 14b, 16 Polycrystalline silicon layer 6, 10, 1 8 Dielectric layer 8 Cover layer 12 Floating gate electrode 6 Control gate electrode 1 0 Erase gate electrode 16

Page 14 513789 Simple illustration of the polysilicon spacer 1 8 Page 15

Claims (1)

513789 VI. Scope of patent application Patent scope: 1. A flash memory manufacturing method with a floating gate, a control gate, and an erase gate, including the following steps: forming a gate dielectric layer on the substrate Forming a first conductive layer over the gate dielectric layer; forming an inner polycrystalline silicon dielectric layer, a second conductive layer, and a cover layer over the first conductive layer, wherein the inner polycrystalline silicon dielectric Layers, the second conductive layer and the cover layer are also formed on the area where the PMOS and NMOS are made; the second conductive layer layer, the cover layer and the inner polycrystalline silicon dielectric layer are etched to form the control gate, and simultaneously formed A transistor is over the PMOS and NMOS regions; a thermal oxidation process is performed to form an oxide layer barrier on the control gate sidewall, and a first thermal oxide layer is formed on the exposed surface of the first conductive layer Removing the oxide layer on the first conductive layer; using the gap between the cover layer and the oxide layer as an etching mask to etch the first conductive layer to form the floating gate electrode, and exposing the floating gate electrode Sidewall of the gate; forming a second thermal oxide layer on the floating gate of the exposed side walls, to form a tunneling oxide layer; Page 16 513789 6. The scope of the patent application forms a polycrystalline silicon spacer on the control gate and the side wall of the floating gate; removing the above polycrystalline silicon spacer on the source side to form the erased gate on the drain side ; And forming a source and a drain in the substrate. 2. A flash memory manufacturing method having a floating gate, a control gate, and an erase gate, as described in item 1 of the scope of the patent application, wherein the gate dielectric layer includes an oxide. 3. The method for manufacturing a flash memory having a floating gate, a control gate, and an erase gate according to item 1 of the scope of patent application, wherein the inner polycrystalline silicon dielectric layer includes an oxide / nitride V oxide. 4. The method for manufacturing a flash memory having a floating gate, a control gate, and an erase gate according to item 1 of the scope of the patent application, wherein the inner polycrystalline silicon dielectric layer includes a nitride / oxide. 5. The flash memory manufacturing method with a floating gate, a control gate and an erase gate as described in item 1 of the scope of patent application, wherein the first and second thermal oxide layers are in an environment containing nitrogen and oxygen. Medium, formed at a temperature of about 700 ° C to 100 ° C. 6.If there is a floating gate or control gate in the scope of patent application Page 17 513789 VI. Scope of patent application and manufacturing method of flash memory for erasing gate, wherein the above-mentioned tunneling oxide layer includes oxide fragments. 7. The method for manufacturing a flash memory having a floating gate, a control gate, and an erase gate according to item 1 of the scope of patent application, wherein the first conductive layer includes polycrystalline silicon. 8. The method for manufacturing a flash memory having a floating gate, a control gate, and an erase gate according to item 1 of the scope of the patent application, wherein the second conductive layer includes polycrystalline silicon. 9. The method for manufacturing a flash memory having a floating gate, a control gate, and an erase gate according to item 1 of the scope of the patent application, further comprising a third conductive layer for forming a polycrystalline fracture wall. 1 0. A method for manufacturing a flash memory with a floating gate, a control gate, and an erase gate includes the following steps: forming a gate dielectric layer on a substrate; forming a first conductive layer Over the gate dielectric layer; forming an inner polycrystalline silicon dielectric layer, a second conductive layer and a cover layer on the first conductive layer; etching the second conductive layer, the cover layer and the inner polycrystalline silicon A dielectric layer to form a control gate; performing a thermal oxidation process to form an oxide barrier wall on the control gate Page 18 513789 VI. The scope of patent application is above the extreme sidewall, and a first thermal oxide layer is formed on the exposed surface of the first conductive layer polycrystalline silicon layer; removing the oxide layer on the first conductive layer; using the cover The gap between the layer and the oxide layer is used as an etching mask to etch the first conductive layer to form a floating gate electrode. As a result, a side wall of the floating gate electrode is exposed; a second thermal oxide layer is formed on the floating gate electrode. Forming a tunnel oxide layer on the exposed sidewalls; forming a polysilicon spacer on the sidewalls of the control gate and the floating gate; and removing the control gate and the floating gate formed on the source side The polycrystalline silicon spacers on the sides form an erase gate on the drain side. 1 1. The method for manufacturing a flash memory having a floating gate, a control gate, and an erase gate, as described in item 10 of the scope of patent application, wherein the gate dielectric layer includes an oxide. 12. The method for manufacturing a flash memory with a floating gate, a control gate, and an erase gate according to item 10 of the scope of patent application, wherein the inner polycrystalline silicon dielectric layer includes an oxide / nitride / Oxide. Page 19 513789 VI. Application scope of patent 13. For the method of manufacturing flash memory with floating gate, control gate and erasing gate, the above-mentioned inner polycrystalline silicon dielectric layer Contains nitrides / oxides. 1 4. A method for manufacturing a flash memory having a floating gate, a control gate, and an erase gate according to item 10 of the scope of the patent application, wherein the first and second thermal oxide layers are formed by containing nitrogen and In an oxygen environment, the temperature is about 700 ° C to 100 ° C. 15. The method for manufacturing a flash memory having a floating gate, a control gate, and an erase gate according to item 10 of the scope of patent application, wherein the tunneling oxide layer includes silicon oxide. 16. The method for manufacturing a flash memory with a floating gate, a control gate, and an erase gate according to item 10 of the scope of patent application, wherein the first and second conductive layers include polycrystalline silicon. Page 20