CN104465387A - Manufacturing method of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, and the surface of the semiconductor substrate has a gate structure; forming a mask layer covering the semiconductor substrate and the gate structure; patterning the mask layer , using the patterned mask layer as a mask, etching the semiconductor substrate adjacent to the gate structure to form a groove; using the first selective epitaxial process to form a stress film in the groove; using the second Two selective epitaxial processes etch the mask layer, and the etching rate of the defect film in the second selective epitaxial process is greater than the etching rate of the corresponding stress film; alternately perform the first selective epitaxial process process and the second selective epitaxial process until a stress layer filling the groove is formed. In the process of forming the stress layer, the invention performs etching treatment on the surface of the mask layer, avoids the formation of defective films on the surface of the mask layer, and optimizes the electrical performance of the semiconductor device.

Description

Manufacturing method of semiconductor device

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device.

Background technique

With the continuous development of semiconductor technology, carrier mobility enhancement technology has been widely studied and applied. Improving the carrier mobility in the channel region can increase the driving current of MOS devices and improve the performance of the devices.

In the existing manufacturing process of semiconductor devices, since stress can change the energy gap and carrier mobility of silicon materials, it has become more and more common means to improve the performance of semiconductor devices through stress. Specifically, by properly controlling the stress, the mobility of carriers (electrons in NMOS devices, holes in PMOS devices) can be increased, thereby increasing the driving current, thereby greatly improving the performance of semiconductor devices.

At present, embedded silicon germanium (Embedded SiGe) or/and embedded silicon carbon (Embedded SiC) technology is used, that is, the silicon germanium material is first formed in the region where the source region and the drain region of the PMOS region need to be formed, and then doped to form The source region and the drain region of the PMOS device, in the region of the source region and the drain region of the NMOS region, a carbon silicon material is first formed, and then doped to form the source region and the drain region of the NMOS device; the silicon germanium material is formed to introduce Compressive stress created by lattice mismatch between silicon and silicon germanium (SiGe) to enhance the performance of PMOS devices. The silicon carbon material is formed to introduce tensile stress formed by lattice mismatch between silicon and silicon carbon (SiC), so as to improve the performance of the NMOS device.

The application of embedded silicon germanium and embedded silicon carbon technologies can improve the carrier mobility of semiconductor devices to a certain extent, but in practical applications, it is found that there are still problems to be solved in the manufacturing process of semiconductor devices.

Contents of the invention

The problem to be solved by the invention is to provide an optimized manufacturing method of a semiconductor device, which avoids the formation of defective films on the surface of the mask layer, improves the reliability of the semiconductor device, and optimizes the electrical performance of the semiconductor device.

In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, and the surface of the semiconductor substrate has a gate structure; forming a mask layer covering the semiconductor substrate and the gate structure ; patterning the mask layer, using the patterned mask layer as a mask, etching the semiconductor substrate adjacent to the gate structure to form a groove; using a first selective epitaxy process in the groove A stress film is formed in the groove; the mask layer is etched by a second selective epitaxy process, and a cover film is formed on the surface of the stress film at the same time, and the etching rate of the defect film by the second selective epitaxy process is greater than Etching rate of the stress film: performing the first selective epitaxial process and the second selective epitaxial process alternately until the stress layer filling the groove is formed.

Optionally, the reaction gas of the first selective epitaxy process includes a first etching gas, the reaction gas of the second selective epitaxy process includes a second etching gas, and the flow rate of the second etching gas is greater than First etching gas flow.

Optionally, the flow rate of the first etching gas is 1 sccm to 300 sccm, and the flow rate of the second etching gas is 5 sccm to 500 sccm.

Optionally, the first etching gas is HCl, and the second etching gas is HCl.

Optionally, while forming the stress film, the defect film is formed on the surface of the mask layer.

Optionally, the material of the covering film is Si, SiGe, SiGeB, SiC or SiCP.

Optionally, the stress type of the covering film is the same as that of the stress film.

Optionally, when the material of the capping film is SiGe, the reaction gas of the second selective epitaxial process includes a second etching gas, and the reaction gas further includes silicon source gas, germanium source gas and H ₂ .

Optionally, when the material of the covering film is SiGe, the specific process parameters of the second selective epitaxial process are: the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , the germanium source gas is GeH ₄ , the silicon source gas is The flow rate is 5sccm to 500sccm, the germanium source gas flow rate is 5sccm to 500sccm, the _H2 flow rate is 1000sccm to 50000sccm, the second etching gas flow rate is 5sccm to 5000sccm, the reaction chamber temperature is 400 degrees to 900 degrees, and the chamber pressure is 1 Torr to 100 Torr.

Optionally, the material of the stress film is Si, SiGe, SiGeB, SiC or SiCP.

Optionally, the specific process parameters of the first selective epitaxy process are: the reaction gas includes not only the first etching gas, but also the silicon source gas, the germanium source gas and H ₂ , wherein the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , germanium source gas is GeH ₄ , silicon source gas flow rate is 5 sccm to 500 sccm, germanium source gas flow rate is 5 sccm to 500 sccm, H ₂ flow rate is 1000 sccm to 50000 sccm, first etching gas flow rate is 1 sccm to 300 sccm, the reaction chamber temperature is 400 to 900 degrees, and the chamber pressure is 1 torr to 100 torr.

Optionally, the reaction gas further includes a boron source gas, the boron source gas is B ₂ H ₆ , and the flow rate of the boron source gas is 5 sccm to 500 sccm.

Optionally, the material of the mask layer is silicon nitride.

Optionally, the mask layer is formed by using a chemical vapor deposition process.

Optionally, the specific process parameters of the chemical vapor deposition process are: feed NH ₃ and silicon source gas into the reaction chamber, the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , wherein the flow rate of NH ₃ is 5 sccm to 1000 sccm, the flow rate of the silicon source gas is 5 sccm to 500 sccm, the temperature of the reaction chamber is 300 degrees to 800 degrees, and the pressure of the reaction chamber is 0.05 Torr to 50 Torr.

Optionally, the formed semiconductor device is an NMOS transistor, a PMOS transistor or a CMOS transistor.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In this embodiment, after the first selective epitaxial process is used to form the stress film in the groove, due to the similar structure of the mask layer and the stress film material, a defect film is formed on the surface of the mask layer; The mask layer is etched, and the defect film located on the surface of the mask layer is etched and removed; the first selective epitaxial process and the second selective epitaxial process are alternately performed until the stress filling the groove is formed. layer; since the mask layer is alternately etched during the formation of the stress layer, when the stress layer is formed, the defect film on the surface of the mask layer is completely removed by etching, which reduces the subsequent removal of the mask layer. The process difficulty of the layer, and the mask layer is completely removed, which is conducive to the formation of metal silicides in close contact on the top of the gate structure, avoiding the formation of metal silicides in undesired areas, improving the reliability of semiconductor devices, and optimizing the electronics of semiconductor devices performance.

At the same time, in this embodiment, the second selective epitaxy process includes an etching process to remove the defect film on the surface of the mask layer in the selective epitaxy process; a deposition process is also included in the selective epitaxy process. A cover film is formed on the surface of the stress film; therefore, in this embodiment, while removing the defect film on the surface of the mask layer, a cover film is formed on the surface of the stress film. Compared with only etching, the present invention avoids Second, selective epitaxial process etching removes part of the stress film, resulting in longer process time for filling the groove, improving the production efficiency of semiconductor devices and shortening the production cycle.

Further, in this embodiment, an optimized process is used to carry out the second selective epitaxy process, and the flow rate of the second etching gas in the second selective epitaxy process is greater than that of the first etching gas in the first selective epitaxy process. The gas flow rate ensures that after the second selective epitaxial process is completed, the defect film on the surface of the mask layer is completely removed, and the electrical performance of the semiconductor device is improved.

Description of drawings

Fig. 1 is a schematic flow chart of forming a semiconductor device according to an embodiment;

2 to 8 are schematic cross-sectional structure diagrams of the manufacturing process of a semiconductor device according to another embodiment of the present invention.

Detailed ways

It can be seen from the background art that there are still problems to be solved in the formation process of semiconductor devices in the prior art.

According to research on the formation process of semiconductor devices, it is found that the formation process of semiconductor devices includes the following steps, please refer to Figure 1: step S1, providing a semiconductor substrate, the semiconductor substrate includes a first region and a second region; step S2, in A first gate structure is formed on the surface of the semiconductor substrate in the first region, a second gate structure is formed on the surface of the semiconductor substrate in the second region, and both sides of the first gate structure and the second gate structure have Offset sidewalls; step S3, forming a mask layer covering the semiconductor substrate, the first gate structure and the second gate structure; step S4, patterning the mask layer, using the patterned mask layer as a mask film, etching the semiconductor substrate adjacent to the first gate structure to form a groove; Step S5, using a selective epitaxy process to form a stress layer filling the groove; Step S6, removing the mask layer; Step S7, forming a metal silicide on top of the first gate structure and the second gate structure.

For the semiconductor device formed by the above process steps, the process of removing the mask layer is very difficult, and after the process of removing the mask layer is completed, the semiconductor device, the top and side walls of the first gate structure, and the top and side walls of the second gate structure Metal silicides are formed on the walls, which affects the electrical performance of the semiconductor device, resulting in poor reliability of the semiconductor device.

Further studies on the formation process of semiconductor devices have found that the above problems are caused by the fact that there are more floating Si bonds in the material of the mask layer, and the material of the stress layer contains more Si atoms, so the floating Si bonds The existence of the stress layer material is similar to that of the mask layer material. When the stress layer is formed by the selective epitaxy process, the stress layer material will also grow on the mask layer surface, that is, a defect film is formed on the mask layer surface; the stress layer After the formation process is completed, there is a defect film on the surface of the mask layer, and the defect film covers the surface of the mask layer, so that the mask layer cannot be removed; subsequently, a metal layer is formed on the top of the first gate structure and the top of the second gate structure. In the case of silicide, since the mask layer cannot be removed and a defective film is formed on the surface of the mask layer, the defect film provides Si atoms for the formation of metal silicide, and metal silicide is formed on the surface of the mask layer, resulting in A metal silicide is formed, thereby deteriorating the electrical performance of the semiconductor device and deteriorating the reliability of the semiconductor device.

At the same time, since the defect film is also formed on the surface of the mask layer above the groove, the process window for filling the groove is reduced, and the reduction of the process window increases the difficulty of forming a high-quality stress layer in the groove, and the formed stress The quality of the layer deteriorates.

To this end, the present invention provides an optimized method for forming a semiconductor device. After the stress film is formed in the groove by the first selective epitaxial process, the mask layer is etched by the second selective epitaxial process; The first selective epitaxial process and the second selective epitaxial process until the stress layer filling the groove is formed; the defect film grown on the surface of the mask layer is removed by etching to improve the reliability of the semiconductor device, Improve the electrical performance of semiconductor devices.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

The semiconductor device formed in the present invention is an NMOS transistor, a PMOS transistor or a CMOS transistor. In this embodiment, the formed semiconductor device is a CMOS transistor for exemplary illustration.

2 to 8 are schematic cross-sectional structure diagrams of the manufacturing process of the semiconductor device provided by the present invention.

Referring to FIG. 2 , a semiconductor substrate 200 is provided, and the surface of the semiconductor substrate 200 has a gate structure.

In this embodiment, the semiconductor substrate 200 includes the first region I and the second region II, and the semiconductor device formed is a CMOS transistor for exemplary illustration, and the positions of the first region I and the second region II can be mutually Change.

In this embodiment, the gate structure includes a first gate structure 210 located on the surface of the semiconductor substrate 200 in the first region I and a second gate structure 220 located on the surface of the semiconductor substrate 200 in the second region II.

In other embodiments of the present invention, if the semiconductor substrate only includes one of the first region or the second region, the gate structure only includes the gate structure on the surface of the semiconductor substrate in the first region or the semiconductor substrate in the second region. Gate structures on the substrate surface.

The semiconductor substrate 200 is one of monocrystalline silicon, polycrystalline silicon, amorphous silicon or silicon-on-insulator; the semiconductor substrate 200 can also be a Si substrate, a Ge substrate, a SiGe substrate or a GaAs substrate .

Several epitaxial interface layers or strain layers can also be formed on the surface of the semiconductor substrate 200 to improve the electrical performance of the semiconductor device.

In this embodiment, the semiconductor substrate 200 is a Si substrate.

In this embodiment, an isolation structure 201 is further provided in the semiconductor substrate 200 to prevent electrical connection between the first region I and the second region II. The filling material of the isolation structure 201 may be one or more of silicon oxide, silicon nitride or silicon oxynitride.

In order to meet the development trend of continuous miniaturization of semiconductor devices, there may be one first gate structure or multiple first gate structures on the surface of the semiconductor substrate in the first region I, and the materials of the multiple first gate structures and structures can be the same or different; the surface of the second region II semiconductor substrate can have a second gate structure or multiple second gate structures, and the materials and structures of multiple second gate structures can be the same It can also be different.

In this embodiment, one first gate structure 210 is formed on the surface of the semiconductor substrate 200 in the first region I, two second gate structures 220 are formed on the surface of the semiconductor substrate 200 in the second region II, and the two second gate structures The material and structure of 220 are the same, and the sidewall of one of the second gate structures 220 is adjacent to the isolation structure 201 for exemplary illustration. In other embodiments of the present invention, the first gate structure or the second gate structure may be partly located on the surface of the isolation structure or away from the isolation structure, and the relationship between the first gate structure or the second gate structure and the isolation structure should not be restricted too much. positional relationship between them.

The first gate structure 210 includes a first gate oxide layer 211 on the surface of the semiconductor substrate 200 , and a first gate electrode layer 212 on the surface of the first gate oxide layer 211 .

The second gate structure 220 includes a second gate oxide layer 221 on the surface of the semiconductor substrate 200 , and a second gate electrode layer 222 on the surface of the second gate oxide layer 221 .

The material of the first gate oxide layer 211 or the second gate oxide layer 221 is silicon oxide or a high-k dielectric material, and the material of the first gate electrode layer 212 or the second gate electrode layer 222 is polysilicon, doped polysilicon or metal.

Please continue to refer to FIG. 2 , an offset spacer 202 is formed on the surface of the semiconductor substrate 200 , and the offset spacer 202 is located on both sides of the first gate structure 210 or the second gate structure 220 .

The offset spacer 202 protects both sides of the first gate structure 210 or the second gate structure 220 from being damaged by the subsequent process; in order to prevent the short channel effect of the semiconductor device, the semiconductor substrate 200 on both sides of the gate structure A pocket area is formed inside, and the offset sidewall 202 is a mask for forming the pocket area.

The material of the offset sidewall 202 is silicon oxynitride or silicon nitride, and the offset sidewall 202 can be a single-layer structure or a multi-layer structure.

In this embodiment, the offset sidewall 202 is a single-layer structure of silicon nitride.

Before forming the offset spacer 202, lightly doped ion implantation can also be performed on the semiconductor substrate 200 on both sides of the first gate structure 210 or the second gate structure 220 to form a lightly doped region (LDD ), to prevent the hot carrier effect in semiconductor devices.

After the offset spacer 202 is formed, ion implantation can be performed on the semiconductor substrate 200 on both sides of the first gate structure 210 or the second gate structure 220 to form a pocket region, and the pocket region and the lightly doped The impurity region is of the opposite type, which prevents the short channel effect of the semiconductor device.

It should be noted that the formation of the offset sidewall 202 is optional but not necessary.

Referring to FIG. 3 , a mask layer 203 covering the semiconductor substrate 200 and the gate structure is formed.

Specifically, in this embodiment, the mask layer 203 covers the semiconductor substrate 200 , the offset spacer 202 , the first gate structure 210 and the second gate structure 220 .

The function of the mask layer 203 is to serve as a mask for subsequent etching of the semiconductor substrate 200 to form a groove, and to protect the first gate structure 210 in the first region I from being damaged by the formation process of the groove.

The mask layer 203 is used as a mask for the subsequent groove formation process, and the material of the mask layer 203 must meet the following two conditions: first, when the stress layer is formed by the subsequent selective epitaxy process, the stress layer only fills the groove , therefore, there must be a high selectivity between the mask layer 203 and the material of the semiconductor substrate 200; secondly, there is a hydrofluoric acid solution in the subsequent groove formation and groove cleaning process, therefore, the mask layer 203 The material must have a high ability to resist etching by hydrofluoric acid solution. In order to meet the above requirements on the material of the mask layer 203 , as an embodiment, the material of the mask layer 203 is silicon nitride, and the thickness of the mask layer 203 is 50 angstroms to 200 angstroms.

The mask layer 203 is formed by chemical vapor deposition process.

As an example, the specific process parameters of the chemical vapor deposition are: feed NH ₃ and silicon source gas into the reaction chamber, the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , wherein the flow rate of NH ₃ is 5 sccm to 1000 sccm, the flow rate of the silicon source gas is 5 sccm to 500 sccm, the temperature of the reaction chamber is 300 degrees to 800 degrees, and the pressure of the reaction chamber is 0.05 Torr to 50 Torr.

Referring to FIG. 4, the mask layer 203 is patterned to form an opening 204 in the mask layer 203, the opening 204 exposing the surface of the second region II semiconductor substrate 200 adjacent to the second gate structure 220, And the position and width of the opening 204 correspond to the position and width of the subsequently formed groove.

As an embodiment, the forming process of the opening 204 is: forming a photoresist layer covering the mask layer 203, the photoresist layer has a pattern corresponding to the opening 204, and the photoresist layer is mask, etch the mask layer 203 to form an opening 204 in the mask layer 203 , and the opening 204 exposes the surface of the second region II semiconductor substrate 200 adjacent to the second gate structure 220 .

In other embodiments of the present invention, if the second gate structure is far away from the isolation structure, openings are formed in the mask layer on both sides of the second gate structure, and then the semiconductor substrate in the second region on both sides of the second gate structure is Grooves are formed in the bottom.

It should be noted that, in this embodiment, the opening exposes the surface of the semiconductor substrate in the second region as an exemplary illustration. In other embodiments of the present invention, the opening exposes the first region adjacent to the first gate structure. surface of the semiconductor substrate.

Referring to FIG. 5 , using the patterned mask layer 203 as a mask, the semiconductor substrate 200 adjacent to the gate structure is etched to form a groove 205 .

Specifically, using the patterned mask layer 203 as a mask, the second region II semiconductor substrate 200 adjacent to the second gate structure 220 is etched along the opening 204 (please refer to FIG. 4 ) to form a groove 205 .

The shape of the groove 205 is U-shape, square or sigma (Σ) shape.

As an embodiment, the shape of the groove 205 is Σ-shape.

The sidewall of the Σ-shaped groove is concave toward the direction of the device channel. This shape can effectively shorten the length of the device channel and meet the requirements of device size miniaturization; and the Σ-shaped groove has a large undercut under the gate spacer. The characteristics of the stress material formed in the groove of this shape can generate greater stress on the channel region of the device.

The formation process of the groove 205 may be dry etching, wet etching or an etching process combining dry etching and wet etching.

As an example, the formation process of the Σ-shaped groove 205 is exemplified: firstly, the semiconductor substrate 200 is etched along the opening 204 by using the mask layer 203 as a mask, using a dry etching process, An inverted trapezoidal pre-groove is formed, and then a wet etching process is used to continuously etch the pre-groove to form a Σ-shaped groove 205 .

Referring to FIG. 6 , a stress film 206 is formed in the groove 205 by a first selective epitaxial process.

The material of the stress film 206 is Si, SiGe, SiGeB, SiC or SiCP.

As an example, the stress film 206 provides compressive stress for the channel region of the second region II, and the material of the stress film 206 is a compressive stress material, and the material of the stress film 206 is SiGe or SiGeB. The material of the stress film 206 can also be Si.

As another embodiment, the stress film provides tensile stress for the channel region of the second region, the material of the stress film is a tensile stress material, the material of the stress film is SiC or SiCP, and the material of the stress film is also Can be Si.

The reaction gas of the first selective epitaxial process includes a first etching gas, and the first etching gas is HCl (hydrogen chloride), and HCl as the first etching gas has a relatively high selective etching capability; The first etching gas may also be other halogen-containing gases, for example, HBr (hydrogen bromide) or HI (hydrogen iodide).

As an example, the specific process parameters of the first selective epitaxy process are: in addition to the first etching gas, the reaction gas also includes silicon source gas, germanium source gas and H ₂ , wherein the silicon source gas SiH ₄ or SiH ₂ Cl ₂ , germanium source gas is GeH ₄ , silicon source gas flow rate is 5 sccm to 500 sccm, germanium source gas flow rate is 5 sccm to 500 sccm, H ₂ flow rate is 1000 sccm to 50000 sccm, first etching gas flow rate is 1 sccm to 300 sccm, the temperature of the reaction chamber is 400°C to 900°C, and the chamber pressure is 1 Torr to 100 Torr.

It should be noted that, if the material of the stress film 206 is SiGeB, the reaction gas further includes a boron source gas, the boron source gas is B ₂ H ₆ , and the flow rate of the boron source gas is 5 sccm to 500 sccm.

The selective epitaxial process includes a deposition process and an etching process. In this embodiment, since the flow rate of the etching gas in the first selective epitaxial process is relatively small, specifically, the flow rate of the first etching gas is 1 sccm to 300 sccm, therefore, In this embodiment, the first selective epitaxy process is mainly a deposition process, and the deposition rate in the selective epitaxy process is greater than the etching rate, and the stress film 206 is formed in the groove 205 .

The thickness of the stress film 206 can be determined according to actual needs, for example, the thickness of the stress film 206 is 30 angstroms, 50 angstroms or 80 angstroms. According to the reaction gas flow rate of the first selective epitaxy process and the required thickness of the stress film 206 , the reaction time of the first selective epitaxy process can be determined.

After the first selective epitaxial process is completed, a stress film 206 is formed in the groove 205, and a small amount of material of the stress film 206 is also formed on the surface of the mask layer 203, that is, when the stress film 206 is formed, a stress film 206 is formed on the surface of the mask layer 203. A defective film 207 is formed. This is mainly caused by the following reasons:

Although silicon nitride is used as the material of the mask layer 203, it can basically meet the requirements of good selectivity and strong corrosion resistance, but since the material of the mask layer 203 is silicon nitride, the Si-N bond has a negative effect on Si The binding ability of atoms is limited, resulting in the presence of many floating Si bonds in the material of the mask layer 203. When the stress film 206 is formed by the subsequent selective epitaxy process, the material of the stress film 206 will also grow on the surface of the mask layer 203, that is, the formation of The defect film 207 is formed, and the thickness of the defect film 207 increases as the process of filling the groove 205 continues.

As an example, the material of the first gate electrode layer 212 or the second gate electrode layer 222 is polysilicon or doped polysilicon, then after the mask layer 203 is subsequently removed, the top of the first gate structure 210 or the second A salicide is formed on top of the two-gate structure 220 . If there is a defect film 207 on the surface of the mask layer 203, then after the stress layer is formed, the defect film 207 must be removed first and then the mask layer 203, and removing the defect film 207 will cause the stress layer to be removed, so it cannot be used in the stress layer. A process of removing the defective film 207 after layer formation.

If the defect film 207 is formed on the surface of the mask layer 203 after the stress layer is formed, the mask layer 203 cannot be removed subsequently; Or the metal silicide formed on the top of the second gate structure 220, the metal silicide is formed on the surface of the defect film 207, resulting in the formation of metal silicide in the undesired area, which reduces the reliability of the semiconductor device and affects the reliability of the semiconductor device. Electrical properties; and a defective film 207 is formed on the surface of the mask layer 203 close to the groove 205, causing the process window for filling the groove 205 to gradually become smaller, and the reduction of the process window is not conducive to forming a high-quality stress layer and filling the groove The difficulty of 205 increases, which affects the improvement of carrier mobility in semiconductor devices.

Please refer to FIG. 7 , the mask layer 203 is etched by a second selective epitaxial process, and a cover film 208 is formed on the surface of the stress film 206 at the same time, and the etching of the defect film 207 by the second selective epitaxial process The etch rate is greater than the etch rate for the stress film 206 .

After the first selective epitaxial process is completed, a defective film 207 is formed on the surface of the mask layer 203, but due to the selective nature of the selective epitaxial process, the thickness of the defective film 207 on the surface of the mask layer 203 is much smaller than the stress film 206 thickness, and the material structure difference between the material of the mask layer 203 and the stress film 206 is larger than the material structure difference between the material of the semiconductor substrate 200 and the stress film 206, therefore, the defect film 207 formed on the surface of the mask layer 203 is compact poor and unstable, and the material of the defect film 207 has much poorer etching resistance than the material of the stress film 206, therefore, the etching rate of the defect film 207 in the second selective epitaxial process is greater than that of the stress film 206 rate; the second selective epitaxial process etching removes the thickness of the stress film 206 much smaller than the thickness of the defect film 207, and when the second selective epitaxial process is completed, the second selective epitaxial process will mask the mask layer The defective film 207 on the surface of 203 is completely etched away.

Since the selective epitaxy process includes a deposition process and an etching process, the selective epitaxy process will also etch the defect film 207, and at the same time as the etching process, a deposition reaction will also occur, forming a covering film on the surface of the stress film 206 208, improving the production efficiency of the semiconductor device, avoiding the second selective epitaxial process to etch the stress film 206 to a greater extent while removing the defect film 207, this embodiment shortens the production cycle of the semiconductor device; by controlling the first The flow rate of the etching gas in the second selective epitaxial process improves the etching rate of the second selective epitaxial process, increases the etching rate of the second selective epitaxial process to the defect film 207 on the surface of the mask layer 203, and reaches the rate of removing the defective film 207 Purpose.

The reaction gas of the second selective epitaxy process includes a second etching gas, the second etching gas is HCl (hydrogen chloride), and HCl as the second etching gas has a relatively high selective etching ability, which requires When stated, the second etching gas may also be other halogen-containing gases, for example, HBr (hydrogen bromide) or HI (hydrogen iodide).

The flow rate of the second etching gas is greater than the flow rate of the first etching gas. In this embodiment, the flow rate of the second etching gas is 5 sccm to 500 sccm.

The material of the covering film 208 is Si, SiGe, SiGeB, SiC or SiCP.

In this embodiment, the cover film 208 provides compressive stress for the channel region of the second region II, and the material of the cover film 208 is a compressive stress material, and the material of the cover film 208 is SiGe or SiGeB, so The material of the covering film 208 can also be Si.

In other embodiments of the present invention, the covering film provides tensile stress for the channel region of the first region, and the material of the covering film is a tensile stress material, and the material of the covering film is SiC or SiCP. The material can also be Si.

It should be noted that the stress type of the cover film 208 is the same as that of the stress film 206 .

When the material of the covering film 208 is SiGe, the reaction gas of the second selective epitaxy process also includes silicon source gas, germanium source gas and H ₂ ; the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , germanium source gas is GeH ₄ .

In this embodiment, the specific process parameters of the second selective epitaxy process are: the silicon source gas flow rate is 5 sccm to 500 sccm, the germanium source gas flow rate is 5 sccm to 500 sccm, the _H2 flow rate is 1000 sccm to 50000 sccm, the second etching gas The flow rate is 5sccm to 5000sccm, the reaction chamber temperature is 400°C to 900°C, and the chamber pressure is 1 Torr to 100 Torr.

It should be noted that, if the material of the covering film 208 is SiGeB, the reaction gas further includes a boron source gas, the boron source gas is B ₂ H ₆ , and the flow rate of the boron source gas is 5 sccm to 500 sccm.

In this embodiment, after the second selective epitaxial process is completed, the defect film 207 on the surface of the mask layer 203 is completely removed, while the stress film 206 is hardly affected by the etching process, and a deposition reaction occurs on the surface of the stress film 206 , forming the cover film 208 on the surface of the stress film 206, which improves the production efficiency of the semiconductor device.

Referring to FIG. 8 , the first selective epitaxial process and the second selective epitaxial process are alternately performed until the stress layer 209 filling the groove 205 (please refer to FIG. 7 ) is formed.

The top of the stress layer 209 may be higher than the surface of the semiconductor substrate 200 , or may be flush with the surface of the semiconductor substrate 200 . In this embodiment, the top of the stress layer 209 is flush with the surface of the semiconductor substrate 200 for exemplary illustration.

By alternately performing the first selective epitaxial process and the second selective epitaxial process, the stress film 206 is formed cyclically, the defect film 207 is formed on the surface of the mask layer 203 (please refer to FIG. 6 ), and the covering layer is formed on the surface of the stress film 206. film 208 and removing the defective film 207 located on the surface of the mask layer 203 , finally forming a stress layer 209 filling the groove 205 . The thickness of the stress film 206 formed cyclically may be the same or different, and the thickness of the covering film 208 formed cyclically may be the same or different.

It should be noted that the number of times for performing the first selective epitaxy process and the second selective epitaxy process can be determined by the depth of the groove 205, the reaction gas flow rate of the first selective epitaxy process, and the reaction gas flow rate of the second selective epitaxy process. The flow rate, the thickness of the first stress layer and the thickness of the second stress layer are determined, and the times of the first selective epitaxial process and the second selective epitaxial process should not be excessively limited.

As an example, the material of the first gate electrode layer 212 and the second gate electrode layer 222 is polysilicon or doped polysilicon, then the subsequent process also includes removing the mask layer 203, and the first gate structure 210 and the A metal silicide is formed on the surface of the second gate structure 220 . Since in this embodiment, after the stress layer 209 is formed, there is no defect film on the surface of the mask layer 203, therefore, the process of removing the mask layer 203 is simple, and the mask layer 203 can be completely removed. When the metal silicide is formed on the surface of the first gate structure 210 and the second gate structure 220, the metal silicide is in close contact with the first gate structure 210 and the second gate structure 220, and the metal silicide only Formed on the top of the first gate structure 210 and the second gate structure 220, it is beneficial to improve the reliability of the semiconductor device, reduce the contact resistance of the semiconductor device, increase the operating speed of the semiconductor device, and optimize the electrical performance of the semiconductor device.

In summary, the technical solution provided by the present invention has the following advantages:

First, in the embodiment of the present invention, an optimized process is used to form a stress layer that fills the groove, that is, the first selective epitaxy process and the second selective epitaxy process are alternately performed, and the first selective epitaxy process is formed in the groove The stress film is formed inside, and the mask layer is etched by the second selective epitaxy process; since the mask layer contains floating Si bonds, after the stress film is formed by the first selective epitaxy process, the mask layer A defect film is formed on the surface, and the defect film will reduce the process window for filling the groove and make it difficult to remove the mask layer subsequently; and after the first selective epitaxial process, the second selective epitaxial process is used to etch the mask layer etch treatment, the second selective epitaxial process etches and removes the defect film, avoids the reduction of the process window for filling the groove, improves the quality of forming the stress layer, thereby improving the carrier mobility of the semiconductor device; the second After the selective epitaxial process removes the defect film, the mask layer can be completely removed, so that the subsequent formation of metal silicide is only formed on the top of the gate structure, avoiding the formation of metal silicide in undesired areas, and improving the reliability of semiconductor devices, thereby Optimizing the electrical performance of semiconductor devices.

Secondly, in this embodiment, while the mask layer is etched in the second selective epitaxial process, the second selective epitaxial process forms a cover film on the surface of the stress film, which improves the production of semiconductor devices. Efficiency shortens the production cycle of semiconductor devices.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (16)

1. a manufacture method for semiconductor device, is characterized in that, comprising:

There is provided Semiconductor substrate, and described semiconductor substrate surface has grid structure;

Form the mask layer covering described Semiconductor substrate and grid structure;

Graphical described mask layer, with described patterned mask layer for mask, etches the Semiconductor substrate adjacent with grid structure, forms groove;

The first selective epitaxial process is adopted to form stress film in described groove;

Adopt the second selective epitaxial process to carry out etching processing to described mask layer, form coverlay on stress film surface, and the etch rate of described second selective epitaxial process to defect film is greater than the etch rate of counter stress film simultaneously;

Hocket described first selective epitaxial process and described second selective epitaxial process, until form the stressor layers of filling full described groove.

2. the manufacture method of semiconductor device according to claim 1, it is characterized in that, the reacting gas of described first selective epitaxial process comprises the first etching gas, the reacting gas of described second selective epitaxial process comprises the second etching gas, and described second etching gas flow is greater than the first etching gas flow.

3. the manufacture method of semiconductor device according to claim 2, is characterized in that, described first etching gas flow is 1sccm to 300sccm, and described second etching gas flow is 5sccm to 500sccm.

4. the manufacture method of semiconductor device according to claim 3, is characterized in that, described first etching gas is HCl, and described second etching gas is HCl.

5. the manufacture method of semiconductor device according to claim 1, is characterized in that, while forming stress film, forms described defect film on mask layer surface.

6. the manufacture method of semiconductor device according to claim 1, is characterized in that, the material of described coverlay is Si, SiGe, SiGeB, SiC or SiCP.

7. the manufacture method of semiconductor device according to claim 6, is characterized in that, described coverlay is identical with the stress types of stress film.

8. the manufacture method of semiconductor device according to claim 6, it is characterized in that, when the material of described coverlay is SiGe, the reacting gas of described second selective epitaxial process comprises the second etching gas, and reacting gas also comprises silicon source gas, germanium source gas and H ₂.

9. the manufacture method of semiconductor device according to claim 8, is characterized in that, when the material of described coverlay is SiGe, the concrete technology parameter of described second selective epitaxial process is: silicon source gas is SiH ₄or SiH ₂cl ₂, germanium source gas is GeH ₄, silicon source gas flow is 5sccm to 500sccm, and germanium source gas flow is 5sccm to 500sccm, H ₂flow is 1000sccm to 50000sccm, and the second etching gas flow is 5sccm to 5000sccm, and reaction chamber temperature is 400 degree to 900 degree, and chamber pressure is that 1 holder to 100 is held in the palm.

10. the manufacture method of semiconductor device according to claim 1, is characterized in that, the material of described stress film is Si, SiGe, SiGeB, SiC or SiCP.

The manufacture method of 11. semiconductor device according to claim 2, is characterized in that, the concrete technology parameter of described first selective epitaxial process is: reacting gas is except comprising the first etching gas, and reacting gas also comprises silicon source gas, germanium source gas and H ₂, wherein, silicon source gas is SiH ₄or SiH ₂cl ₂, germanium source gas is GeH ₄, silicon source gas flow is 5sccm to 500sccm, and germanium source gas flow is 5sccm to 500sccm, H ₂flow is 1000sccm to 50000sccm, and the first etching gas flow is 1sccm to 300sccm, and reaction chamber temperature is 400 degree to 900 degree, and chamber pressure is that 1 holder to 100 is held in the palm.

The manufacture method of 12. semiconductor device according to claim 11, is characterized in that, reacting gas also comprises boron source gas, and described boron source gas is B ₂h ₆, boron source gas flow is 5sccm to 500sccm.

The manufacture method of 13. semiconductor device according to claim 1, is characterized in that, the material of described mask layer is silicon nitride.

The manufacture method of 14. semiconductor device according to claim 13, is characterized in that, adopts chemical vapor deposition method to form described mask layer.

The manufacture method of 15. semiconductor device according to claim 14, is characterized in that, the concrete technology parameter of described chemical vapor deposition method is: in reaction chamber, pass into NH ₃and silicon source gas, described silicon source gas is SiH ₄or SiH ₂cl ₂, wherein NH ₃flow is 5sccm to 1000sccm, and silicon source gas flow is 5sccm to 500sccm, and reaction chamber temperature is 300 degree to 800 degree, and reaction chamber pressure is that 0.05 holder to 50 is held in the palm.

The manufacture method of 16. semiconductor device according to claim 1, is characterized in that, the semiconductor device of formation is nmos pass transistor, PMOS transistor or CMOS transistor.