CN103730421A - CMOS forming method - Google Patents

CMOS forming method Download PDF

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CN103730421A
CN103730421A CN201210393612.2A CN201210393612A CN103730421A CN 103730421 A CN103730421 A CN 103730421A CN 201210393612 A CN201210393612 A CN 201210393612A CN 103730421 A CN103730421 A CN 103730421A
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region
pmos
cmos
layer
etching
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何有丰
金兰
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A CMOS forming method comprises the steps of providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; forming an oxide layer covering the gate structure and the semiconductor substrate and forming a nitride layer covering the oxide; forming a first blocking layer covering an NMOS region; etching the nitride layer and the oxide layer in a PMOS region to form a PMOS side wall; using the gate structure in the PMOS region and the PMOS side wall as masks and forming grooves in regions to form a source region and a leakage region in the semiconductor substrate in the PMOS region; removing the first blocking layer and filling silicon-germanium materials in the grooves in an epitaxy mode; forming a second blocking layer covering the PMOS region, etching a nitride layer and an oxide layer in an NMOS to form an NMOS side wall and removing the second blocking layer. In the CMOS forming method, leakage current does not exist between a source/leakage electrode and gate electrode.

Description

The formation method of CMOS
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the formation method of CMOS a kind of.
Background technology
MOS transistor, by applying voltage at grid, regulates and produces switching signal by the electric current of channel region.In existing process for fabrication of semiconductor device, in order to improve the performance of MOS transistor, conventionally adopt at the channel region of MOS transistor and introduce stress to improve carrier mobility.For PMOS transistor, can adopt embedded SiGe technology (Embedded SiGe Technology) to produce compression at transistorized channel region, and then improve carrier mobility.So-called embedded SiGe technology refers to embedding silicon germanium material in the region that need to form source region and drain region of Semiconductor substrate, utilizes the lattice mismatch between silicon and SiGe (SiGe) to produce compression to channel region.
Prior art provides the formation method of CMOS a kind of.Please refer to Fig. 1, for prior art adopts embedded SiGe technology, form the schematic flow sheet of CMOS, comprising:
Step S101, provides Semiconductor substrate, in described Semiconductor substrate, forms grid structure.
Step S102, silicon oxide layer and the silicon nitride layer of formation overlies gate structure and Semiconductor substrate, etch nitride layer and oxide skin(coating) form NMOS side wall and PMOS side wall successively.
Step S103, forms the extension selection layer (an Epitaxy SelectivitV Film) that covers Semiconductor substrate and grid structure.Described selective epitaxy layer is generally silica, and when follow-up use selective epitaxial process forms germanium-silicon layer, silicon germanium material is mainly being grown on silicon materials, and the less extension that is grown in is selected on layer.
Step S104, forms the barrier layer that covers territory, nmos area, and in the Semiconductor substrate of PMOS region, the region in source region to be formed and drain region forms groove, removes barrier layer.Described barrier layer is generally photoresist layer, for protect territory, nmos area to avoid damage in etching process.
Step S105, in described groove, extension forms germanium-silicon layer.Because described groove is positioned at the region in source region to be formed, PMOS region and drain region, and the remaining surface of described Semiconductor substrate is selected layer to cover by extension, and SiGe selective growth, in described groove, forms the PMOS with embedded silicon Germanium source/leakage.
S106, removes extension and selects layer.
The Chinese patent application that other formation methods about embedded silicon Germanium source/leakage PMOS can also be CN1870295 with reference to publication number.
But prior art forms the method for embedded silicon Germanium source/leakage CMOS, between source/drain and gate, there is leakage current.
Summary of the invention
The problem that the present invention solves is to have leakage current between source/drain and gate in embedded silicon Germanium source/leakage CMOS of forming of prior art.
For addressing the above problem, the invention provides the formation method of CMOS a kind of, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has PMOS region and territory, nmos area, between described PMOS region and territory, nmos area, has isolation structure; In described PMOS region and NOMS region, form grid structure; Form the oxide skin(coating) that covers described grid structure and Semiconductor substrate, form the nitride layer that covers described oxide skin(coating); Form the first barrier layer that covers territory, nmos area; The nitride layer in etching PMOS region and oxide skin(coating) form PMOS side wall; Take the grid structure in PMOS region and PMOS side wall as mask, in the Semiconductor substrate in described PMOS region, the region in source region to be formed and drain region forms groove; Remove described the first barrier layer, take the nitride layer in described PMOS side wall and covering territory, nmos area, as extension, select layer, in described groove, extension is filled silicon germanium material; Form the second barrier layer that covers PMOS region; The nitride layer in etching N MOS region and oxide skin(coating) form NMOS side wall, remove described the second barrier layer.
Optionally, the formation technique of described silicon germanium material is selective epitaxial.
Optionally, the parameter of described selective epitaxial process comprises: reacting gas comprises silicon source gas and germanium source gas, and described silicon source gas is SiH 4or SiH 2cl 2, flow is 1sccm～1000sccm; Described germanium source gas is GeH 4, flow is 1sccm～1000sccm; Reaction temperature is 500～800 degrees Celsius; Reaction pressure is 1～100Torr.
Optionally, the reacting gas of described selective epitaxial process also comprises HCl and H 2, the flow of described HCl is 1sccm～1000sccm, described H 2flow be 0.1slm～50slm.
Optionally, described groove is Sigma connected in star, and described Sigma connected in star has the tip of the protrusion that points to transistor channel region at the middle part of groove.
Optionally, the technique that forms described Sigma connected in star comprises:
First carry out plasma etching, the parameter of described plasma etching comprises: etching gas comprises HBr, O 2, He, Cl 2and NF 3, described HBr flow is 100～1000sccm, O 2flow is 2～20sccm, and He flow is 100～1000sccm, Cl 2flow is 2～200sccm, NF 3flow is 2～200sccm, and etching air pressure is 10～200mTorr, and bias voltage is 0～400V, and the time is 5～60 seconds;
Carry out wet etching, described wet-etching technology adopts TMAH(Tetramethylammonium hydroxide again) solution, the temperature of TMAH solution is 15～70 degrees Celsius, the time is 20～500 seconds.
Optionally, described isolation structure is fleet plough groove isolation structure.
Optionally, described grid structure comprises gate dielectric layer and is positioned at the gate electrode layer on gate dielectric layer.
Optionally, after forming described grid structure, be also included in the step of carrying out lightly-doped source leakage injection (LDD:Lightly Doped Drain) and halo (Halo Implant) doping in described Semiconductor substrate.
Optionally, the material of described oxide skin(coating) is silica, and the material of described nitride layer is silicon nitride.
Optionally, described the first barrier layer and the second barrier layer are photoresist layer.
Optionally, the width of described PMOS side wall is 5nm to 50nm.
Optionally, the width of described NMOS side wall is 5nm to 50nm.
Compared with prior art, the present invention has the following advantages:
The formation method of the CMOS that embodiments of the invention provide, take the grid structure in PMOS region and PMOS side wall as mask, in the Semiconductor substrate in described PMOS region, the region in source region to be formed and drain region forms groove, and in described groove, extension is filled silicon germanium material.Because the material of described PMOS side wall is silicon nitride, and described silicon nitride material covers territory, nmos area, and the selection window (Selectivity Window) of silicon nitride in the selective epitaxial process of silicon germanium material adopts silica extension to select layer larger than prior art, i.e. more difficult grown silicon germanium material on silicon nitride material, guaranteed in SiGe epitaxial process only grown silicon germanium material in described groove, can be at the grid structure region in PMOS region and territory, nmos area grown silicon germanium material.In the step of territory, follow-up formation source/drain region silicide, silicide only forms in territory, PMOS source/drain region, does not have the conductive channel between source/drain and gate, has prevented leakage current.
Further, in the formation method of the CMOS providing, form the first barrier layer that covers territory, nmos area at embodiments of the invention, the nitride layer in etching PMOS region and oxide skin(coating) form PMOS side wall; Form the second barrier layer that covers PMOS region, the nitride layer in etching N MOS region and oxide skin(coating) form NMOS side wall.Described PMOS side wall and NMOS side wall form by etching technics in different step, according to process requirements, can obtain by adjusting etching parameters PMOS side wall and the NMOS side wall of different in width, further can obtain by the PMOS side wall of different in width and NMOS side wall PMOS and the NMOS source/leakage of different in width, improve the device performance of CMOS.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the formation method of prior art CMOS;
Fig. 2 to Fig. 9 is the cross-sectional view of different preparatory phases in the CMOS formation method of the embodiment of the present invention.
Embodiment
From background technology, prior art forms the method for embedded silicon Germanium source/leakage CMOS, between PMOS source/drain and gate, has leakage current.
The present inventor forms the method for embedded silicon Germanium source/leakage CMOS by research prior art, find that prior art use silica is as extension selection layer (an Epitaxy Selectivity Film), the selection window (Selectivity Window) of silica is limited, still can be on selective epitaxy layer in the epitaxial process of silicon germanium material grown silicon germanium material, form the germanium-silicon layer in the grid structure region that covers PMOS region, be gill fungus type defect (Mushroom Defect), simultaneously also can be in territory, nmos area without the region growing silicon germanium material of epitaxial silicon germanium layer.Follow-uply when removing silica extension and select layer, owing to being coated with silicon germanium material on silicon oxide layer, increased removal difficulty, caused removing completely.And residual silicon germanium material forms in the step of territory, source/drain region silicide in follow-up CMOS preparation process, easily react with metal material and form silicide, as the conductive channel between source/drain and gate, cause leakage current.
On the silicon oxide substrate that the present inventor also forms in thermal oxidation respectively, the silicon oxide substrate that chemical vapour deposition (CVD) forms and silicon nitride substrate, adopt selective epitaxial process grown silicon germanium material, the edge of the silicon oxide substrate that discovery forms in thermal oxidation can grow SiGe, the surface of the silicon oxide substrate forming in chemical vapour deposition (CVD) can grow SiGe, and on silicon nitride substrate, does not grow SiGe.So the extension of silicon nitride during as SiGe selective epitaxial selects layer to have larger selection window.
Based on above research, the present inventor proposes the formation method of CMOS a kind of, comprising: Semiconductor substrate is provided, and described Semiconductor substrate has PMOS region and territory, nmos area, between described PMOS region and territory, nmos area, has isolation structure; In described PMOS region and NOMS region, form grid structure; Form the oxide skin(coating) that covers described grid structure and Semiconductor substrate, form the nitride layer that covers described oxide skin(coating); Form the first barrier layer that covers territory, nmos area; The nitride layer in etching PMOS region and oxide skin(coating) form PMOS side wall; Take the grid structure in PMOS region and PMOS side wall as mask, in the Semiconductor substrate in described PMOS region, the region in source region to be formed and drain region forms groove; Remove described the first barrier layer, take the nitride layer in described PMOS side wall and covering territory, nmos area, as extension, select layer, in described groove, extension is filled silicon germanium material; Form the second barrier layer that covers PMOS region; The nitride layer in etching N MOS region and oxide skin(coating) form NMOS side wall, remove described the second barrier layer.
Below in conjunction with accompanying drawing, describe specific embodiment in detail, above-mentioned object and advantage of the present invention will be clearer.It should be noted that, the object that these accompanying drawings are provided is to contribute to understand embodiments of the invention, and should not be construed as restriction improperly of the present invention.For the purpose of clearer, size shown in figure not drawn on scale, may make and amplify, dwindle or other changes.A lot of details in description below, have been set forth to fully understand the present invention.But the present invention can implement to be much different from other modes described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, and therefore the present invention is not subject to the restriction of following public specific embodiment.
Please refer to Fig. 2, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 has PMOS region and territory, nmos area, between described PMOS region and territory, nmos area, has isolation structure 201.
Described Semiconductor substrate 200 is for the workbench as subsequent technique.Described Semiconductor substrate 200 can be monocrystalline silicon or monocrystalline germanium; Described Semiconductor substrate 200 can be also SiGe, GaAs or silicon-on-insulator substrate (SOI substrate).In the present embodiment, described Semiconductor substrate 200 is monocrystalline silicon.Described Semiconductor substrate 200 has PMOS region and territory, nmos area, and described PMOS region has N-type well region, and territory, described nmos area has P type well region, between described PMOS region and territory, nmos area, by isolation structure 201, isolates.In the present embodiment, described isolation structure 201 is fleet plough groove isolation structure, and so that the active region in Semiconductor substrate 200 is isolated, the formation method of described fleet plough groove isolation structure can, with reference to existing technique, not repeat them here.
Please refer to Fig. 3, in described PMOS region and NOMS region, form grid structure 213, described grid structure 213 comprises gate dielectric layer 212 and is positioned at the gate electrode layer 211 on gate dielectric layer 212.
The material of described gate dielectric layer 212 is silica or high K(high-k) material, described hafnium comprises HfO 2, HfSiO, HfSiON, HfTaO, HfZrO, Al 2o 3and ZrO 2, the material of described gate electrode layer 211 is polysilicon or metal, described metal comprises Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and TaSiN.
In one embodiment, the formation method of described grid structure 213 is, at Semiconductor substrate 200 Film by Thermal Oxidation silicon oxide layers, at silicon oxide surface, use chemical gaseous phase depositing process to form polysilicon layer again, on polysilicon layer surface, form patterned photoresist layer, take patterned photoresist layer as mask etching polysilicon layer and silicon oxide layer, until expose Semiconductor substrate 200 surfaces, remove photoresist layer, form grid structure 213.
It should be noted that, conventionally forming after gate electrode layer, also can form hard mask layer on gate electrode layer surface, the material of described hard mask layer can be silicon nitride, and described hard mask layer plays the effect of etching stop layer and grill-protected electrode layer in follow-up technique.According to process conditions, if described gate electrode layer is polysilicon, described hard mask layer can be removed before the silicide contacts layer that forms grid structure; If described gate electrode layer is metal material, described hard mask layer is without removal.
Also it should be noted that, after forming described grid structure 213, be also included in the step of carrying out lightly-doped source leakage injection (LDD:Lightly Doped Drain) and halo doping (Halo Implant) in described Semiconductor substrate.Described LDD doping, by disperseing to point to along drain electrode pinch off region the highfield in LDD region, suppresses threshold voltage shift, reduces leakage current and alleviates thermoelectronic effect; Described Halo doping can suppress threshold value low pressure and reduce, and less leakage current also strengthens the ability of heatproof carrier.The technique of described formation LDD and Halo doping is well known to those skilled in the art, and does not repeat them here.
Please refer to Fig. 4, form the oxide skin(coating) (not shown) that covers described grid structure 213 and Semiconductor substrate 200, form the nitride layer 214 that covers described oxide skin(coating).
In one embodiment, the material of described oxide skin(coating) is silica, and formation technique is chemical vapour deposition (CVD); The material of described nitride layer 214 is silicon nitride, and formation technique is chemical vapour deposition (CVD).Described oxide skin(coating) and nitride layer are follow-up forms grid curb wall by etching, plays the effect of protection grid and isolation source/leakage and grid, and in addition, in the present invention, described nitride layer is selected layer as extension when follow-up epitaxial sige material.
Please refer to Fig. 5, form the first barrier layer 227 that covers territory, nmos area, the nitride layer 214 in etching PMOS region and oxide skin(coating) (not shown) form PMOS side wall.
In one embodiment, at Semiconductor substrate 200 surface-coated photoresist layers, through steps such as oven dry, exposure, developments, form the first barrier layer 227 that covers territory, nmos area.Take described the first barrier layer 227 as mask, nitride layer 214 and the oxide skin(coating) in etching PMOS region.The technique of etch nitride layer 214 is plasma etching, and etching parameters comprises: etching gas is CF 4(or CHF 3), O 2and He, described CF 4(or CHF 3) flow be 2～200sccm, described O 2flow is 2～500sccm, and described He flow is 10～1000sccm, and etching air pressure is 1～200mTorr, and bias voltage is 50～400V, and the time is 2～60 seconds.The technique of etching oxide layer is plasma etching, and etching parameters comprises: etching gas is CF 4, O 2and He, described CF 4flow be 2～200sccm, described O 2flow is 2～20sccm, and described He flow is 10～500sccm, and etching air pressure is 1～200mTorr, and bias voltage is 50～400V, and the time is 2～60 seconds.Because plasma etching has fine anisotropy, after etching completes, the nitride layer 214 and the oxide skin(coating) that are positioned at PMOS region Semiconductor substrate 200 surfaces and grid structure 213 surfaces are removed, and the nitride layer 214 and the oxide skin(coating) that are positioned at grid structure 213 both sides are retained, form PMOS side wall.The width of described PMOS side wall is 5nm to 50nm, can adjust according to the technological parameter adjustment of the deposit thickness of oxide skin(coating) and nitride layer 214 and etching the width of PMOS side wall.
Please refer to Fig. 6, take the grid structure 213 in PMOS region and PMOS side wall as mask, in the Semiconductor substrate 200 in described PMOS region, the region in source region to be formed and drain region forms groove 215.
In one embodiment, described groove 215 be shaped as Sigma shape, described Sigma connected in star has the tip of the protrusion that points to transistor channel region at the middle part of groove.Please refer to Fig. 6, Sigma connected in star has the tip of protrusion in the horizontal direction, follow-up in Sigma connected in star extension fill during silicon germanium material, silicon germanium material is filled full whole groove, the transistorized channel region of the more close PMOS of place, tip silicon germanium material protruding at described groove, will introduce larger compression at channel region.
The technique that forms described Sigma connected in star is, first carries out plasma etching, and the parameter of described plasma etching comprises: etching gas comprises HBr, O 2, He, Cl 2and NF 3, described HBr flow is 100～1000sccm, O 2flow is 2～20sccm, and He flow is 100～1000sccm, Cl 2flow is 2～200sccm, NF 3flow is 2～200sccm, and etching air pressure is 10～200mTorr, and bias voltage is 0～400V, and the time is 5～60 seconds; After plasma etching, carry out wet etching, described wet-etching technology adopts TMAH(Tetramethylammonium hydroxide) solution, the temperature of TMAH is 15～70 degrees Celsius, the time is 20～500 seconds.In other embodiments of the invention, described wet-etching technology can also adopt potassium hydroxide solution or ammonia spirit.
Please refer to Fig. 7, remove described the first barrier layer, take the nitride layer in described PMOS side wall and covering territory, nmos area, as extension, select layer, in described groove, extension is filled silicon germanium material, forms embedded silicon Germanium source/leakage 216.The formation technique of described silicon germanium material is selective epitaxial.
After the region in source region to be formed and drain region forms groove in the Semiconductor substrate 200 in described PMOS region, remove the first barrier layer that covers territory, nmos area, adopt selective epitaxial process to fill silicon germanium material in described groove.The parameter of described selective epitaxial process is: reacting gas comprises silicon source gas and germanium source gas, and described silicon source gas is SiH 4or SiH 2cl 2, flow is 1sccm～1000sccm; Described germanium source gas is GeH 4, flow is 1sccm～1000sccm; Reaction temperature is 500～800 degrees Celsius; Reaction pressure is 1～100Torr.
In another embodiment of the present invention, the parameter of described selective epitaxial process is: silicon source gas, described silicon source gas is SiH 4or SiH 2cl 2, flow is 1sccm～1000sccm; Germanium source gas, described germanium source gas is GeH 4, flow is 1sccm～1000sccm; HCl gas, flow is 1sccm～1000sccm; H 2gas, flow is 0.1slm～50slm; Reaction temperature is 500～800 degrees Celsius; Reaction pressure is 1～100Torr.
In described groove, fill silicon germanium material and form embedded silicon Germanium source/leakage 216, because the lattice constant of silicon germanium material is greater than the lattice constant of PMOS channel region silicon materials, embedded silicon Germanium source/leakage 216 can be introduced compression at the channel region of PMOS, improves the carrier mobility of PMOS.
Embodiments of the invention adopt the side wall nitride silicon of PMOS to select layer as the extension of selective epitaxial silicon germanium material, compared with prior art, without the extra silica extension that forms, select layer, have saved processing step.In addition, silicon nitride is compared with silica, in selective epitaxial silicon germanium material process, there is larger selection window, i.e. more difficult grown silicon germanium material on silicon nitride material, guaranteed in SiGe epitaxial process only grown silicon germanium material in described groove, can be at the grid structure in PMOS region and territory, nmos area grown silicon germanium material.In the step of territory, follow-up formation source/drain region silicide, silicide only forms in territory, PMOS source/drain region, does not have the conductive channel between source/drain and gate, has prevented leakage current.
Please refer to Fig. 8, form the second barrier layer 217 that covers PMOS region; The nitride layer 214 in etching N MOS region and oxide skin(coating) (not shown) form NMOS side wall.
In one embodiment, at Semiconductor substrate 200 surface-coated photoresist layers, through steps such as oven dry, exposure, developments, form the second barrier layer 217 that covers PMOS region.Take described the second barrier layer 217 as mask, nitride layer 214 and the oxide skin(coating) in etching N MOS region.The technique of etch nitride layer 214 is plasma etching, and etching parameters comprises: etching gas is CF 4(or CHF 3), O 2and He, described CF 4(or CHF 3) flow be 2～200sccm, described O 2flow is 2～500sccm, and described He flow is 10～1000sccm, and etching air pressure is 1～200mTorr, and bias voltage is 50～400V, and the time is 2～60 seconds.The technique of etching oxide layer is plasma etching, and etching parameters comprises: etching gas is CF 4, O 2and He, described CF 4flow be 2～200sccm, described O 2flow is 2～20sccm, and described He flow is 10～500sccm, and etching air pressure is 1～200mTorr, and bias voltage is 50～400V, and the time is 2～60 seconds.Because plasma etching has good anisotropy, after etching completes, the nitride layer 214 and the oxide skin(coating) that are positioned at territory, nmos area Semiconductor substrate 200 surfaces and grid structure 213 surfaces are removed, and the nitride layer 214 and the oxide skin(coating) that are positioned at grid structure 213 both sides are retained, form NMOS side wall.The width of described NMOS side wall is 5nm to 50nm.
It should be noted that, in an embodiment of the present invention, NMOS side wall and PMOS side wall form by etching technics in different step, can be by controlling etching process, obtain NMOS side wall and the PMOS side wall of different in width, further can obtain by the PMOS side wall of different in width and NMOS side wall PMOS and the NMOS source/leakage of different in width, meet the requirement of different process.
Please refer to Fig. 9, remove described the second barrier layer.
In the follow-up manufacture craft of CMOS, need to carry out the injection in the territory, source/drain region of NMOS and PMOS, the formation of territory, source/drain region silicide, also can form the interlayer dielectric layer (not shown) and the conductive plunger (not shown) that cover Semiconductor substrate 200, grid structure 213 and side wall, to form metal interconnect structure.Above-mentioned process can, with reference to existing technique, not repeat them here.
In sum, compared with prior art, the present invention has the following advantages:
The formation method of the CMOS that embodiments of the invention provide, take the grid structure in PMOS region and PMOS side wall as mask, in the Semiconductor substrate in described PMOS region, the region in source region to be formed and drain region forms groove, in described groove, fills silicon germanium material.Because the material of described side wall is silicon nitride, and silicon nitride selection window (Selectivity Window) in the selective epitaxial process of silicon germanium material selects layer larger than the silica extension of prior art, i.e. more difficult grown silicon germanium material on silicon nitride material, guaranteed in SiGe epitaxial process only grown silicon germanium material in described groove, can be at the grid structure region in PMOS region and territory, nmos area grown silicon germanium material.In the step of territory, follow-up formation source/drain region silicide, silicide only forms in territory, PMOS source/drain region, does not have the conductive channel between source/drain and gate, has prevented leakage current.
In the formation method of the CMOS providing at embodiments of the invention, form the first barrier layer that covers territory, nmos area, the nitride layer in etching PMOS region and oxide skin(coating) form PMOS side wall; Form the second barrier layer that covers PMOS region, the nitride layer in etching N MOS region and oxide skin(coating) form NMOS side wall.Described PMOS side wall and NMOS side wall form by etching technics in different step, according to process requirements, can obtain by adjusting etching parameters PMOS side wall and the NMOS side wall of different in width, further can obtain by the PMOS side wall of different in width and NMOS side wall PMOS and the NMOS source/leakage of different in width, improve transistor performance.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (13)

1. a formation method of CMOS, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has PMOS region and territory, nmos area, between described PMOS region and territory, nmos area, has isolation structure;
In described PMOS region and NOMS region, form grid structure;
Form the oxide skin(coating) that covers described grid structure and Semiconductor substrate, form the nitride layer that covers described oxide skin(coating);
Form the first barrier layer that covers territory, nmos area;
The nitride layer in etching PMOS region and oxide skin(coating) form PMOS side wall;
Take the grid structure in PMOS region and PMOS side wall as mask, in the Semiconductor substrate in described PMOS region, the region in source region to be formed and drain region forms groove;
Remove described the first barrier layer, take the nitride layer in described PMOS side wall and covering territory, nmos area, as extension, select layer, in described groove, extension is filled silicon germanium material;
Form the second barrier layer that covers PMOS region;
The nitride layer in etching N MOS region and oxide skin(coating) form NMOS side wall, remove described the second barrier layer.
2. the formation method of CMOS as claimed in claim 1, is characterized in that, the formation technique of described silicon germanium material is selective epitaxial.
3. the formation method of CMOS as claimed in claim 2, is characterized in that, the parameter of described selective epitaxial process comprises: reacting gas comprises silicon source gas and germanium source gas, and described silicon source gas is SiH 4or SiH 2cl 2, flow is 1sccm～1000sccm; Described germanium source gas is GeH 4, flow is 1sccm～1000sccm; Reaction temperature is 500～800 degrees Celsius; Reaction pressure is 1～100Torr.
4. the formation method of CMOS as claimed in claim 3, is characterized in that, the reacting gas of described selective epitaxial process also comprises HCl and H 2, the flow of described HCl is 1sccm～1000sccm, described H 2flow be 0.1slm～50slm.
5. the formation method of CMOS as claimed in claim 1, is characterized in that, described groove is Sigma connected in star, and described Sigma connected in star has the tip of the protrusion that points to transistor channel region at the middle part of groove.
6. the formation method of CMOS as claimed in claim 5, is characterized in that, the technique that forms described Sigma connected in star comprises:
First carry out plasma etching, the parameter of described plasma etching comprises: etching gas comprises HBr, O 2, He, Cl 2and NF 3, described HBr flow is 100～1000sccm, O 2flow is 2～20sccm, and He flow is 100～1000sccm, Cl 2flow is 2～200sccm, NF 3flow is 2～200sccm, and etching air pressure is 10～200mTorr, and bias voltage is 0～400V, and the time is 5～60 seconds;
Carry out wet etching, described wet-etching technology adopts TMAH solution again, and the temperature of TMAH solution is 15～70 degrees Celsius, and the time is 20～500 seconds.
7. the formation method of CMOS as claimed in claim 1, is characterized in that, described isolation structure is fleet plough groove isolation structure.
8. the formation method of CMOS as claimed in claim 1, is characterized in that, described grid structure comprises gate dielectric layer and is positioned at the gate electrode layer on gate dielectric layer.
9. the formation method of CMOS as claimed in claim 1, is characterized in that, after forming described grid structure, is also included in the step of carrying out lightly-doped source leakage injection and halo doping in described Semiconductor substrate.
10. the formation method of CMOS as claimed in claim 1, is characterized in that, the material of described oxide skin(coating) is silica, and the material of described nitride layer is silicon nitride.
The formation method of 11. CMOS as claimed in claim 1, is characterized in that, described the first barrier layer and the second barrier layer are photoresist layer.
The formation method of 12. CMOS as claimed in claim 1, is characterized in that, the width of described PMOS side wall is 5nm to 50nm.
The formation method of 13. CMOS as claimed in claim 1, is characterized in that, the width of described NMOS side wall is 5nm to 50nm.
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Application publication date: 20140416