CN109390367A - Pixel circuit and its manufacturing method - Google Patents
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- CN109390367A CN109390367A CN201811490566.1A CN201811490566A CN109390367A CN 109390367 A CN109390367 A CN 109390367A CN 201811490566 A CN201811490566 A CN 201811490566A CN 109390367 A CN109390367 A CN 109390367A
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- 239000004065 semiconductor Substances 0.000 claims description 42
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- 229910052710 silicon Inorganic materials 0.000 claims description 21
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- 229920000140 heteropolymer Polymers 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
This disclosure relates to pixel circuit and its manufacturing method.A kind of pixel circuit, comprising: floating node, for storing optical charge；Transistor；Capacitor is electrically connected to the floating node by the coupled in parallel；And separator, for keeping the device in the pixel circuit electrically isolated from one, wherein the transistor and the capacitor are all located on the separator.
Description
Technical field
This disclosure relates to pixel circuit and its manufacturing method.
Background technique
Cmos image sensor is a kind of typical solid state image sensor.Cmos image sensor is usually same by being integrated in
Pixel array, line driver, row driver, converter on one piece of silicon wafer etc. are constituted.
Summary of the invention
According to one aspect of the disclosure, a kind of pixel circuit is provided, comprising: floating node, for storing optical charge；
Transistor；Capacitor is electrically connected to the floating node by the coupled in parallel；And separator, it is described for making
Device in pixel circuit is electrically isolated from one, wherein the transistor and the capacitor are all located on the separator.
According in some embodiments of the present disclosure, the separator is shallow trench isolation.
According in some embodiments of the present disclosure, the capacitor includes first electrode, second electrode and is located at the
Dielectric material between one electrode and second electrode, wherein the first electrode is adjacent with the surface of the separator.
According in some embodiments of the present disclosure, the first electrode is made of semiconductor material.
According in some embodiments of the present disclosure, the semiconductor material is silicon or germanium.
According in some embodiments of the present disclosure, the semiconductor material of the first electrode is doping, the crystal
Pipe includes channel, and the doping type of the channel is opposite with the doping type of the first electrode.
According in some embodiments of the present disclosure, the transistor further includes control electrode, third electrode and the 4th electrode,
Wherein according to the voltage of the control electrode, the third electrode is electrically connected to the 4th electrode via the channel, described
Third electrode is electrically connected with the first electrode.
According in some embodiments of the present disclosure, the third electrode is identical as the material of the first electrode.
According in some embodiments of the present disclosure, the 4th electrode is electrically connected to the floating node.
According in some embodiments of the present disclosure, the floating node is adjacent with the separator, the transistor
4th electrode is directly contacted with the floating node.
According in some embodiments of the present disclosure, the dielectric material includes oxide, nitride, nitrogen oxides.
According in some embodiments of the present disclosure, the dielectric material includes silica, silicon nitride, silicon oxynitride.
According in some embodiments of the present disclosure, each pixel in the pixel circuit includes multiple separators, institute
Stating has at least one of the capacitor and transistor at least two separators in multiple separators.
A kind of method manufacturing pixel circuit another aspect of the present disclosure provides, comprising: substrate, institute are provided
State the floating node being formed in substrate for storing optical charge；Separator is formed on the substrate, and the separator is used for
Keep the device in the pixel circuit electrically isolated from one；And transistor and capacitor are formed on the separator, so that institute
It states capacitor and the floating node is electrically connected to by the coupled in parallel.
According in some embodiments of the present disclosure, the separator is shallow trench isolation.
It include: using semiconductor material described in the step of according to transistor is formed in some embodiments of the present disclosure
Deposited semiconductor material on separator；The first part of the semiconductor material is doped, the ditch of the transistor is formed
Road, wherein the doping type of the channel is the first doping type；The first dielectric material is deposited on the channel, as grid
Insulating layer；The first conductive material is deposited on the gate insulating layer, as control electrode；To the remainder of the semiconductor material
Divide and is doped, so that the doping type of the remainder is second doping type different from first doping type,
To form the third electrode and the 4th electrode of the transistor.
The step of according in some embodiments of the present disclosure, forming capacitor include: with the semiconductor material not
The second part of first part is same as first electrode, and be sequentially depositing on the first electrode the second dielectric material and
Second conductive material, wherein second electrode of second conductive material as the capacitor.
According in some embodiments of the present disclosure, the semiconductor material is silicon or germanium.
According in some embodiments of the present disclosure, first dielectric material and second dielectric material are oxidation
Object, nitride or nitrogen oxides.
According in some embodiments of the present disclosure, first dielectric material and second dielectric material are oxidation
Silicon, silicon nitride or silicon oxynitride.
According in some embodiments of the present disclosure, the floating node is adjacent with the groove, and the of the transistor
Four electrodes directly contact the floating node.
According in some embodiments of the present disclosure, each pixel in the pixel circuit includes multiple separators, institute
Stating has at least one of the capacitor and transistor at least two separators in multiple separators.
According to the another aspect of the disclosure, a kind of cmos image sensor is provided, including
Above-mentioned pixel circuit according to an embodiment of the present disclosure.
By the detailed description referring to the drawings to the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become more apparent from.
Detailed description of the invention
The attached drawing for constituting part of specification describes embodiment of the disclosure, and together with the description for solving
Release the principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description referring to attached drawing, in which:
Fig. 1 shows the schematic diagram of the pixel circuit of cmos image sensor.
Fig. 2 shows the schematic diagrames of the pixel circuit of cmos image sensor according to an embodiment of the present disclosure.
Fig. 3 shows the flow chart for manufacturing pixel circuit in accordance with an embodiment of the present disclosure.
Fig. 4 shows the sectional view of pixel circuit according to an embodiment of the present disclosure.
Fig. 5 A- Fig. 5 L shows the schematic diagram for manufacturing the process of pixel circuit according to an embodiment of the present disclosure.
Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiments described below
It indicates same section or part with the same function, and omits its repeated explanation.In some cases, using similar mark
Number and letter indicate similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes
Position, size and range etc..Therefore, the disclosure is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
It is described in detail the various exemplary embodiments of the disclosure below with reference to accompanying drawings.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the disclosure
And its application or any restrictions used.That is, structure and method herein is to show in an exemplary fashion, for
The different embodiments of structures and methods in the bright disclosure.It will be understood by those skilled in the art, however, that they be merely illustrative can
Exemplary approach with the disclosure for being used to implement, rather than mode exhausted.In addition, attached drawing is not necessarily drawn to scale, it is some
Feature may be amplified to show the details of specific component.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
Fig. 1 shows a kind of schematic diagram of the pixel circuit of typical cmos image sensor.As shown in Figure 1, each picture
Element includes 4 transistors Rx, Tx, Sx and Rs, photodiode PD and floating node FD.
In general, the collection and transmitting of a photosignal can be completed by following steps:
(1) transistor Rx and Tx conducting, carries out electric discharge pretreatment to photodiode PD；
(2) transistor Rx and Tx cut-off, photodiode PD collect optical signal and generate photoelectron by photoelectric effect；
(3) transistor Rx is connected, and floating node FD is made to discharge residual charge；
(4) transistor Rx cut-off and transistor Tx conducting, are transferred to the photoelectron generated in photodiode PD floating
In dynamic node FD；And
(5) voltage is converted the charge to by transistor Sx to amplify, and selectively exported by transistor Rs.
In above-mentioned pixel circuit, the capacitor of floating node FD determines the conversion gain of the pixel circuit, to determine
The sensitivity of pixel.The conversion gain of pixel circuit is defined as the voltage of floating node FD and the ratio of the charge stored thereon
Value.In the image sensor, in order to detect low light signals, it is desirable that conversion gain is higher, therefore desirable for the capacitor energy of floating node
It is lower.But in strong light situation, if floating node FD has lower capacitor, the dynamic range of pixel can be made to be limited
System.Therefore, it is necessary to be weighed between dynamic range and the sensitivity of pixel, capacitor appropriate is selected for floating node FD
Value, to make the sensitivity of dynamic range and pixel that can be received.
Fig. 2 shows the schematic diagrames of the pixel circuit of cmos image sensor according to an embodiment of the present disclosure.
Compared with pixel circuit shown in FIG. 1, capacitor C and transistor Tx1 are increased in the pixel circuit in Fig. 2.Its
In, capacitor C is electrically connected by transistor Tx1 with floating node FD in parallel.When being shot under strong light, need compared with
Big dynamic range.At this point, transistor Tx1 is connected, so that capacitor C is in parallel with floating node FD, total capacitance increases.In this way,
Floating node FD and capacitor C can receive more photoelectrons from photodiode PD, realize bigger dynamic range.When
When shooting under dim light, higher sensitivity is needed.At this point, transistor Tx1 ends, so that capacitor C and floating node FD is disconnected
Connection.In this way, only having floating node FD to receive the photoelectron from photodiode in pixel circuit.The capacitor of floating node FD
Total capacitance when obviously smaller than capacitor C is in parallel with floating node FD.Therefore, the sensitivity of pixel is improved.
Fig. 4 shows the sectional view of pixel circuit according to an embodiment of the present disclosure.
As shown in figure 4, having in substrate 401 for receiving and storing the floating node 401 of optical charge and for making picture
Each device in plain circuit shallow trench isolation (Shallow Trench Isolation, STI) 402 electrically isolated from one is (i.e.
Separator).It is provided with capacitor and transistor in shallow trench isolation 402, which can be by coupled in parallel to floating
Dynamic node 401.
Wherein, capacitor include top crown (i.e. first electrode) 403, dielectric layer (i.e. the second dielectric material) 404 and under
Pole plate (i.e. second electrode) 405.In one embodiment according to the disclosure, top crown 403 is made of polysilicon, dielectric layer
404 are made of silica, and bottom crown 405 is made of the polysilicon that n is adulterated, and top crown 403 is grounded.The source electrode of transistor
412 are made with 410 (i.e. third pole and quadrupoles) of drain electrode of the polysilicon that n is adulterated, the polysilicon system that channel region 409 is adulterated by p
At gate insulating layer (i.e. the first dielectric material) 408 is made of silica, and grid 406 is made of polysilicon, and side wall 407 is by oxygen
SiClx is made.
In addition, in the embodiment shown in fig. 4, because the bottom crown 405 of capacitor and the source electrode 412 of transistor are by identical
Material constitute, so they can be integrally formed by the material.In other embodiments, the bottom crown 405 and crystalline substance of capacitor
The source electrode 412 of body pipe can be made of different materials, can directly be contacted between them, can also be for example, by metal line
Etc. other ways electrical connection.
In addition, in the embodiment shown in fig. 4, drain electrode 410 is directly contacted with floating node 401.According to the disclosure
In another embodiment, drain electrode 410 can be electrically connected to floating node 401 for example, by other ways such as metal lines.
It should be appreciated that above-described embodiment is the material and structure of schematical illustrated capacitor and transistor.In this public affairs
Under the introduction and enlightenment opened, all parts of capacitor and transistor can be manufactured using other suitable materials.For example, electric
The dielectric layer 404 and gate insulating layer 408 of container can be (all using any dielectric material appropriate, such as oxide, nitride
Such as silicon nitride), nitrogen oxides (such as silicon oxynitride).In addition, according in some embodiments of the present disclosure, capacitor it is upper
One or two in pole plate 403 and bottom crown 405 can be made of metal, such as copper, silver, gold, aluminium etc..The grid of transistor
406 can be made of metal, and form so-called high k (dielectric constant) metal gate, and correspondingly, gate insulating layer 408 is situated between using high k
Electric material, such as a series of materials based on element hafnium, such as hafnium oxide (HfO2), hafnium silicate/hafnium silicon oxygen nitrogen chemical combination
Object (HfSiO/HfSiON) etc..
Fig. 3 shows the flow chart for manufacturing pixel circuit in accordance with an embodiment of the present disclosure.Fig. 5 A- Fig. 5 L shows manufacture root
According to the schematic diagram of the process of the pixel circuit of embodiment of the disclosure.
According to some embodiments of the present disclosure, manufacture pixel circuit the following steps are included:
Substrate is provided, the floating node (step 301) for storing optical charge is formed in the substrate；
The groove for being filled with insulating materials is formed on the substrate, and the groove is used to make the device in the pixel circuit
Part (step 302) electrically isolated from one；And
Transistor and capacitor are formed on the groove, so that the capacitor is by the transistor with side in parallel
Formula is electrically connected to the floating node (step 303).
The process of manufacture pixel circuit is described in detail below in conjunction with Fig. 5 A- Fig. 5 L.
Firstly, providing substrate 401.There is floating node 411 in substrate 401.In one embodiment according to the disclosure
In, substrate 401 can be the semiconductor base such as silicon or germanium.Floating node 411 can store (not to be shown by photodiode
The optical charge generated out).For example, floating node can be for example, by substrate in the case that substrate 401 is P-type silicon substrate
A region on 401 carries out N-type heavy doping (N+ doping) and obtains.
Then, groove 402 is formed in substrate 401.Groove 402 can make each in the pixel circuit in substrate 401
Device is electrically isolated from one.For this purpose, dielectric is normally filled in groove 402.Implement according to one of the disclosure
In example, as shown in Figure 5A, groove 402 can be such as shallow trench isolation (STI), fill silica in groove 402.
Finally, transistor and capacitor are formed on groove 402, so that capacitor is electric in parallel by transistor
It is connected to floating node 411.The manufacturing process of transistor and capacitor is described more fully below.
As shown in Figure 5 B, the dielectric (such as silica) in groove 402 is performed etching, to remove certain thickness
Dielectric.Specifically, can coat a layer photoresist in substrate 401, by exposing, developing etc., processing steps are formed
Patterned photoresist exposure mask 501.Photoresist exposure mask 501 exposes groove 402, the other positions of substrate (such as floating node
411) all it is photo-etched the covering of glue exposure mask 501.Then such as dry etching is carried out to substrate 401, to remove one in groove 402
SI semi-insulation medium.Groove 402 be STI and in the case that insulating materials is silica, such as dry etching can be used,
Utilize such as heteropolymer gas CH2F2、CF4、NF3Equal gases carry out plasma etching to the silica in groove 402.Such as
Shown in Fig. 5 C, after plasma etching, the insulating materials of predetermined thickness is removed.
Then, as shown in Figure 5 D, under the protection of photoresist exposure mask 501, layer of semiconductor 502 is deposited on groove 402.
In one embodiment according to the disclosure, which is the semiconductor materials such as silicon or germanium.Following description is with silicon
Example, still, this field, which should be appreciated that, can also use other suitable semiconductor materials.In addition, the example shown in Fig. 5 D
In, the upper surface of semiconductor layer 502 and the upper surface of floating node 411 are substantially flush, but this not necessarily condition.Actually answering
In, the upper surface of semiconductor 502 can be higher or lower than the upper surface of floating node 411.
Next, removal photoresist exposure mask 501, and form photoresist exposure mask 503.As shown in fig. 5e, photoresist exposure mask
503 are exposed a part of region of semiconductor layer 502.Then, the region is doped for example, by ion implanting, example
It such as, can be by mixing N-type impurity (such as phosphorus, arsenic) or p type impurity (such as boron, indium) to the region.As will be described later
, the region is by the channel region 409 as transistor.
Next, as illustrated in figure 5f, forming gate insulating layer 408 on channel region 409.Gate insulating layer 408 can be
Such as the dielectric materials such as silica, silicon oxynitride, silicon nitride.In the case where transistor uses metal gates, also can be used
Such as Si3N4、Al2O3、HfO2、La2O3、Ta2O5、TiO2、Y2O3、ZrO2, the high K mediums such as ZrSiO.According to one of the disclosure
In embodiment, gate insulating layer 408 can be formed using chemical vapour deposition technique or atomic layer deposition method.
Next, as depicted in fig. 5g, forming grid 406 on gate insulating layer.Oxidation is used in gate insulating layer 408
It, can be for example, by the side such as chemical vapor deposition or atomic layer deposition in the case where the dielectric materials such as silicon, silicon oxynitride, silicon nitride
Formula deposit polycrystalline silicon is as grid 406.Metal gates can be used using in the case where high K medium in gate insulating layer 408.
For example, for N-type transistor grid can be made using the lower metal material of the work functions such as Nb, Al, Ta, Zr, V, Ti.
For P-type transistor, Re, Ir, Pt, RuO can be used2Etc. work functions higher metal materials make grid.
It should be appreciated that during making transistor, the technique that metal gate can be used preposition, the i.e. grid of high-g value
Pole insulating layer and metal gates are all formed before source electrode and drain electrode, after this requires high-g value and metal gates that can withstand
Continuous high-temperature activation treatment process.It, can also be in the high-temperature activation of source electrode and drain electrode in the other embodiments according to the disclosure
Metal gates, the i.e. technique of metal gates postposition are formed after processing.The disclosure is without limitation, and those skilled in the art can
To use metal gates preposition according to actual needs or the technique of postposition.
Next, forming side wall 407.Side wall is for limiting lightly doped drain (Light Doping Drain, LDD) knot
The self-aligned technology of (not shown) and deep source/drain knot width.It will be appreciated by those skilled in the art that lightly doped drain LDD is 1 μm
The following common protectiveness technique of technique.It can be for example, by arsenic or BF2Equal dopant materials inject drain region, form shallow junction.
Shallow junction helps to reduce the channel leakage stream effect between source and drain.The disclosure is just not described in detail the forming process of LDD.
As illustrated in fig. 5h, in order to form side wall 407, one layer of insulating materials 504, such as silicon nitride or oxide are deposited first
(such as silica).It, can be for example, by chemical vapor deposition or atomic layer deposition according in some embodiments of the present disclosure
Long-pending mode forms insulation material layer 504.
Then, insulation material layer 504 is performed etching using such as dry etch process, to form side wall 407, is such as schemed
Shown in 5I.
Next, as indicated at figure 5j, processing is doped to semiconductor layer 502 for example, by ion implanting, to be formed
The source electrode and drain electrode of transistor.The doping type of semiconductor layer 502 is opposite with the doping type of channel region 409.For example, if ditch
Road area 409 is p-type doping, then carries out n-type doping to semiconductor layer 502, obtain N-type transistor；If channel region 409 is N-type
Doping then carries out p-type doping to semiconductor layer 502, obtains P-type transistor.By above-mentioned doping treatment, transistor is formd
Source electrode 412 and drain electrode 410.
In the above description, transistor is illustrated as the field effect transistor with side wall and LDD knot.Art technology
Personnel should be appreciated that transistor can also be using any other structure, as long as can be selectively by capacitor with parallel connection
Mode is electrically connected to floating node.
In addition, as indicated at figure 5j, handling by above-mentioned ion implanting, it is also formed simultaneously the bottom crown 405 of capacitor.?
That is the bottom crown 405 of capacitor can be formed by semiconductor material.It, can also in the other embodiments according to the disclosure
To independently form the bottom crown 405 of capacitor.Such as by modes such as chemical vapor deposition or atomic layer depositions in 402 table of groove
Predetermined position on face forms one layer of metal, using the metal layer as the bottom crown 405 of capacitor.The metal layer can direct shape
At the surface of the insulating materials in groove 402, can also be formed on semiconductor layer 502.In addition it is also possible to using other conjunctions
Suitable conductive material manufactures bottom crown 405, and the disclosure is without limitation.
The dielectric layer and top crown of capacitor will be initially formed below.
As it can be seen from figure 5k, under such as protection of photoresist exposure mask 504, for example, by chemical vapor deposition or atomic layer deposition
The processing such as product forms dielectric layer 404 on bottom crown 405.Dielectric layer 404 can use any dielectric material appropriate, such as oxygen
Compound (such as silica), nitride (such as silicon nitride), nitrogen oxides (such as silicon oxynitride) etc..
Then, as shown in fig. 5l, still under the protection of photoresist exposure mask 504, top crown is formed on dielectric layer 404
403.Top crown 403 can be made of metal or semiconductor material (such as silicon or germanium).For example, chemical vapor deposition can be passed through
Or atomic layer deposition forms top crown 403.
Removal photoresist exposure mask 504 is simultaneously grounded top crown 403, to obtain crystal as shown in Figure 4 on groove 402
Pipe and capacitor.
In in accordance with an embodiment of the present disclosure, transistor is formed on a part of region of semiconductor layer 502, in semiconductor
Capacitor will be formed on another part region of layer 502.Due to semiconductor layer 502 be it is integrated, so the lower pole of capacitor
Plate 405 is electrically connected to the source electrode 412 of transistor.As indicated at figure 5j, the case where semiconductor layer 502 and floating node contact
Under, being electrically connected between the drain electrode of transistor and floating node 411 is also realized by above-mentioned ion implanting simultaneously.
Certainly, it will be appreciated by those skilled in the art that semiconductor layer 502 can be formed on 402 surface of groove it is multiple not
In continuous region.In such a case, it is possible to be respectively formed capacitor and transistor in different regions, then pass through gold
Belong to cloth bundle of lines capacitor and the electrical connection of corresponding transistor.
In addition, semiconductor layer 502 can also be not directly contacted with floating node 411, but it is electrically connected to by metal line
Floating node 411.In such a case, it is possible to omit processing step shown in Fig. 5 B.I.e., it is not necessary to exhausted in etching groove 402
Edge medium directly can deposit the semiconductor materials such as silicon or germanium on the surface of groove 402.
In addition, each pixel circuit can have multiple each for being isolated according in some embodiments of the present disclosure
The separator of device can form transistor and capacitor on part or all of separator of these separators.For example,
In one exemplary embodiment, it is simply formed with capacitor in a shallow trench isolation, and in another shallow trench isolation
It is simply formed with transistor.
In another exemplary embodiment, it is formed with capacitor in some shallow trench isolations, in another shallow ridges
Transistor is formed in slot isolation.Multiple capacitors in shallow trench isolation are connected after being connected in parallel with each other by coupled in parallel
It is connected to floating node.In this way, the quantity for being parallel to the capacitor of floating node can be further increased.Under some intense light conditions
When being shot, even if the capacitor in single shallow trench isolation is in parallel with floating node, may still it not be able to satisfy to dynamic
The demand of state range.In this case, by that can further increase dynamic the capacitor parallel connection in multiple shallow trench isolations
State range.
In addition, the pixel circuit of each pixel has multiple separators, each in one embodiment according to the disclosure
All there is capacitor and transistor on separator.In this way, the Lighting information that processing circuit can be measured according to such as light measuring circuit,
One or more capacitors are selected to be connected to floating node by corresponding coupled in parallel.In this embodiment, floating node
And the total capacitance of capacitor connected in parallel can change between multiple numerical value.To realize high dynamic range and highly sensitive
Degree.
In addition, in one embodiment according to the disclosure, can be arranged for the pixel circuit of different pixels different total
Capacitor.Specifically, can for example be individually for the setting of each pixel: whether capacitor is parallel-connected to floating node, and/or
Which capacitor is parallel-connected to floating node, to preferably take into account dynamic range and sensitivity.For example, working as imaging sensor
A part by strong illumination, and when another part is in low light environment, if floating node (i.e. floating node is used only
Disconnected with capacitor), preferably low light environment can be imaged, but dynamic range is smaller, it cannot be to by strong illumination
Part accurate imaging.If floating node is in parallel with capacitor, may can satisfy by the accurate of the part of strong illumination
Imaging, but sensitivity is too low, causes low light environment cannot be imaged.By being separately provided in the pixel circuit of each pixel
Whether floating node is in parallel with corresponding capacitor, can solve the problem.For in imaging sensor by strong illumination
Pixel can make floating node in parallel with capacitor, realize big dynamic range.It, can for the pixel in low light environment
To be that floating node is disconnected with capacitor, to realize high sensitivity.
In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language be in appropriate circumstances it is interchangeable so that embodiment of the disclosure described herein, for example, can in this institute
It is operated in those of description show or other other different orientations of orientation.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other implementations in any implementation of this exemplary description
It is preferred or advantageous.Moreover, the disclosure is not by above-mentioned technical field, background technique, summary of the invention or specific embodiment
Given in go out theory that is any stated or being implied limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Any small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual implementation with perfect or ideal situation
Between difference.
In addition, the description of front may be referred to and be " connected " or " coupling " element together or node or feature.Such as
It is used herein, unless explicitly stated otherwise, " connection " mean an element/node/feature and another element/node/
Feature is being directly connected (or direct communication) electrically, mechanically, in logic or in other ways.Similarly, unless separately
It clearly states outside, " coupling " means that an element/node/feature can be with another element/node/feature with direct or indirect
Mode link mechanically, electrically, in logic or in other ways to allow to interact, even if the two features may
It is not directly connected to be also such.That is, " coupling " is intended to encompass the direct connection and indirectly of element or other feature
Connection, including the use of the connection of one or more intermediary elements.
In addition, just to the purpose of reference, can with the similar terms such as " first " used herein, " second ", and
And it thus is not intended to limit.For example, unless clearly indicated by the context, be otherwise related to structure or element word " first ", "
Two " do not imply order or sequence with other such digital words.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or their combination.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..
It should be appreciated by those skilled in the art that the boundary between aforesaid operations is merely illustrative.Multiple operations
It can be combined into single operation, single operation can be distributed in additional operation, and operating can at least portion in time
Divide and overlappingly executes.Moreover, alternative embodiment may include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are modified, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
Embodiment of the disclosure can also include following technical scheme:
1, a kind of pixel circuit characterized by comprising
Floating node, for storing optical charge；
Transistor；
Capacitor is electrically connected to the floating node by the coupled in parallel；And
Separator, for keeping the device in the pixel circuit electrically isolated from one,
Wherein, the transistor and the capacitor are all located on the separator.
2, the pixel circuit according to 1, which is characterized in that the separator is shallow trench isolation.
3. the pixel circuit according to 1, which is characterized in that the capacitor include first electrode, second electrode and
Dielectric material between first electrode and second electrode, wherein the first electrode is adjacent with the surface of the separator.
4. the pixel circuit according to 3, which is characterized in that the first electrode is made of semiconductor material.
5. the pixel circuit according to 4, which is characterized in that the semiconductor material is silicon or germanium.
6. according to pixel circuit described in 4 or 5, which is characterized in that the semiconductor material of the first electrode is doping,
The transistor includes channel, and the doping type of the channel is opposite with the doping type of the first electrode.
7. the pixel circuit according to 6, which is characterized in that the transistor further includes control electrode, third electrode and
Four electrodes, wherein the third electrode is electrically connected to the 4th electricity via the channel according to the voltage of the control electrode
Pole, the third electrode are electrically connected with the first electrode.
8. the pixel circuit according to 7, which is characterized in that the material phase of the third electrode and the first electrode
Together.
9. the pixel circuit according to 7, which is characterized in that the 4th electrode is electrically connected to the floating node.
10. the pixel circuit according to 7, which is characterized in that the floating node is adjacent with the separator, the crystalline substance
4th electrode of body pipe is directly contacted with the floating node.
11. the pixel circuit according to 3, which is characterized in that the dielectric material includes oxide, nitride, nitrogen oxygen
Compound.
12. the pixel circuit according to 11, which is characterized in that the dielectric material includes silica, silicon nitride, nitrogen oxygen
SiClx.
13. the pixel circuit according to any one of 1-12, which is characterized in that each pixel in the pixel circuit
Including multiple separators, have in the capacitor and transistor extremely at least two separators in the multiple separator
Few one kind.
14. a kind of method for manufacturing pixel circuit characterized by comprising
Substrate is provided, the floating node for storing optical charge is formed in the substrate；
Form separator on the substrate, the separator be used to make the device in the pixel circuit each other electricity every
From；And
Transistor and capacitor are formed on the separator, so that the capacitor is by the coupled in parallel electric
It is connected to the floating node.
15. the method according to 14, which is characterized in that the separator is shallow trench isolation.
16. the method according to 14, which is characterized in that forming transistor includes:
Using semiconductor material on the separator deposited semiconductor material；
The first part of the semiconductor material is doped, the channel of the transistor is formed, wherein the channel
Doping type be the first doping type；
The first dielectric material is deposited on the channel, as gate insulating layer；
The first conductive material is deposited on the gate insulating layer, as control electrode；
The remainder of the semiconductor material is doped so that the doping type of the remainder be with it is described
The second different doping type of first doping type, to form the third electrode and the 4th electrode of the transistor.
17. the method according to 16, which is characterized in that forming capacitor includes:
Using the second part different from first part of the semiconductor material as first electrode, and described first
The second dielectric material and the second conductive material are sequentially depositing on electrode, wherein second conductive material is as the capacitor
Second electrode.
18. the method according to 16, which is characterized in that the semiconductor material is silicon or germanium.
19. the method according to 16, which is characterized in that first dielectric material and second dielectric material are oxygen
Compound, nitride or nitrogen oxides.
20. the method according to 19, which is characterized in that first dielectric material and second dielectric material are oxygen
SiClx, silicon nitride or silicon oxynitride.
21. the method according to 14, which is characterized in that the floating node is adjacent with the groove, the transistor
The 4th electrode directly contact the floating node.
22. the method according to 14, which is characterized in that each pixel in the pixel circuit includes multiple isolation
Part has at least one of the capacitor and transistor at least two separators in the multiple separator.
23. a kind of imaging sensor, including the pixel circuit according to any one of 1-13.
Although being described in detail by some specific embodiments of the example to the disclosure, the skill of this field
Art personnel it should be understood that above example merely to be illustrated, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out without departing from the scope and spirit of the disclosure to embodiment.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
1. a kind of pixel circuit characterized by comprising
Floating node, for storing optical charge；
Transistor；
Capacitor is electrically connected to the floating node by the coupled in parallel；And
Separator, for keeping the device in the pixel circuit electrically isolated from one,
Wherein, the transistor and the capacitor are all located on the separator.
2. pixel circuit according to claim 1, which is characterized in that the separator is shallow trench isolation.
3. pixel circuit according to claim 1, which is characterized in that the capacitor includes first electrode, second electrode
And the dielectric material between first electrode and second electrode, wherein the surface of the first electrode and the separator
It is adjacent.
4. pixel circuit according to claim 3, which is characterized in that the first electrode is made of semiconductor material.
5. pixel circuit according to claim 4, which is characterized in that the semiconductor material is silicon or germanium.
6. pixel circuit according to claim 4 or 5, which is characterized in that the semiconductor material of the first electrode is to mix
Miscellaneous, the transistor includes channel, and the doping type of the channel is opposite with the doping type of the first electrode.
7. pixel circuit according to claim 6, which is characterized in that the transistor further includes control electrode, third electrode
With the 4th electrode, wherein the third electrode is electrically connected to described via the channel according to the voltage of the control electrode
Four electrodes, the third electrode are electrically connected with the first electrode.
8. pixel circuit according to claim 7, which is characterized in that the material of the third electrode and the first electrode
It is identical.
9. pixel circuit according to claim 7, which is characterized in that the 4th electrode is electrically connected to the floating section
Point.
10. pixel circuit according to claim 7, which is characterized in that the floating node is adjacent with the separator, institute
The 4th electrode for stating transistor is directly contacted with the floating node.
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| CN205159324U (en) * | 2014-11-25 | 2016-04-13 | 半导体元件工业有限责任公司 | Image sensor pixel circuit and treater system |
| CN107040732A (en) * | 2016-02-03 | 2017-08-11 | 原相科技股份有限公司 | Image sensing circuit and method |
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| CN102891148A (en) * | 2011-07-18 | 2013-01-23 | 台湾积体电路制造股份有限公司 | Structure and method for single gate non-volatile memory device |
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Application publication date: 20190226 |