CN104464808B - A kind of new NOR Flash decoding circuits - Google Patents
A kind of new NOR Flash decoding circuits Download PDFInfo
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- CN104464808B CN104464808B CN201410819478.7A CN201410819478A CN104464808B CN 104464808 B CN104464808 B CN 104464808B CN 201410819478 A CN201410819478 A CN 201410819478A CN 104464808 B CN104464808 B CN 104464808B
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- nmos tube
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- source electrode
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Abstract
The invention provides a kind of new NOR Flash decoding circuits, the circuit is made up of NMOS tube array, it is characterized in that：The drain electrode of first horizontally-arranged NMOS tube connects different PS leads, and grid connects identical PG leads, and source electrode is connected with the drain electrode of the second horizontally-arranged NMOS tube, and draws wordline WL respectively；The drain electrode of second horizontally-arranged NMOS tube is connected with the source electrode of the first horizontally-arranged NMOS tube, and grid meets identical NG, and source electrode is connected with the drain electrode positioned at the 3rd horizontally-arranged NMOS tube；3rd horizontally-arranged includes a NMOS tube, its drain electrode is connected with the source electrode of the second horizontally-arranged NMOS tube, grid meets chip selection signal CHIPG, source electrode meets PG, by way of being decoded only with NMOS, the N traps needed for introducing PMOS are avoided, reduce circuit area, while the reading speed of circuit is improved by combining various sizes of NMOS tube.
Description
Technical field
The present invention relates to field of circuit technology, more particularly to a kind of new NOR Flash decoding circuits.
Background technology
NOR Flash and NAND Flash are two kinds of main nonvolatile flash memory technologies currently on the market, NOR Flash's
Feature is to perform (XIP, eXecute In Place) in chip, and such application program directly can be run in Flash flash memories,
Code need not be read in system RAM again, therefore stability and efficiency of transmission are very high, this is well suited for being used for embedded system conduct
NOR FLASH ROM.At present, the NOR FLASH extensive uses in SOC.
All memory (or I/O interfaces) is all mutually distinguished with address, (or is accessed I/O according to memory is accessed and is connect
Mouthful) address information in instruction, its address decoding circuitry produces corresponding address selected signal, to choose required memory
(or I/O interfaces).
Existing NOR Flash decoding circuit using NMOS and PMOS hybrid decodings mode, using this mode institute
The decoding circuit of design introduces N traps and p-well respectively due to needing, therefore shared area is larger, is unfavorable for NOR Flash storages
The raising of density, decoding circuit are responsible for the voltage under different working condition to be transferred to cell, divide Y-direction in NOR flash
The decoding of (drain for being transferred to cell) and X-direction (wordline for being transferred to cell) both direction, X-direction therein was both
Transmit positive voltage and transmit negative voltage again so that circuit can be very complicated, takes very big area, therefore also increase unit
The cost of amount of storage, the read or write speed of existing NOR Flash decoding circuits is also urgent problem to be solved more slowly in addition.
The content of the invention
Present invention aims at a kind of new NOR Flash decoding circuits are provided, to reduce the area of decoding circuit and increasing
Add read or write speed.
Concrete technical scheme is as follows：
The drain electrode of first horizontally-arranged NMOS tube connects different PS leads, and grid connects identical PG leads, and source electrode is horizontally-arranged with second
The drain electrode of NMOS tube is connected, and draws wordline WL respectively, and wherein PS represents the malleation signal needed for wordline, and a bank is total to
With；PG represents transmission malleation PS signal, and a sector is shared.
The drain electrode of second horizontally-arranged NMOS tube is connected with the source electrode of the first horizontally-arranged NMOS tube, and grid meets identical NG, source electrode with
The drain electrode of the NMOS tube horizontally-arranged positioned at the 3rd is connected, and wherein NG represents the signal of transmission zero or negative pressure, and a sector is shared.
3rd horizontally-arranged includes a NMOS tube, and its drain electrode is connected with the source electrode of the second horizontally-arranged NMOS tube, grid contact pin
Signal CHIPG is selected, source electrode meets PG.
Further, NMOS tube array includes 2N+1 (N >=1) individual NMOS tube altogether, wherein the first horizontally-arranged NMOS tube and second
The quantity of horizontally-arranged NMOS tube is the same, all individual for N (N >=1), and the 3rd horizontally-arranged NMOS tube quantity is 1, and NMOS number can be according to knot
The difference of structure.
Further, the breadth length ratio of the 3rd horizontally-arranged NMOS tube is more than the breadth length ratio of the second horizontally-arranged NMOS tube, and second is horizontally-arranged
The breadth length ratio of NMOS tube is more than the breadth length ratio of the first horizontally-arranged NMOS tube.The breadth length ratio of NMOS tube is bigger, electric current increase, such circuit
Reading speed can accelerate.
Further, when performing writes, PG lead ends add 5V to 15V voltage, NG termination 0V voltages, CHIPG ends
Connect supply voltage, PS lead ends optionally connected 4V to 12V voltage or connect 0V voltages；
When performing erasing operation, PS lead ends meet 0V voltages, NG termination 0V voltages, the optionally connected -5V of PG lead ends
To -12V voltage or connect 0V voltages.
Further, when performing writes, for the sector chosen, PG lead ends add 5V to 15V voltages, NG terminations
0V voltages, CHIPG termination power voltages, the PS lead ends chosen add 4V to 12V voltages, unchecked PS terminations 0V voltages；
For the unselected sector of the same bank of the sector with choosing, PG lead ends add 0V voltages, NG ends
Supply voltage, CHIPG termination power voltages are connect, the PS lead ends chosen add 4V to 12V voltages, unchecked PS terminations 0V electricity
Pressure；
For the unselected sector of the sector differences bank with choosing, PG lead ends add 0V voltages, NG terminations
Supply voltage, CHIPG termination power voltages, PS termination 0V voltages.
When performing erasing operation, PS lead ends connect 0V voltages, NG termination 0V voltages, and PG lead ends are for choosing
Sector meets -5V to -12V voltages, and that does not choose connects 0V voltages；CHIPG ends connect 0V voltages for the bank chosen, unselected
In bank meet -5V to -12V voltages.
Compared with prior art, had the following advantages that using technical scheme provided by the invention：By being translated only with NMOS
The mode of code, the N traps introduced needed for PMOS are avoided, reduce circuit area, while by combining various sizes of NMOS tube
Improve the reading speed of circuit.
Brief description of the drawings
Fig. 1 is the schematic diagram according to a kind of new NOR Flash decoding circuits of embodiments of the invention.
Embodiment
Embodiments of the invention are described below in detail.
The example of the embodiment is shown in the drawings, wherein same or similar label represents identical or class from beginning to end
As element or with same or like function element.The embodiments described below with reference to the accompanying drawings are exemplary, only
For explaining the present invention, and it is not construed as limiting the claims.Following disclosure provide many different embodiments or
Example is used for realizing the different structure of the present invention.In order to simplify disclosure of the invention, hereinafter to the parts of specific examples and set
Put and be described.Certainly, they are only example, and purpose does not lie in the limitation present invention.In addition, the present invention can be in difference
Repeat reference numerals and/or letter in example.This repetition is for purposes of simplicity and clarity, itself not indicate to be discussed
Relation between various embodiments and/or setting.In addition, the invention provides various specific circuits and device examples,
But those of ordinary skill in the art can be appreciated that the applicable property of other circuits and/or the use of other devices.
The invention provides a kind of NOR Flash decoding circuits.Below, an implementations of the Fig. 1 by the present invention will be combined
This circuit is specifically described example.As shown in figure 1, NOR Flash decoding circuits provided by the present invention are included with lower part：
NOR Flash decoding circuits of the present invention include：
Such as Fig. 1, the drain electrode of the first horizontally-arranged NMOS tube connects different PS leads, and grid connects identical PG leads, source electrode and
The drain electrode of two horizontally-arranged NMOS tubes is connected, and draws wordline WL respectively；
The drain electrode of second horizontally-arranged NMOS tube is connected with the source electrode of the first horizontally-arranged NMOS tube, and grid meets identical NG, drain electrode with
The drain electrode of the NMOS tube horizontally-arranged positioned at the 3rd is connected；
3rd horizontally-arranged includes a NMOS tube, and its drain electrode is connected with the source electrode of the second horizontally-arranged NMOS tube, grid contact pin
Signal CHIPG is selected, source electrode meets PG.
Wherein NMOS tube array includes 33 NMOS tubes altogether, wherein the first horizontally-arranged NMOS tube and the second horizontally-arranged NMOS tube difference
Including 16 NMOS tubes, the 3rd horizontally-arranged NMOS tube quantity is 1；Other NMOS number can be according to the difference of structure, can also
First it is horizontally-arranged and second it is horizontally-arranged be 8, the 3rd horizontally-arranged one.
Meanwhile the 3rd horizontally-arranged NMOS tube breadth length ratio be more than the second horizontally-arranged NMOS tube breadth length ratio, the second horizontally-arranged NMOS tube
Breadth length ratio be more than the first horizontally-arranged NMOS tube breadth length ratio.
When performing writes, for the sector chosen, PG lead ends add 11V voltages, NG termination 0V, CHIPG terminations
Supply voltage VCC, the PS lead ends chosen add 8V voltages, and unchecked PS terminates 0V voltages；It is same for the sector with choosing
The one bank sector not chosen, PG lead ends add 0V voltages, NG termination power voltage VCC, CHIPG termination power electricity
VCC is pressed, the PS lead ends chosen add 8V voltages, and unchecked PS terminates 0V；For the not same bank of the sector with choosing
The sector not chosen, PG lead ends add 0V voltages, NG termination power voltage VCC, CHIPG termination power voltages VCC, PS
Terminate 0V voltages.
When performing erasing operation, PS lead ends connect 0V voltages, NG termination 0V voltages, and PG lead ends are for choosing
Sector connects -9V voltages, and that does not choose connects 0V voltages.The bank that CHIPG chooses connects 0V voltages, the bank not chosen
Connect -9V voltages.
It the following is the calculation formula of metal-oxide-semiconductor electric current, wherein IDIt is the electric current of metal-oxide-semiconductor, Un is the mobility of electronics, CoxIt is oxygen
Change thickness degree, W/L is the breadth length ratio of device, VGSBe MOS device gate-source voltage it is poor, VTHIt is the threshold voltage of MOS device,
Un、CoxAnd VTHAll it is process constant.
It can be drawn from formula, W/L (breadth length ratio) is bigger, and metal-oxide-semiconductor electric current is also bigger, corresponding circuit reading speed
It can accelerate.
By way of being decoded only with NMOS, the N traps introduced needed for PMOS are avoided, reduce circuit area, NMOS
The breadth length ratio increase of pipe, its resistance reduce, and electric current increase, the reading speed of such circuit can be accelerated, and circuit of the present invention reads speed
Degree can lift 10% or so.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Not
In the case of departing from the principle and objective of the present invention a variety of change, modification, replacement and modification can be carried out to these embodiments, this
The scope of invention is limited by claim and its equivalent.
Claims (2)
1. a kind of new NOR Flash decoding circuits, the circuit are made up of NMOS tube array, it is characterised in that：
The drain electrode of first horizontally-arranged NMOS tube connects different PS leads, and grid meets identical PG leads, source electrode and the second horizontally-arranged NMOS
The drain electrode of pipe is connected, and draws wordline WL respectively；
The drain electrode of second horizontally-arranged NMOS tube is connected with the source electrode of the first horizontally-arranged NMOS tube, and grid meets identical NG, and source electrode is with being located at
The drain electrode of 3rd horizontally-arranged NMOS tube is connected；
3rd horizontally-arranged includes a NMOS tube, and its drain electrode is connected with the source electrode of the second horizontally-arranged NMOS tube, grid contact pin choosing letter
Number CHIPG, source electrode meet PG；
The breadth length ratio of the 3rd horizontally-arranged NMOS tube is more than the breadth length ratio of the described second horizontally-arranged NMOS tube, the second horizontally-arranged NMOS
The breadth length ratio of pipe is more than the breadth length ratio of the described first horizontally-arranged NMOS tube；
When performing writes, for the sector chosen, PG lead ends add 5V to 15V voltages, NG termination 0V voltages, CHIPG
Termination power voltage, the PS lead ends chosen add 4V to 12V voltages, unchecked PS terminations 0V voltages；
For the unselected sector of the same bank of the sector with choosing, PG lead ends add 0V voltages, NG termination electricity
Source voltage, CHIPG termination power voltages, the PS lead ends chosen add 4V to 12V voltages, unchecked PS terminations 0V voltages；
For the unselected sector of the sector differences bank with choosing, PG lead ends add 0V voltages, NG termination powers
Voltage, CHIPG termination power voltages, PS termination 0V voltages；
When performing erasing operation, PS lead ends connect 0V voltages, NG termination 0V voltages, and PG lead ends are for the sector that chooses
- 5V is met to -12V voltages, that does not choose connects 0V voltages；CHIPG ends connect 0V voltages for the bank chosen, unchecked
Bank meets -5V to -12V voltages.
2. circuit according to claim 1, it is characterised in that the NMOS tube array includes 2N+1 NMOS tube altogether, its
Described in the first horizontally-arranged NMOS tube as the quantity of the described second horizontally-arranged NMOS tube, all to be N number of, the 3rd horizontally-arranged NMOS tube quantity
For 1；Wherein, N >=1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410819478.7A CN104464808B (en) | 2014-12-25 | 2014-12-25 | A kind of new NOR Flash decoding circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410819478.7A CN104464808B (en) | 2014-12-25 | 2014-12-25 | A kind of new NOR Flash decoding circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104464808A CN104464808A (en) | 2015-03-25 |
| CN104464808B true CN104464808B (en) | 2018-01-19 |
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| CN201410819478.7A Expired - Fee Related CN104464808B (en) | 2014-12-25 | 2014-12-25 | A kind of new NOR Flash decoding circuits |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364440A (en) * | 2007-08-06 | 2009-02-11 | 海力士半导体有限公司 | Block decoder and semiconductor memory device including the same |
| CN102646449A (en) * | 2011-02-17 | 2012-08-22 | 宜扬科技股份有限公司 | Regional character line driver and flash memory array device thereof |
| CN103177754A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Address decoding circuit for storer |
| CN103177756A (en) * | 2013-03-25 | 2013-06-26 | 西安华芯半导体有限公司 | Power saving method of dynamic memory under read operation and column selection signal driving circuit of dynamic memory |
| CN204516363U (en) * | 2014-12-25 | 2015-07-29 | 武汉云雅科技有限公司 | A kind of novel NOR Flash decoding scheme |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009272000A (en) * | 2008-05-07 | 2009-11-19 | Toshiba Microelectronics Corp | Nonvolatile semiconductor memory and its test method |
| CN102881330A (en) * | 2011-07-14 | 2013-01-16 | 华邦电子股份有限公司 | Source switch and flash memory device |
-
2014
- 2014-12-25 CN CN201410819478.7A patent/CN104464808B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364440A (en) * | 2007-08-06 | 2009-02-11 | 海力士半导体有限公司 | Block decoder and semiconductor memory device including the same |
| CN102646449A (en) * | 2011-02-17 | 2012-08-22 | 宜扬科技股份有限公司 | Regional character line driver and flash memory array device thereof |
| CN103177754A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Address decoding circuit for storer |
| CN103177756A (en) * | 2013-03-25 | 2013-06-26 | 西安华芯半导体有限公司 | Power saving method of dynamic memory under read operation and column selection signal driving circuit of dynamic memory |
| CN204516363U (en) * | 2014-12-25 | 2015-07-29 | 武汉云雅科技有限公司 | A kind of novel NOR Flash decoding scheme |
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| CN104464808A (en) | 2015-03-25 |
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