CN104464808A - Novel NOR Flash decoding circuit - Google Patents
Novel NOR Flash decoding circuit Download PDFInfo
- Publication number
- CN104464808A CN104464808A CN201410819478.7A CN201410819478A CN104464808A CN 104464808 A CN104464808 A CN 104464808A CN 201410819478 A CN201410819478 A CN 201410819478A CN 104464808 A CN104464808 A CN 104464808A
- Authority
- CN
- China
- Prior art keywords
- voltage
- nmos tube
- horizontally
- termination
- lead end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a novel NOR Flash decoding circuit. The novel NOR Flash decoding circuit consists of NMOS tube arrays. The novel NOR Flash decoding circuit is characterized in that source electrodes of a first transverse row of NMOS tubes are connected to different PS lead wires, grid electrodes are connected to the same PG lead wire, drain electrodes are respectively connected to source electrodes of the second transverse row of NMOS tubes and word lines WL are respectively led out; the source electrodes of the second transverse row of NMOS tubes are connected to the drain electrodes of the first transverse row of the NMOS tubes, the grid electrodes are connected to the same NG, the drain electrodes are connected to a source electrode of a third transverse row of NMOS tube; the third transverse row only includes one NMOS tube, the source electrode of which is connected to the drain electrodes of the second transverse row of NMOS tubes, the grid electrode is connected to a chip selection signal CHIPG, and the drain electrode is connected to the PG. By only adopting an NMOS decoding method, the N well needed for introducing the PMOS is avoided, the circuit area is reduced; meanwhile, the reading speed of the circuit is increased by combining the NMOS tubes with different dimensions.
Description
Technical field
The present invention relates to circuit engineering field, particularly relate to a kind of novel NOR Flash decoding scheme.
Background technology
NOR Flash and NAND Flash is existing commercially two kinds of main nonvolatile flash memory technology, the feature of NOR Flash performs (XIP in chip, eXecute In Place), such application program can directly be run in Flash flash memory, need not again code be read in system RAM, therefore stability and transfer efficiency are very high, and this is well suited for for embedded system as NOR FLASH ROM.At present, NOR FLASH widespread use in SOC.
All storeies (or I/O interface) are all distinguished mutually with address, according to the address information in access storer (or access I/O interface) instruction, its address decoding circuitry produces corresponding address selected signal, to choose required storer (or I/O interface).
The mode of NMOS and PMOS hybrid decoding that what the decoding scheme of existing NOR Flash adopted is, the decoding scheme designed by this mode is adopted to introduce N trap and P trap respectively due to needs, therefore shared area is larger, be unfavorable for the raising of NOR Flash storage density, decoding scheme is in NOR flash, be responsible for the voltage transmission under different operating state to cell, the decoding of point Y-direction (being transferred to the drain of cell) and X-direction (being transferred to the wordline of cell) both direction, X-direction wherein should be transmitted positive voltage and transmit negative voltage again, make circuit can be very complicated, take very large area, therefore the cost of unit memory space is also just added, in addition the read or write speed of existing NOR Flash decoding scheme is also problem demanding prompt solution comparatively slowly.
Summary of the invention
The object of the invention is to provide a kind of new NOR Flash decoding scheme, reduces the area of decoding scheme and increases read or write speed.
Concrete technical scheme is as follows:
The source electrode of the first horizontally-arranged NMOS tube connects different PS lead-in wires, and grid connects identical PG lead-in wire, and the source electrode of the NMOS tube horizontally-arranged with second that drain is connected, and draws wordline WL respectively, and wherein PS represents the malleation signal needed for wordline, and a bank shares; PG represents the signal of transmission malleation PS, and a sector shares.
The source electrode of the second horizontally-arranged NMOS tube is connected with the drain electrode of the first horizontally-arranged NMOS tube, and grid meets identical NG, drains to be connected with the source electrode being positioned at the 3rd horizontally-arranged NMOS tube, and wherein NG represents the signal of transmission zero or negative pressure, and a sector shares.
3rd horizontally-arranged comprises a NMOS tube, and its source electrode is connected with the drain electrode of the second horizontally-arranged NMOS tube, and grid meets chip selection signal CHIPG, and drain electrode meets PG.
Further, NMOS tube array comprises 2N+1 (N >=1) individual NMOS tube altogether, and wherein the first horizontally-arranged NMOS tube is the same with the quantity of the second horizontally-arranged NMOS tube, is all that N (N >=1) is individual, 3rd horizontally-arranged NMOS tube quantity is 1, and the number of NMOS can according to the difference of structure.
Further, the breadth length ratio of the 3rd horizontally-arranged NMOS tube is greater than the breadth length ratio of the second horizontally-arranged NMOS tube, and the breadth length ratio of the second horizontally-arranged NMOS tube is greater than the breadth length ratio of the first horizontally-arranged NMOS tube.The breadth length ratio of NMOS tube is larger, and electric current increases, and the reading speed of such circuit can be accelerated.
Further, when performing writes, PG lead end adds the voltage of 5V to 15V, NG termination 0V voltage, CHIPG termination power voltage, the voltage of the optionally connected 4V to 12V of PS lead end or connect 0V voltage;
When perform erase operation time, PS lead end all connects 0V voltage, NG termination 0V voltage, the optionally connected-5V of PG lead end to-12V voltage or connect 0V voltage.
Further, when performing writes, add 5V to 15V voltage for the sector chosen, PG lead end, NG termination 0V voltage, CHIPG termination power voltage, the PS lead end chosen adds 4V to 12V voltage, unchecked PS termination 0V voltage;
For with the same bank of described sector chosen do not choose sector, PG lead end adds 0V voltage, NG termination power voltage, CHIPG termination power voltage, and the PS lead end chosen adds 4V to 12V voltage, unchecked PS termination 0V voltage;
For from the different bank of described sector chosen do not choose sector, PG lead end adds 0V voltage, NG termination power voltage, CHIPG termination power voltage, PS termination 0V voltage.
When performing erase operation, PS lead end all connects 0V voltage, NG termination 0V voltage, and PG lead end meets-5V to-12V voltage for what choose, and that does not choose connects 0V voltage; CHIPG end connects 0V voltage for the bank chosen, and unchecked sector meets-5V to-12V voltage.
Compared with prior art, technical scheme tool provided by the invention is adopted to have the following advantages: by only adopting the mode of NMOS decoding, avoid the N trap introduced needed for PMOS, reduce circuit area, the NMOS tube simultaneously by combining different size improves the reading speed of circuit.
Accompanying drawing explanation
Fig. 1 is a kind of according to an embodiment of the invention schematic diagram of novel NOR Flash decoding scheme.
Embodiment
Embodiments of the invention are described below in detail.
The example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.Disclosing hereafter provides many different embodiments or example is used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can in different example repeat reference numerals and/or letter.This repetition is to simplify and clearly object, itself does not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific circuit that the invention provides and the example of device, but those of ordinary skill in the art can recognize the property of can be applicable to of other circuit and/or the use of other devices.
The invention provides a kind of NOR Flash decoding scheme.Below, composition graphs 1 is specifically described this circuit by one embodiment of the present of invention.As shown in Figure 1, NOR Flash decoding scheme provided by the present invention comprises with lower part:
NOR Flash decoding scheme of the present invention comprises:
As Fig. 1, the source electrode of the first horizontally-arranged NMOS tube connects different PS lead-in wires, and grid connects identical PG lead-in wire, and the source electrode of the NMOS tube horizontally-arranged with second that drain is connected, and draws wordline WL respectively;
The source electrode of the second horizontally-arranged NMOS tube is connected with the drain electrode of the first horizontally-arranged NMOS tube, and grid meets identical NG, drains to be connected with the source electrode being positioned at the 3rd horizontally-arranged NMOS tube;
3rd horizontally-arranged comprises a NMOS tube, and its source electrode is connected with the drain electrode of the second horizontally-arranged NMOS tube, and grid meets chip selection signal CHIPG, and drain electrode meets PG.
Wherein NMOS tube array comprises 33 NMOS tube altogether, and wherein the first horizontally-arranged NMOS tube and the second horizontally-arranged NMOS tube comprise 16 NMOS tube respectively, and the 3rd horizontally-arranged NMOS tube quantity is 1; The number of NMOS can according to the difference of structure in addition, also can first horizontally-arranged and second horizontally-arranged be 8, the 3rd horizontally-arranged one.
Meanwhile, the breadth length ratio of the 3rd horizontally-arranged NMOS tube is greater than the breadth length ratio of the second horizontally-arranged NMOS tube, and the breadth length ratio of the second horizontally-arranged NMOS tube is greater than the breadth length ratio of the first horizontally-arranged NMOS tube.
When performing writes, add 11V voltage for the sector chosen, PG lead end, NG termination 0V, CHIPG termination power voltage VCC, the PS lead end chosen adds 8V voltage, unchecked PS termination 0V voltage; For the sector do not chosen with the same bank of the sector chosen, PG lead end adds 0V voltage, NG termination power voltage VCC, CHIPG termination power voltage VCC, and the PS lead end chosen adds 8V voltage, unchecked PS termination 0V; For the sector do not chosen with the not same bank of the sector chosen, PG lead end adds 0V voltage, NG termination power voltage VCC, CHIPG termination power voltage VCC, PS termination 0V voltage.
When performing erase operation, PS lead end all connects 0V voltage, NG termination 0V voltage, and PG lead end connects-9V voltage for what choose, and that does not choose connects 0V voltage.The bank that CHIPG chooses connects 0V voltage, and the sector do not chosen connects-9V voltage.
The following is the computing formula of metal-oxide-semiconductor electric current, wherein I
dbe the electric current of metal-oxide-semiconductor, Un is the mobility of electronics, C
oxbe oxidated layer thickness, W/L is the breadth length ratio of device, V
gSthe gate-source voltage being MOS device is poor, V
tHthe threshold voltage of MOS device, U
n, C
oxand V
tHit is all process constant.
Can draw from formula, W/L (breadth length ratio) is larger, and metal-oxide-semiconductor electric current is also larger, and corresponding circuit reading speed also can be accelerated.
By only adopting the mode of NMOS decoding, avoiding the N trap introduced needed for PMOS, reducing circuit area, the breadth length ratio of NMOS tube increases, and its resistance reduces, and electric current increases, the reading speed of such circuit can be accelerated, and circuit reading speed of the present invention can promote about 10%.
Although illustrate and describe embodiments of the invention, those having ordinary skill in the art will appreciate that: can carry out multiple change, amendment, replacement and modification to these embodiments when not departing from principle of the present invention and aim, scope of the present invention is by claim and equivalents thereof.
Claims (5)
1. a novel NOR Flash decoding scheme, described circuit is made up of NMOS tube array, it is characterized in that:
The source electrode of the first horizontally-arranged NMOS tube connects different PS lead-in wires, and grid connects identical PG lead-in wire, and the source electrode of the NMOS tube horizontally-arranged with second that drain is connected, and draws wordline WL respectively;
The source electrode of the second horizontally-arranged NMOS tube is connected with the drain electrode of the first horizontally-arranged NMOS tube, and grid meets identical NG, drains to be connected with the source electrode being positioned at the 3rd horizontally-arranged NMOS tube;
3rd horizontally-arranged comprises a NMOS tube, and its source electrode is connected with the drain electrode of the second horizontally-arranged NMOS tube, and grid meets chip selection signal CHIPG, and drain electrode meets PG.
2. circuit according to claim 1, it is characterized in that, described NMOS tube array comprises 2N+1 (N >=1) individual NMOS tube altogether, wherein said first horizontally-arranged NMOS tube is the same with the quantity of described second horizontally-arranged NMOS tube, be all that N (N >=1) is individual, the 3rd horizontally-arranged NMOS tube quantity is 1.
3. circuit according to claim 1, is characterized in that, the breadth length ratio of described 3rd horizontally-arranged NMOS tube is greater than the breadth length ratio of described second horizontally-arranged NMOS tube, and the breadth length ratio of described second horizontally-arranged NMOS tube is greater than the breadth length ratio of described first horizontally-arranged NMOS tube.
4. circuit according to claim 1, is characterized in that, when performing writes, described PG lead end adds the voltage of 5V to 15V, described NG termination 0V voltage, described CHIPG termination power voltage, the voltage of the optionally connected 4V to 12V of described PS lead end or connect 0V voltage;
When perform erase operation time, described PS lead end all connects 0V voltage, described NG termination 0V voltage, the optionally connected-5V of described PG lead end to-12V voltage or connect 0V voltage.
5. circuit according to claim 1, is characterized in that, when performing writes, 5V to 15V voltage is added for the sector chosen, PG lead end, NG termination 0V voltage, CHIPG termination power voltage, the PS lead end chosen adds 4V to 12V voltage, unchecked PS termination 0V voltage;
For with the same bank of described sector chosen do not choose sector, PG lead end adds 0V voltage, NG termination power voltage, CHIPG termination power voltage, and the PS lead end chosen adds 4V to 12V voltage, unchecked PS termination 0V voltage;
For from the different bank of described sector chosen do not choose sector, PG lead end adds 0V voltage, NG termination power voltage, CHIPG termination power voltage, PS termination 0V voltage.
When performing erase operation, PS lead end all connects 0V voltage, NG termination 0V voltage, and PG lead end meets-5V to-12V voltage for what choose, and that does not choose connects 0V voltage; CHIPG end connects 0V voltage for the bank chosen, and unchecked sector meets-5V to-12V voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410819478.7A CN104464808B (en) | 2014-12-25 | 2014-12-25 | A kind of new NOR Flash decoding circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410819478.7A CN104464808B (en) | 2014-12-25 | 2014-12-25 | A kind of new NOR Flash decoding circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104464808A true CN104464808A (en) | 2015-03-25 |
| CN104464808B CN104464808B (en) | 2018-01-19 |
Family
ID=52910741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410819478.7A Expired - Fee Related CN104464808B (en) | 2014-12-25 | 2014-12-25 | A kind of new NOR Flash decoding circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104464808B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364440A (en) * | 2007-08-06 | 2009-02-11 | 海力士半导体有限公司 | Block decoder and semiconductor memory device including the same |
| US20090279357A1 (en) * | 2008-05-07 | 2009-11-12 | Hitoshi Ohta | Nonvolatile semiconductor storage device and method of testing the same |
| CN102646449A (en) * | 2011-02-17 | 2012-08-22 | 宜扬科技股份有限公司 | Regional character line driver and flash memory array device thereof |
| CN102881330A (en) * | 2011-07-14 | 2013-01-16 | 华邦电子股份有限公司 | Source switch and flash memory device |
| CN103177756A (en) * | 2013-03-25 | 2013-06-26 | 西安华芯半导体有限公司 | Power saving method of dynamic memory under read operation and column selection signal driving circuit of dynamic memory |
| CN103177754A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Address decoding circuit for storer |
| CN204516363U (en) * | 2014-12-25 | 2015-07-29 | 武汉云雅科技有限公司 | A kind of novel NOR Flash decoding scheme |
-
2014
- 2014-12-25 CN CN201410819478.7A patent/CN104464808B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364440A (en) * | 2007-08-06 | 2009-02-11 | 海力士半导体有限公司 | Block decoder and semiconductor memory device including the same |
| US20090279357A1 (en) * | 2008-05-07 | 2009-11-12 | Hitoshi Ohta | Nonvolatile semiconductor storage device and method of testing the same |
| CN102646449A (en) * | 2011-02-17 | 2012-08-22 | 宜扬科技股份有限公司 | Regional character line driver and flash memory array device thereof |
| CN102881330A (en) * | 2011-07-14 | 2013-01-16 | 华邦电子股份有限公司 | Source switch and flash memory device |
| CN103177754A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Address decoding circuit for storer |
| CN103177756A (en) * | 2013-03-25 | 2013-06-26 | 西安华芯半导体有限公司 | Power saving method of dynamic memory under read operation and column selection signal driving circuit of dynamic memory |
| CN204516363U (en) * | 2014-12-25 | 2015-07-29 | 武汉云雅科技有限公司 | A kind of novel NOR Flash decoding scheme |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104464808B (en) | 2018-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9424939B2 (en) | Non-volatile memory apparatus and erasing method thereof | |
| CN101617371B (en) | Non-volatile semiconductor memory having multiple external power supplies | |
| KR101384316B1 (en) | Semiconductor memory devices | |
| TWI685849B (en) | Semiconductor memory device and operating method thereof | |
| CN107564567A (en) | The method being programmed to semiconductor memory system | |
| CN102136293A (en) | Method of programming non-volatile semiconductor memory device | |
| CN104903965A (en) | Erase for non-volatile storage | |
| CN105261386A (en) | Semiconductor memory device including three-dimensional array structure | |
| CN102314946A (en) | Voltage switch circuit and the nonvolatile semiconductor memory member that uses it | |
| US10790033B2 (en) | Operating method of memory device using channel boosting before read or verify operation | |
| CN105006251B (en) | NAND-type flash memory and method for programming thereof | |
| CN109243510A (en) | Semiconductor storage and its operating method | |
| CN103456359A (en) | Improved differential framework Nor flash storage unit based on serially-connected transistor type | |
| CN101986389B (en) | Flash memory unit, flash memory device and programming method thereof | |
| US9472292B1 (en) | Semiconductor memory device | |
| CN103117085A (en) | Bias voltage generating circuit and memory of line decoder | |
| KR20100013960A (en) | Erase method of flash device | |
| CN103824597A (en) | Memory as well as readout circuit and reading method of memory cell | |
| US10176879B2 (en) | High voltage switch circuit and semiconductor memory device including the same | |
| CN104464810A (en) | Storage and erasing, programming and reading method thereof | |
| CN109524043A (en) | Semiconductor storage | |
| CN204516363U (en) | A kind of novel NOR Flash decoding scheme | |
| CN106024058B (en) | Semiconductor storage and data processing method | |
| CN109448775B (en) | Memory array structure and operation method thereof | |
| CN104282336A (en) | Semiconductor memory device and programming method for flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180119 Termination date: 20191225 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |