CN104460796A - Circuit capable of generating constant charging time constants - Google Patents
Circuit capable of generating constant charging time constants Download PDFInfo
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- CN104460796A CN104460796A CN201410548526.3A CN201410548526A CN104460796A CN 104460796 A CN104460796 A CN 104460796A CN 201410548526 A CN201410548526 A CN 201410548526A CN 104460796 A CN104460796 A CN 104460796A
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- oxide
- metal
- semiconductor
- current source
- mirror current
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Abstract
The invention relates to a circuit capable of generating constant charging time constants. The source electrode of a first MOS tube is connected with the drain electrode of a second MOS tube, the source electrode of the second MOS tube is connected to the ground, and the grid electrode of the second MOS tube is connected with the grid electrode of a third MOS tube. The drain electrode of the third MOS tube is connected with a first image current source, the source electrode of the third MOS tube is connected with the drain electrode of a fourth MOS tube, the source electrode of the fourth MOS tube is connected to the ground, and the grid electrode of the fourth MOS tube is connected with the grid electrode of the third MOS tube. The third MOS tube is of a diode type and works at a saturation region, and the fourth MOS tube works at a linear region; a first single-pole double-throw switch and a second single-pole double-throw switch are arranged between the first image current source and a second image current source and connected in series; the positive input end of a first comparator and the negative input end of a second comparator are connected between the first single-pole double-throw switch and the second single-pole double-throw switch and connected with an MOS capacitor. The circuit can greatly lower system cost.
Description
Technical field
The present invention relates to integrated circuit (IC) design technical field, particularly relate to a kind of circuit producing constant charging rate.
Background technology
The method of the constant charging rate of existing generation is that employing external perimysium reference benchmark is for referencial use, adopt the method for phaselocked loop or Resistor-Capacitor Unit is decorated, but need more external devices when adopting phaselocked loop to produce constant charging rate, then need extra making up use when adopting Resistor-Capacitor Unit to produce constant charging rate, two kinds of modes all can make the cost greatly improving system.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of circuit producing constant charging rate, greatly can reduce the cost of system.
The technical solution adopted for the present invention to solve the technical problems is: provide a kind of circuit producing constant charging rate, comprise generating circuit from reference voltage, the first mirror current source, the second mirror current source, the first comparer and the second comparer, the output terminal of described generating circuit from reference voltage is connected with the negative input end of operational amplifier, the output terminal of described operational amplifier is connected with the grid of the first metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor is connected to the positive input terminal of described operational amplifier, drains to be connected with the first mirror current source; The source electrode of described first metal-oxide-semiconductor is also connected with the drain electrode of the second metal-oxide-semiconductor, the source ground of described second metal-oxide-semiconductor, and grid is connected with the grid of the 3rd metal-oxide-semiconductor; The drain electrode of described 3rd metal-oxide-semiconductor is connected with the first mirror current source, and source electrode is connected with the drain electrode of the 4th metal-oxide-semiconductor, the source ground of described 4th metal-oxide-semiconductor, and grid is connected with the grid of described 3rd metal-oxide-semiconductor; Wherein, the 3rd metal-oxide-semiconductor is connected into diode form, is operated in saturation region, and the 4th metal-oxide-semiconductor is operated in linear zone; Described first mirror current source is also connected with the second mirror current source, described first mirror current source also be provided with two the first single-pole double-throw switch (SPDT)s and the second single-pole double-throw switch (SPDT) of mutually connecting between the second mirror current source; The positive input terminal of described first comparer and the negative input end of the second comparer are connected between the first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT), and are connected with mos capacitance; The negative input end of described first comparer is connected with high-order reference voltage, the positive input terminal of described second comparer is connected with low level reference voltage, the output terminal of described first comparer is connected with the switch shutdown side of logical circuit, and the output terminal of described second comparer is connected with the switch open end of logical circuit.
Described first mirror current source is made up of four metal-oxide-semiconductors.
Described second mirror current source is made up of two metal-oxide-semiconductors.
Beneficial effect
Owing to have employed above-mentioned technical scheme, the present invention compared with prior art, there is following advantage and good effect: the present invention is temperature independent by generation one, only with the electric current of the changes in process parameters of metal-oxide-semiconductor, by charging to the metal-oxide-semiconductor as electric capacity, thus the charging rate that generation one is constant, the method can save more external devices and extra trim expense than these conventional methods, thus greatly reduces the cost of system.
Accompanying drawing explanation
Fig. 1 is circuit diagram of the present invention;
Fig. 2 is the circuit diagram of generating circuit from reference voltage in the present invention;
Fig. 3 is the circuit diagram of the first mirror current source in the present invention;
Fig. 4 is the circuit diagram of the second mirror current source in the present invention;
Fig. 5 is mos capacitance performance diagram in the present invention;
Fig. 6 is the voltage oscillogram of mos capacitance working point in the present invention.
Embodiment
Below in conjunction with specific embodiment, set forth the present invention further.Should be understood that these embodiments are only not used in for illustration of the present invention to limit the scope of the invention.In addition should be understood that those skilled in the art can make various changes or modifications the present invention, and these equivalent form of values fall within the application's appended claims limited range equally after the content of having read the present invention's instruction.
Embodiments of the present invention relate to a kind of circuit producing constant charging rate, as shown in Figure 1, comprise generating circuit from reference voltage, the first mirror current source, the second mirror current source, the first comparer CP1 and the second comparer CP2, the output terminal of described generating circuit from reference voltage is connected with the negative input end of operational amplifier OP, the output terminal of described operational amplifier OP is connected with the grid of the first metal-oxide-semiconductor M1, the source electrode of described first metal-oxide-semiconductor M1 is connected to the positive input terminal of described operational amplifier OP, drains to be connected with the first mirror current source; The source electrode of described first metal-oxide-semiconductor M1 is also connected with the drain electrode of the second metal-oxide-semiconductor M2, the source ground of described second metal-oxide-semiconductor M2, and grid is connected with the grid of the 3rd metal-oxide-semiconductor M3; The drain electrode of described 3rd metal-oxide-semiconductor M3 is connected with the first mirror current source, and source electrode is connected with the drain electrode of the 4th metal-oxide-semiconductor M4, the source ground of described 4th metal-oxide-semiconductor M4, and grid is connected with the grid of described 3rd metal-oxide-semiconductor M3; Wherein, the 3rd metal-oxide-semiconductor M3 is connected into diode form, is operated in saturation region, and the 4th metal-oxide-semiconductor M4 is operated in linear zone; Described first mirror current source is also connected with the second mirror current source, described first mirror current source also be provided with two the first single-pole double-throw switch (SPDT) SP and the second single-pole double-throw switch (SPDT) SN mutually connected between the second mirror current source; The positive input terminal of described first comparer CP1 and the negative input end of the second comparer CP2 are connected between the first single-pole double-throw switch (SPDT) SP and the second single-pole double-throw switch (SPDT) SN, and are connected with mos capacitance C1; The negative input end of described first comparer CP1 is connected with high-order reference voltage, the positive input terminal of described second comparer CP2 is connected with low level reference voltage, the described output terminal of the first comparer CP1 is connected with the switch shutdown side of logical circuit, and the described output terminal of the second comparer CP2 is connected with the switch open end of logical circuit.
Fig. 2 is the circuit diagram of generating circuit from reference voltage in the present invention, and this circuit is for generation of reference voltage Vr, high-order reference voltage Vtrh and low level reference voltage Vtrl; Fig. 3 is the circuit diagram of the first mirror current source in the present invention, is made up of four metal-oxide-semiconductors; Fig. 4 is the circuit diagram of the second mirror current source in the present invention, is made up of two metal-oxide-semiconductors.
In Fig. 1, voltage Vr is produced by standard Bandgap circuit (see Fig. 2), this voltage and operational amplifier OP form a negative feedback control ring to control the drain-source voltage of the second metal-oxide-semiconductor M2 together with the first metal-oxide-semiconductor M1, and wherein voltage Vr is less than the drain-source saturation voltage V of the second metal-oxide-semiconductor M2
ds1, the leakage current of the second metal-oxide-semiconductor M2 can be expressed as:
In formula: β
1=μ
nc
oxw
1/ L
1, wherein, μ
nelectron mobility, C
oxthe oxide layer electric capacity of grid unit area, W
1and L
1width and the length of the second metal-oxide-semiconductor M2 respectively, V
gbe the grid voltage of the second metal-oxide-semiconductor M2, V
tit is the threshold voltage of the second metal-oxide-semiconductor M2.
On the other hand, the 3rd metal-oxide-semiconductor M3 is connected into diode form, works in saturation region, and its electric current is:
I
d2=β
2(V
g-V
ds3-V
t)
2, wherein, V
ds3it is the drain-source saturation voltage of the 3rd metal-oxide-semiconductor M3.
4th metal-oxide-semiconductor M4 works in linear zone, and its electric current is:
In formula: β
3=μ
nc
oxw
3/ L
3, wherein, μ
nelectron mobility, C
oxthe oxide layer electric capacity of grid unit area, W
3and L
3width and the length of the 4th metal-oxide-semiconductor M3 respectively
Consider: V
ds1=V
r, V
ds3, < < V
g, I
d1=I
d2=I
d3=I
out=I
o, can obtain:
I
o=k β V
r, wherein β=μ
nc
ox, k is only relevant to the breadth length ratio of the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3 and a 4th metal-oxide-semiconductor M4 constant term.
C
1be mos capacitance, its capacitance characteristic curve as shown in Figure 5.
As shown in Figure 6, in 301 moment, hysteresis comparator CP2 overturns the voltage waveform of its working point, and switch S P opens, and switch S N closes, and circuit is with I
outto mos capacitance C
1charge, as mos capacitance C
1on voltage V
outfrom V
trlbe charged to V
trhtime, overturn at 302 moment hysteresis comparator CP1, switch S P closes, and switch S N opens, and circuit is with I
outto mos capacitance C
1discharge, the duration of charging equals discharge time, can be expressed as:
Wherein W
1, L
1mos capacitance C
1wide and long, relative variable effect is little, V
trl, V
trhand V
rbe the reference voltage that BGR produces, k is a constant term, μ
nbe electron mobility, as can be seen from these variablees, t is substantially not with the constant of temperature and technique change.
Claims (3)
1. one kind produces the circuit of constant charging rate, comprise generating circuit from reference voltage, first mirror current source, second mirror current source, first comparer (CP1) and the second comparer (CP2), it is characterized in that, the output terminal of described generating circuit from reference voltage is connected with the negative input end of operational amplifier (OP), the output terminal of described operational amplifier (OP) is connected with the grid of the first metal-oxide-semiconductor (M1), the source electrode of described first metal-oxide-semiconductor (M1) is connected to the positive input terminal of described operational amplifier (OP), drain electrode is connected with the first mirror current source, the source electrode of described first metal-oxide-semiconductor (M1) is also connected with the drain electrode of the second metal-oxide-semiconductor (M2), the source ground of described second metal-oxide-semiconductor (M2), and grid is connected with the grid of the 3rd metal-oxide-semiconductor (M3), the drain electrode of described 3rd metal-oxide-semiconductor (M3) is connected with the first mirror current source, source electrode is connected with the drain electrode of the 4th metal-oxide-semiconductor (M4), the source ground of described 4th metal-oxide-semiconductor (M4), grid is connected with the grid of described 3rd metal-oxide-semiconductor (M3), wherein, the 3rd metal-oxide-semiconductor (M3) is connected into diode form, is operated in saturation region, and the 4th metal-oxide-semiconductor (M4) is operated in linear zone, described first mirror current source is also connected with the second mirror current source, described first mirror current source also be provided with two the first single-pole double-throw switch (SPDT)s (SP) and the second single-pole double-throw switch (SPDT) (SN) of mutually connecting between the second mirror current source, the positive input terminal of described first comparer (CP1) and the negative input end of the second comparer (CP2) are connected between the first single-pole double-throw switch (SPDT) (SP) and the second single-pole double-throw switch (SPDT) (SN), and are connected with mos capacitance (C1), the negative input end of described first comparer (CP1) is connected with high-order reference voltage, the positive input terminal of described second comparer (CP2) is connected with low level reference voltage, the described output terminal of the first comparer (CP1) is connected with the switch shutdown side of logical circuit, and the described output terminal of the second comparer (CP2) is connected with the switch open end of logical circuit.
2. the circuit of the constant charging rate of generation according to claim 1, is characterized in that, described first mirror current source is made up of four metal-oxide-semiconductors.
3. the circuit of the constant charging rate of generation according to claim 1, is characterized in that, described second mirror current source is made up of two metal-oxide-semiconductors.
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| CN201410548526.3A CN104460796B (en) | 2014-10-16 | 2014-10-16 | A kind of circuit producing constant charging rate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410548526.3A CN104460796B (en) | 2014-10-16 | 2014-10-16 | A kind of circuit producing constant charging rate |
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| CN104460796A true CN104460796A (en) | 2015-03-25 |
| CN104460796B CN104460796B (en) | 2016-04-13 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108566173A (en) * | 2018-06-11 | 2018-09-21 | 杨俊杰 | A kind of RC time constant correcting circuits using CMOS technology chip interior |
| CN109150141A (en) * | 2018-10-23 | 2019-01-04 | 上海艾为电子技术股份有限公司 | A kind of analog switching circuit and its method of controlling switch and device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7615981B2 (en) * | 2004-06-09 | 2009-11-10 | O2Micro International Limited | Boost converter with enhanced control capabilities of emulating an inductor current |
| CN101364122B (en) * | 2008-09-16 | 2010-08-25 | 智原科技股份有限公司 | Reference circuit for simultaneously supplying precision voltage and precision current |
| CN101840241B (en) * | 2010-03-30 | 2015-01-21 | 北京中星微电子有限公司 | Differential current sampling circuit and linear voltage regulator |
| CN103188177B (en) * | 2011-12-30 | 2016-09-07 | 意法半导体研发（上海）有限公司 | The method effectively reduced of the Electromagnetic Launching in LIN driver |
| CN202918029U (en) * | 2012-11-29 | 2013-05-01 | 无锡华润矽科微电子有限公司 | A charging circuit structure |
| CN203434663U (en) * | 2013-07-29 | 2014-02-12 | 无锡华润矽科微电子有限公司 | Constant-current constant-voltage charging control circuit |
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2014
- 2014-10-16 CN CN201410548526.3A patent/CN104460796B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108566173A (en) * | 2018-06-11 | 2018-09-21 | 杨俊杰 | A kind of RC time constant correcting circuits using CMOS technology chip interior |
| CN109150141A (en) * | 2018-10-23 | 2019-01-04 | 上海艾为电子技术股份有限公司 | A kind of analog switching circuit and its method of controlling switch and device |
| CN109150141B (en) * | 2018-10-23 | 2023-09-15 | 上海艾为电子技术股份有限公司 | Analog switch circuit and switch control method and device thereof |
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| CN104460796B (en) | 2016-04-13 |
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Effective date of registration: 20220919 Address after: Room 922, Building 2, No. 111 Xiangke Road, China (Shanghai) Pilot Free Trade Zone, Pudong New Area, Shanghai, 201210 Patentee after: Shanghai Fumanduo Semiconductor Co.,Ltd. Address before: 315336 No. 77 Binhai Second Road, Hangzhou Bay New Area, Ningbo City, Zhejiang Province Patentee before: NINGBO XINCHEN MICROELECTRONICS Co.,Ltd. |
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