CN104425585A - High electron mobility transistor - Google Patents

High electron mobility transistor Download PDF

Info

Publication number
CN104425585A
CN104425585A CN201410414271.1A CN201410414271A CN104425585A CN 104425585 A CN104425585 A CN 104425585A CN 201410414271 A CN201410414271 A CN 201410414271A CN 104425585 A CN104425585 A CN 104425585A
Authority
CN
China
Prior art keywords
electrode
electron mobility
high electron
mobility transistor
finger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410414271.1A
Other languages
Chinese (zh)
Other versions
CN104425585B (en
Inventor
邱显钦
童建凯
林恒光
杨治琟
王祥骏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Epistar Corp
Original Assignee
GUANGJIA PHOTOELECTRIC CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GUANGJIA PHOTOELECTRIC CO Ltd filed Critical GUANGJIA PHOTOELECTRIC CO Ltd
Priority to CN201811098772.8A priority Critical patent/CN109390396B/en
Publication of CN104425585A publication Critical patent/CN104425585A/en
Application granted granted Critical
Publication of CN104425585B publication Critical patent/CN104425585B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/157—Doping structures, e.g. doping superlattices, nipi superlattices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A high electron mobility transistor comprises a substrate, an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region, a matrix electrode structure arranged in the first region, and a plurality of first bridges electrically connecting the plurality of second electrodes. The matrix electrode structure comprises a plurality of first electrodes arranged on the epitaxial stack and a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes. One of the bridges is arranged between two of the second electrodes and crossed over one of the first electrodes.

Description

High Electron Mobility Transistor
Technical field
The present invention relates to a kind of High Electron Mobility Transistor (HEMT), particularly relate to the High Electron Mobility Transistor that one has sky bridge array (Air-bridge matrix, ABM) electrode structure.
Background technology
Aluminium gallium nitride alloy/GaN high electron mobility transistor is a high-power components of future generation with development potentiality.Due to the material behavior that they are superior, firm element characteristic can be maintained at high temperature under high pressure, thus at Schottky diode (Schottky barrier diodes, SBDs) attracted attention especially with field-effect transistor (Field effecttransistors, FETs) aspect.
In the upper technology forming gallium nitride material of silicon substrate (111), due to the characteristic of its low cost and superior large-sized wafer expandability, gradually by electronic component is adopted.But because the electric current under high voltage operation is jammed effect, application GaN high electron mobility transistor on a silicon substrate still has obvious thermal effect.
Summary of the invention
For solving the problem, the invention provides a kind of High Electron Mobility Transistor, comprising: a substrate; One extension lamination is positioned on substrate, comprises a first area and the second area around first area; An array electrode structure is positioned at first area; And multiple first electric bridge is electrically connected to multiple second electrode.Array electrode structure comprises: multiple first electrode is positioned in extension lamination and multiple second electrode is positioned in extension lamination and adjacent to multiple first electrode.Multiple first electric bridge one of them between two the second electrodes and across multiple first electrode one of them.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the High Electron Mobility Transistor of first embodiment of the invention;
Fig. 2 A is the High Electron Mobility Transistor vertical view of first embodiment of the invention;
Fig. 2 B ~ Fig. 2 C is the magnified partial view of Fig. 2 A of first embodiment of the invention;
Fig. 3 is the schematic diagram of the High Electron Mobility Transistor of second embodiment of the invention;
Fig. 4 A ~ Fig. 4 D is the photo of sample A ~ C that the present invention tests;
Fig. 5 A is the I of sample A ~ C that the present invention tests dS– V gSand gm – V gSperformance plot;
Fig. 5 B is the I of sample A ~ C that the present invention tests dS– V dSperformance plot.
Fig. 5 C is puncture voltage (off-state breakdown) performance plot of sample A ~ C that the present invention tests;
Fig. 6 A ~ Fig. 6 C is the thermal imagery figure of sample A ~ C that the present invention tests.
Symbol description
100 High Electron Mobility Transistor
10,20 small field effect transistors
101,201 substrates
102 extension lamination
102s extension lamination plane
103 array electrode structures
1021 first semiconductor layers
1022 second semiconductor layers
1023 the 3rd semiconductor layers
1024 channel layers
1025 accommodating layers
1026 cap layers
102A first area
102B second area
10311,10311d, 10311e, 10311f, 20,311 first electrodes
10321,10321e, 20,321 second electrodes
10331,10331e, 20331,20331 third electrodes
10313 first electronic padses
10323 second electronic padses
10333 third electrode pads
10311S geometric figure
1041,1041a first electric bridge
1042,1042a second electric bridge
10312a first finger electrode
10322a second finger electrode
10332a the 3rd finger electrode
1032110 first edges
1033110 second edges
204 conductive layers
205 insulator layers
2011 sunk areas
Embodiment
As illustrated, same or similar part is shown among accompanying drawing or specification with identical numbering embodiments of the invention with shown in accompanying drawing.
Fig. 1 shows the High Electron Mobility Transistor of first embodiment of the invention.High Electron Mobility Transistor 100 comprises multiple small field effect transistor (field effect transistor) 10, and wherein multiple small field effect transistor 10 is connected in parallel.High Electron Mobility Transistor 100 comprises: a substrate 101; One extension lamination 102 is formed on substrate 101; And an array electrode structure 103 is formed in extension lamination 102.Extension lamination 102 is contained in one first semiconductor layer 1021,1 second semiconductor layer 1022, the 3rd semiconductor layer 1023, channel layer 1024, accommodating layer 1025 that substrate 101 is sequentially grown up, and a cap layer 1026.
The material of substrate 101 can select the material being suitable as nitride semiconductor growing, such as silicon (Si), carborundum (SiC), gallium nitride (GaN) or sapphire (sapphire).First semiconductor layer 1021 thickness, between 150 ~ 200nm, can be a nucleating layer (nucleation layer), and comprises three or five races (III-V) material, such as aluminium nitride (AlN).When using silicon substrate, nucleating layer is formed in (111) plane of silicon substrate, and grow up along (0001) direction with the difference reducing silicon substrate and extension lamination lattice constant (lattice constant), contribute to the quality promoting extension lamination.Second layer semiconductor layer 1022 thickness is between 700 ~ 800nm, can be the gradient layer (grading layer) or a superlattice structure (superlattice structure) that are made up of three or five race's materials, a such as aluminium gallium nitride alloy (AlGaN) gradient layer, or one aluminium gallium nitride alloy/aluminium nitride superlattice structure.3rd semiconductor layer 1023 thickness, between 1 ~ 4 μm, can be with a resilient coating (buffer layer) of three or five race's material compositions, such as gallium nitride (GaN) material.
Channel layer 1024 thickness range, at 50 ~ 300nm, is formed on the 3rd semiconductor layer 1023, and has one first band gap.Accommodating layer 1025 thickness range, at 20 ~ 50nm, is formed on channel layer 1024, and has one second band gap, and the second band gap is high compared with the first band gap of channel layer 1024, represents that the lattice constant of accommodating layer 1025 is less than channel layer 1024.In the present embodiment, channel layer 1024 comprises InGaN (In xga (1-x)n), 0≤x<1, accommodating layer 1025 comprises aluminum indium gallium nitride (Al yin zga (1-z)n), 0<y<1,0≤z<1.Channel layer 1024 and accommodating layer 1025 self form spontaneous polarization (spontaneouspolarization), and because of its different lattice constants formation piezoelectric polarization (piezoelectric polarization), and then the heterojunction between channel layer 1024 and accommodating layer 1025 produces two dimension electrically (two dimensionelectron gas, 2DEG).It is special it is noted that channel layer 1024 and accommodating layer 1025 can be extrinsic semiconductor.In other embodiments, in order to strengthen spontaneous polarization and piezoelectric polarization effect, and promote the electric concentration of two dimension, channel layer 1024 and accommodating layer 1025 can be the semiconductor layers with doping, and the material of doping can be silane (SiH 4).Its thickness range of cap layer 1026, between 0.1 ~ 3nm, is formed on accommodating layer 1025, is made up of three or five race's materials, such as gallium nitride (GaN), stablizes, and avoid accommodating layer 1025 to be subject to surface damage in manufacture craft to maintain surface state.
Fig. 2 A shows the vertical view of first embodiment of the invention High Electron Mobility Transistor, and extension lamination 102 has a first area 102A, and a second area 102B is around first area 102A.Array electrode structure 103 is positioned on cap layer 1026 and first area 102A, comprises: multiple first electrode 10311; Multiple second electrode 10321 is adjacent to multiple first electrode 10311; Multiple third electrode 10331 is adjacent to multiple first electrode 10311 and multiple second electrode 10321.In the present embodiment, multiple first electrode 10311 can be grid (gate electrode), and contacts (schottky contact) in Xiao Ji with extension lamination 102; Multiple second electrode 10321 can be source electrode (source electrode), and with extension lamination 102 in ohmic contact (ohmic contact); Multiple third electrode 10331 can be drain electrode (drainelectrode), and with extension lamination 102 in ohmic contact.First electronic pads (pad) 10313, can be gate pad (gate bonding pad), to be electrically connected to multiple first electrode 10311; Second electronic pads 10323, can be source bonding pads (source bonding pad), to be electrically connected to multiple second electrode 10321; And third electrode pad 10333, can be drain bonding pad (drain bonding pad), to be electrically connected to multiple third electrode 10331, wherein the first electronic pads 10313, second electronic pads 10323 and third electrode pad 10333 are all positioned at second area 102B.Second electrode 10321 one of them and third electrode 10331 one of them can be titanium (Ti)/aluminium (Al)/titanium (Ti)/gold (Au), titanium (Ti)/aluminium (Al)/nickel (Ni)/gold (Au) or the stacking composition of other metal materials, wherein the second electrode 10321 and third electrode 10331, can be titanium (Ti)/aluminium (Al)/titanium (Ti)/gold (Au), titanium (Ti)/aluminium (Al)/nickel (Ni)/gold (Au) or the stacking composition of other metal materials simultaneously.First electrode 10311 one of them can be nickel (Ni)/gold (Au) or the stacking composition of other metal materials.First electronic pads 10313, second electronic pads 10323 and third electrode pad 10333 can be metal material, such as gold (Au) or aluminium (Al) composition.As shown in Figure 2 A, several first electrode 10311 forms a geometric figure 10311S, can be rectangle.Geometric figure 10311S is around wherein one second electrode 10321 or third electrode 10331.Should be noted, multiple first electrode 10311, and multiple second electrode 10321 or multiple third electrode 10331 are positioned on different hurdles or row.
Fig. 2 B and Fig. 2 C shows the magnified partial view of first embodiment of the invention Fig. 2 A.Multiple first electric bridge 1041 is electrically connected to multiple second electrode 10321, and multiple second electric bridge 1042 is electrically connected to multiple third electrode 10331, wherein the first electric bridge 1041 and the second electric bridge 1042 can be metal material as gold (Au) form.As shown in Figure 1, the first electric bridge 1041a between two the second electrodes 10321, and across the first electrode 10311d, the second electric bridge 1042a between two third electrodes 10331, and across the first electrode 10311e.In the present embodiment, medium between the extension lamination plane 102s of the first electric bridge 1041, second electric bridge 1042 and extension lamination 102 can be air, to complete dissipation of heat effect, therefore array electrode structure 103 can be described as sky bridge array (air-bridge matrix) electrode structure.But, air is unrestricted at this as medium.In other embodiments, an insulating barrier can be positioned at the surface of extension lamination, and first and second electric bridge is positioned on insulating barrier, and wherein insulating barrier can be a dissipation of heat material, as silicon dioxide (SiO 2) (not shown).
Shown in Fig. 2 B and Fig. 2 C, array electrode structure 103 also comprises multiple first finger electrode 10312, multiple second finger electrode 10322 and multiple 3rd finger electrode 10332, wherein the material of multiple first finger electrode 10312 can be identical with the first electrode 10311, the material of multiple second finger electrode 10322 can be identical with the second electrode 10321, and the material of multiple 3rd finger electrode 10332 can be identical with third electrode 10331.The first many finger electrodes 10312 stretches out from the first electrode 10311f, and the first finger electrode 10312a is electrically connected the first electrode 10311f and the first electronic pads 10313 (as shown in Figure 2 B).Multiple second finger electrode 10322 stretches out from the second electrode 10321e, and the second finger electrode 10322a is electrically connected the second electrode 10321e and the second electronic pads 10323 (as shown in Figure 2 C).Multiple 3rd finger electrode 10332 stretches out from third electrode 10331e, and the 3rd finger electrode 10332a is electrically connected third electrode 10331e and third electrode pad 10333.Wherein, comparatively the second finger electrode 10322b and the 3rd finger electrode 10332b is long for the length of the first finger electrode 10312a; First finger electrode 10312a is around the second finger electrode 10322b and the 3rd finger electrode 10332a; First finger electrode 10312a is between the second finger electrode 10322b and the 3rd finger electrode 10332b, and wherein the first finger electrode 10312a is comparatively close to the 3rd finger electrode 10332b, and comparatively away from the second finger electrode 10322b.Moreover the second finger electrode 10322 vertically extends from the first edge 1032110, the 3rd finger electrode 10332 vertically extends from the second edge 1033110.In embodiments of the present invention, array electrode structure and electric bridge for increasing conductance and thermal conductance region, and then reduce drain-source conducting resistance R dS_on, increase current density, and better electric current scatters.
Although the first embodiment of High Electron Mobility Transistor is as implied above, the present invention is not limited in the first embodiment.
Figure 3 shows that a small field effect transistor (field effecttransistor) of second embodiment of the invention.In a second embodiment, small field effect transistor 20 similar first embodiment, except small field effect transistor 20 also comprises under a sunk area 2011 is positioned at first area 102A.Sunk area 2011, between the second electrode 20321 and third electrode 20331, to avoid the generation of leakage current paths, and is positioned at substrate 201.One conductive layer 204 is formed in sunk area 2011.One insulating barrier 205 is between substrate 201 and conductive layer 204, and between extension lamination 102 and conductive layer 204, and insulating barrier 205 can directly contact extension lamination 102.Small field effect transistor 20 comprises conductive layer 204 and insulating barrier 205, can have improving device mechanical strength, increases heat radiation and improve the effect of puncture voltage.In the present embodiment, the first electrode 20311 is D1 with the distance of third electrode 20331, and sunk area 2011 width is W1, and wherein W1 is greater than D1, to avoid leakage current paths and to improve puncture voltage.In other embodiments, W1 can be less than or equal to D1.Conductive layer 204 comprises a metal material, such as copper (Cu), and wherein the thickness of conductive layer 204 is greater than 0.1 μm.Insulating barrier 205 comprises silicon dioxide (SiO 2), wherein the thickness of insulating barrier 205 is greater than 50nm.In other embodiments, substrate can be removed completely, and under conductive layer can be positioned at extension lamination, insulating barrier can be positioned between extension lamination and conductive layer, and directly contacts extension lamination.
Shown the experimental result of sample A ~ C under different electrode structure and board structure of the present invention's experiment by table 1, wherein gate electrode width Wg is the finger electrode total length on gate electrode.Shown in Fig. 4 A ~ Fig. 4 D, sample A comprises traditional many finger-like (multi-finger; MF) electrode structure, gate electrode width Wg is 40mm.Sample B has comprised bridge array (air-bridge matrix) electrode structure, and gate electrode width is 22.8mm.Sample C has comprised bridge array electrode structure, gate electrode width is 22.8mm, and the substrate of sample C is removed (as shown in Figure 4 D), and one deck 300nm silicon dioxide and one deck 20 μm of copper are had to be positioned at (as shown in Figure 4 C) below extension lamination.The active area area of above-mentioned sample A ~ C is 1.5625 mm 2(1.25mm x 1.25mm).
As the I of the present invention's experiment in Fig. 5 A dS– V gSand gm – V gSshown in performance plot, when operating in drain-source voltage V dSfor 5V, gate source voltage V gSduring for-3V to 1V, sample C reaches the highest drain-source current I dSfor 4.81A.Due to the cause of many finger electrode structure, the electric current of sample A be one-dimensional square to; Due to the cause of empty bridge array electrode structure, the electric current of sample B is two-dimensional directional.In the essence improvement of current density, sample B is that electric current is from one-dimensional square to being transformed into two-dimensional directional relative to sample A.In addition, due to the cause that substrate is removed, compared to the drain-source current I of sample B dSfor 4.7A, the drain-source current I of sample C dS4.81A can be risen to.The critical voltage (threshold voltage) of all sample A ~ C is all-2.3V.
Be the I of the present invention's experiment as shown in Figure 5 B dS– V dSperformance plot, wherein gate source voltage V gSfor 1V to-3V, drain-source conducting resistance R dS_oncan be determined when gate source voltage is 0V.The drain-source conducting resistance R of sample B dS_onlower, be attributable to the minimizing that the improvement of sample B current density and electric current are jammed.The electric current of sample A be one-dimensional square to, under high electric field operation, electric current is jammed and occurs in drain electrode.But the electric current of sample B is two-dimensional directional, electric current can be disperseed and be reduced electric current to be jammed.Low next compared with sample B of the drain-source conducting resistance of sample C, because substrate is removed, increases dissipation of heat effect.
Be puncture voltage (off-state breakdown) performance plot of the present invention's experiment as shown in Figure 5 C, wherein operating voltage V gSfor-8V, V dSfor 0V to 800V.Puncture voltage V bRvoltage when (off-state breakdownvoltage) leakage current be defined as between source-drain electrode is 1mA, the most high-breakdown-voltage V that sample C presents bRfor 659V.
Be the thermal imagery figure of sample A ~ C of the present invention, wherein drain-source voltage V as figs. 6 a to 6 c dSfor 5V, leakage current I dbe limited to 1A, the duration is 1 minute.The drain electrode temperature of sample A under 100 μm of silicon substrates is 187.5 degree Celsius.The drain electrode temperature of sample B under 100 μm of silicon substrates reduces to 120.2 degree Celsius, and this is because the more traditional many finger electrode structure of heat radiation of empty bridge array electrode structure are good factor.When using sky bridge array electrode structure and remove silicon substrate, temperature can be down to 85.9 degree Celsius.Prove that empty bridge array electrode structure matching removes silicon substrate thus, significantly can eliminate the self-heating effect (self-heating effect) when drain-source voltage is high voltage.
It is noted that above-described embodiment scope of the present invention of letting loose, any adjustment not exceeding spirit of the present invention and do, all may maybe ought to covered in the present invention.
Table 1

Claims (10)

1. a High Electron Mobility Transistor, comprises:
Substrate;
Extension lamination, is positioned on this substrate, comprises first area and the second area around this first area;
Array electrode structure, is positioned at this first area, comprises: multiple first electrode, is positioned in this extension lamination; And multiple second electrode, be positioned in this extension lamination, and adjacent to the plurality of first electrode; And
Multiple first electric bridge is electrically connected to the plurality of second electrode, the plurality of first electric bridge one of them between two the plurality of second electrodes, and across the plurality of first electrode one of them.
2. High Electron Mobility Transistor as claimed in claim 1, wherein this array electrode structure also comprise multiple first finger electrode extend from the plurality of first electrode one of them; And/or multiple second finger electrode extend from the plurality of second electrode one of them.
3. High Electron Mobility Transistor as claimed in claim 2, wherein the plurality of first finger electrode one of them around the plurality of second finger electrode one of them; And/or one of them length of the plurality of first finger electrode is greater than one of them length of the plurality of second finger electrode.
4. High Electron Mobility Transistor as claimed in claim 1, wherein this array electrode structure also comprises multiple third electrode adjacent to the plurality of first electrode and the plurality of second electrode.
5. High Electron Mobility Transistor as claimed in claim 4, also comprises multiple second electric bridge and is electrically connected to the plurality of third electrode; And/or wherein the plurality of first electrode is grid, the plurality of second electrode is source electrode, and the plurality of third electrode is drain electrode.
6. High Electron Mobility Transistor as claimed in claim 5, wherein the plurality of second electric bridge one of them between two the plurality of third electrodes and across the plurality of first electrode one of them.
7. High Electron Mobility Transistor as claimed in claim 4, wherein this array electrode structure also comprise multiple first finger electrode extend from the plurality of first electrode one of them, and/or multiple 3rd finger electrode extend from the plurality of third electrode one of them.
8. High Electron Mobility Transistor as claimed in claim 7, also comprises third electrode pad, is positioned at this second area, wherein the plurality of 3rd finger electrode one of them be electrically connected the plurality of third electrode and this third electrode pad one of them; And/or the plurality of first finger electrode one of them around the plurality of 3rd finger electrode one of them.
9. High Electron Mobility Transistor as claimed in claim 4, wherein more than the plurality of first electrode of two form a geometric figure around this second electrode and this third electrode one of them; And/or the plurality of first electrode and the plurality of second electrode or the plurality of third electrode are positioned on different hurdles or row.
10. High Electron Mobility Transistor as claimed in claim 1, wherein this substrate comprises:
Sunk area, under being positioned at this first area;
Conductive layer, is positioned at this sunk area; And
Insulating barrier, between this conductive layer and this substrate.
CN201410414271.1A 2013-08-21 2014-08-21 High electron mobility transistor Active CN104425585B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811098772.8A CN109390396B (en) 2013-08-21 2014-08-21 High electron mobility transistor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201361868423P 2013-08-21 2013-08-21
US61/868,423 2013-08-21
US14/328,241 2014-07-10
US14/328,241 US9331154B2 (en) 2013-08-21 2014-07-10 High electron mobility transistor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201811098772.8A Division CN109390396B (en) 2013-08-21 2014-08-21 High electron mobility transistor

Publications (2)

Publication Number Publication Date
CN104425585A true CN104425585A (en) 2015-03-18
CN104425585B CN104425585B (en) 2018-10-23

Family

ID=52479588

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201811098772.8A Active CN109390396B (en) 2013-08-21 2014-08-21 High electron mobility transistor
CN201410414271.1A Active CN104425585B (en) 2013-08-21 2014-08-21 High electron mobility transistor

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201811098772.8A Active CN109390396B (en) 2013-08-21 2014-08-21 High electron mobility transistor

Country Status (3)

Country Link
US (2) US9331154B2 (en)
CN (2) CN109390396B (en)
TW (2) TWI667794B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9685438B2 (en) 2015-08-19 2017-06-20 Raytheon Company Field effect transistor having two-dimensionally distributed field effect transistor cells
US9698144B2 (en) 2015-08-19 2017-07-04 Raytheon Company Field effect transistor having loop distributed field effect transistor cells
US9577048B1 (en) * 2015-09-24 2017-02-21 Epistar Corporation Heterostructure field-effect transistor
EP3613082A4 (en) * 2017-04-10 2021-05-12 The Government of the United States of America as represented by the Secretary of the Navy Diamond air bridge for thermal management of high power devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1918712A (en) * 2004-02-12 2007-02-21 国际整流器公司 Integrated iii-nitride power devices
US20080277698A1 (en) * 2006-07-12 2008-11-13 Kabushiki Kaisha Toshiba Field effect transistor
CN101371345A (en) * 2006-07-12 2009-02-18 株式会社东芝 Semiconductor device for high frequency
CN102195502A (en) * 2010-03-02 2011-09-21 松下电器产业株式会社 Semiconductor device
CN102637735A (en) * 2011-02-14 2012-08-15 富士通株式会社 Compound semiconductor device and method for manufacturing the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278579A (en) * 1990-03-28 1991-12-10 Nec Corp Semiconductor device
US5412239A (en) * 1993-05-14 1995-05-02 Siliconix Incorporated Contact geometry for improved lateral MOSFET
JPH07263665A (en) * 1994-03-22 1995-10-13 Nippondenso Co Ltd Semiconductor device
US6084266A (en) * 1998-03-02 2000-07-04 Vanguard International Semiconductor Corporation Layout of semiconductor devices to increase the packing density of a wafer
US6548839B1 (en) * 2002-02-20 2003-04-15 National Semiconductor Corporation LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability
US6727547B1 (en) * 2002-10-08 2004-04-27 National Semiconductor Corporation Method and device for improving hot carrier reliability of an LDMOS transistor using drain ring over-drive bias
US7166867B2 (en) * 2003-12-05 2007-01-23 International Rectifier Corporation III-nitride device with improved layout geometry
JP4316597B2 (en) * 2006-09-15 2009-08-19 株式会社東芝 Semiconductor device
CN201007770Y (en) * 2006-09-29 2008-01-16 上海广电光电子有限公司 Thin-film transistor array substrates for LCD
CN101330009A (en) * 2007-06-20 2008-12-24 中国科学院微电子研究所 Method for drawing off sub-micron HBT emitter electrode/HEMT gate air bridge
JP2009164278A (en) * 2007-12-28 2009-07-23 Mitsumi Electric Co Ltd Mos transistor and semiconductor integrated circuit device using the same
WO2010013195A1 (en) * 2008-07-28 2010-02-04 Nxp B.V. Integrated circuit and method for manufacturing an integrated circuit
US9029866B2 (en) * 2009-08-04 2015-05-12 Gan Systems Inc. Gallium nitride power devices using island topography
CA2769940C (en) * 2009-08-04 2016-04-26 Gan Systems Inc. Island matrixed gallium nitride microwave and power switching transistors
WO2011039800A1 (en) * 2009-09-29 2011-04-07 株式会社 東芝 Semiconductor device
US8304812B2 (en) * 2010-02-24 2012-11-06 Panasonic Corporation Terahertz wave radiating element
JP5649347B2 (en) * 2010-07-20 2015-01-07 住友電工デバイス・イノベーション株式会社 Semiconductor device
CN102623496B (en) * 2011-01-27 2014-11-05 无锡华润上华半导体有限公司 Matrix type mos field effect transistor
JP5866769B2 (en) * 2011-02-16 2016-02-17 富士通株式会社 Semiconductor device, power supply device and amplifier
CN102270659B (en) * 2011-08-11 2012-09-26 中国科学院微电子研究所 Multi-gate GaN high electron mobility transistors (HEMTs)
US20130095650A1 (en) * 2011-10-14 2013-04-18 Neofocal Systems, Inc. System And Method For Constructing Waffle Transistors
CN102522378A (en) * 2011-11-29 2012-06-27 中国电子科技集团公司第五十五研究所 Distributed image high power tube core
JP2013183062A (en) * 2012-03-02 2013-09-12 Toshiba Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1918712A (en) * 2004-02-12 2007-02-21 国际整流器公司 Integrated iii-nitride power devices
US20080277698A1 (en) * 2006-07-12 2008-11-13 Kabushiki Kaisha Toshiba Field effect transistor
CN101371345A (en) * 2006-07-12 2009-02-18 株式会社东芝 Semiconductor device for high frequency
CN102195502A (en) * 2010-03-02 2011-09-21 松下电器产业株式会社 Semiconductor device
CN102637735A (en) * 2011-02-14 2012-08-15 富士通株式会社 Compound semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
TW201513344A (en) 2015-04-01
US9627523B2 (en) 2017-04-18
US20160233326A1 (en) 2016-08-11
TWI634664B (en) 2018-09-01
US9331154B2 (en) 2016-05-03
CN109390396A (en) 2019-02-26
CN109390396B (en) 2022-03-29
TWI667794B (en) 2019-08-01
US20150054034A1 (en) 2015-02-26
TW201836151A (en) 2018-10-01
CN104425585B (en) 2018-10-23

Similar Documents

Publication Publication Date Title
JP6049674B2 (en) Dual gate type III-V compound transistor
JP5793120B2 (en) Composite semiconductor device having SOI substrate with integrated diode
CN107359196B (en) Semiconductor device with a plurality of semiconductor chips
JP6025213B2 (en) HEMT with floating and grounded substrate area
JP2007059595A (en) Nitride semiconductor element
WO2014026018A1 (en) Iii-nitride enhancement mode transistors with tunable and high gate-source voltage rating
US9076850B2 (en) High electron mobility transistor
KR20140042470A (en) Normally off high electron mobility transistor
TWI621265B (en) Semiconductor device and method of fabrication the same
US8907377B2 (en) High electron mobility transistor and method of manufacturing the same
US20150263155A1 (en) Semiconductor device
US9627523B2 (en) High electron mobility transistor
CN103003930B (en) Field-effect transistor
JP2007081096A (en) Semiconductor device
JP5415668B2 (en) Semiconductor element
JP5721782B2 (en) Semiconductor device
KR102005451B1 (en) High Electron Mobility Transistor
RU136238U1 (en) HETEROSTRUCTURAL MODULATED-ALLOYED FIELD TRANSISTOR
KR102029807B1 (en) hetero junction field effect transistor
Chiu et al. High performance micromachined GaN on Si HEMT with backside diamondlke-carbon/titanium heat dissipation layer
Yang et al. Micromachined p-GaN gate normally-off power HEMT with an optimized air-bridge matrix layout design
RU2534437C1 (en) Heterostructure modulated-doped field-effect transistor
KR101887535B1 (en) High electron mobility transistor and method of manufacturing the same
CN104347695A (en) Semiconductor device for increasing longitudinal voltage endurance capability of device
Selvaraj et al. Enhancing the breakdown voltage by growing 9 µm thick AlGaN/GaN HEMTs on 4 inch silicon

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20161027

Address after: Hsinchu City, Taiwan, China

Applicant after: Jingyuan Optoelectronics Co., Ltd.

Address before: Taichung City, Taiwan, China

Applicant before: Guangjia Photoelectric Co., Ltd.

GR01 Patent grant
GR01 Patent grant