CN104425583B - Semiconductor device and its manufacture method - Google Patents
Semiconductor device and its manufacture method Download PDFInfo
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- CN104425583B CN104425583B CN201310364265.5A CN201310364265A CN104425583B CN 104425583 B CN104425583 B CN 104425583B CN 201310364265 A CN201310364265 A CN 201310364265A CN 104425583 B CN104425583 B CN 104425583B
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Abstract
The invention discloses a kind of semiconductor device and its manufacture method.Semiconductor device includes a substrate, one first doped region (doping region), one first trap (well), one first heavily doped region (heavily doping region), one second heavily doped region, one the 3rd heavily doped region and a resistive element.First doped region is arranged on substrate, and the first trap is arranged in the first doped region.First heavily doped region is arranged in the first trap.Second heavily doped region is arranged in the first trap, and the second heavily doped region is spaced apart with the first heavily doped region.3rd heavily doped region is arranged in the first doped region, and the second heavily doped region is electrically connected at the 3rd heavily doped region via resistive element.Substrate, the first trap and the second heavily doped region have one first dopant profile, and the first doped region, the first heavily doped region and the 3rd heavily doped region have one second dopant profile, and the first dopant profile is complementary to the second dopant profile.
Description
Technical field
Present invention relates to a kind of semiconductor device and its manufacture method, and in particular to one kind with low
The semiconductor device and its manufacture method of substrate leakage.
Background technology
With the development of semiconductor technology, various semiconductor element continues to introduce new.For example, memory, crystal
The elements such as pipe, diode are widely used in various electronic device.
In the development of semiconductor technology, researcher constantly attempts to be improved for various elements, e.g. contracts
The subjects under discussion such as small size, increase/drop low start voltage, increase/reduction breakdown voltage, reduction electric leakage, electrostatic protection.
The content of the invention
Present invention relates to a kind of semiconductor device and its manufacture method.In embodiment, semiconductor device includes
One thyristor, the base stage of the equivalent N PN transistors of thyristor are electrically connected at collector (quite via a resistive element
In the base stage of equivalent PNP transistor) so that make that there is voltage difference between the two, therefore can be equivalent by unwanted conduct current
The collector of NPN transistor, and then the substrate leakage (substrate leakage) of semiconductor device is reduced, while also improve quiet
Discharge of electricity (electrostatic discharge, ESD) protection effect.
An embodiment of content according to the present invention, is to propose a kind of semiconductor device.Semiconductor device includes a substrate, one
First doped region (doping region), one first trap (well), one first heavily doped region (heavily doping
Region), one second heavily doped region, one the 3rd heavily doped region and a resistive element.First doped region is arranged on substrate, the
One trap is arranged in the first doped region.First heavily doped region is arranged in the first trap.Second heavily doped region is arranged in the first trap,
Second heavily doped region is spaced apart with the first heavily doped region.3rd heavily doped region is arranged in the first doped region, and second is heavily doped
Miscellaneous area is electrically connected at the 3rd heavily doped region via resistive element.Substrate, the first trap and the second heavily doped region have one first to mix
Miscellaneous kenel, the first doped region, the first heavily doped region and the 3rd heavily doped region have one second dopant profile, and the first dopant profile is mutual
Mend in the second dopant profile.
Another embodiment of content according to the present invention, is to propose a kind of semiconductor device.Semiconductor device includes a lock stream
Transistor (thyristor) and a resistive element.Thyristor has an equivalent NPN transistor and an equivalent PNP crystalline substances
Body pipe.The base stage of equivalent N PN transistors is electrically connected at the base stage of equivalent PNP transistor via resistive element.
The another embodiment of content according to the present invention, is to propose a kind of manufacture method of semiconductor device.Semiconductor device
Manufacture method comprise the following steps.One substrate is provided；One first doped region is formed on substrate；One first trap is formed in first
In doped region；One first heavily doped region is formed in the first trap；One second heavily doped region is formed in the first trap, the second heavy doping
Area is spaced apart with the first heavily doped region；One the 3rd heavily doped region is formed in the first doped region；And form resistance member
Part, the second heavily doped region are electrically connected at the 3rd heavily doped region via resistive element.Substrate, the first trap and the second heavily doped region tool
There is one first dopant profile, the first doped region, the first heavily doped region and the 3rd heavily doped region have one second dopant profile, and first
Dopant profile is complementary to the second dopant profile.
More preferably understand to have to the above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinate institute
Accompanying drawings, are described in detail below：
Brief description of the drawings
Fig. 1 illustrates the profile of the semiconductor device of first embodiment.
Fig. 2A~Fig. 2 D illustrate the flow chart of the manufacture method of the semiconductor element of first embodiment.
Fig. 3 illustrates the profile of the semiconductor device of second embodiment.
Fig. 4 A~Fig. 4 F illustrate the flow chart of the manufacture method of the semiconductor element of second embodiment.
Fig. 5 illustrates the profile of the semiconductor device of 3rd embodiment.
Fig. 6 illustrates the profile of the semiconductor device of fourth embodiment.
Fig. 7 illustrates the equivalent transistor schematic diagram of the semiconductor device of second embodiment.
Fig. 8 illustrates the equivalent circuit diagram of the semiconductor device of some embodiments of content according to the present invention.
Fig. 9 illustrates the I-V curve figure of the semiconductor device of second embodiment.
【Symbol description】
100、200、300、400：Semiconductor device
110P：Substrate
120：Epitaxial layer
121P：First trap
123P：Second trap
125N：3rd trap
130N、230N：First doped region
141N：First heavily doped region
143P：Second heavily doped region
145N：3rd heavily doped region
147P：4th heavily doped region
150：Resistive element
160、161：Field oxide
171：First electrode
172：Second electrode
173：3rd electrode
181、183：Equivalent N PN transistors
231N：Buried regions
I、II：Curve
MLl、ML2：Metal layer
Vanode：Anode voltage
Embodiment
It is to propose a kind of semiconductor device and its manufacture method in the embodiment of this content of the invention.In embodiment, partly lead
Body device includes a thyristor, and the base stage of the equivalent N PN transistors of thyristor is electrically connected via a resistive element
In collector (equivalent to the base stage of equivalent PNP transistor) so that make that there is voltage difference between the two, therefore can be by unwanted electricity
Conductance and then reduces the substrate leakage of semiconductor device, while also improves electrostatic discharge protective to the collector of equivalent N PN transistors
Effect.However, embodiment only to illustrate as example, can't limit the scope of the invention to be protected.In addition, in embodiment
Schema be to omit the element wanted of part, to clearly show that the technical characterstic of the present invention.
First embodiment
Fig. 1 is refer to, it illustrates the profile of the semiconductor device 100 of first embodiment.Semiconductor device 100 includes lining
Bottom 110P, the first doped region (doping region) 130N, the first trap (well) 121P, the first heavily doped region (heavily
Doping region) 141N, the second heavily doped region 143P, the 3rd heavily doped region 145N and resistive element 150.
The material of substrate 110P is, for example, P-type silicon or N-type silicon.First doped region 130N is arranged on substrate 110P, and first
Trap 121P is arranged in the first doped region 130N.First doped region 130N and the first trap 121P is, for example, p-type trap (P type
Well) or N-type trap (N type well), the first doped region 130N also can be for example N-type deep trap (deep N type well),
First trap 121P also can be for example p-type trap/p-type heavy doping buried regions (P+buried layer) lamination layer, p-type heavily doped layer (P+
Implant layer), N-type trap/N-type heavy doping buried regions (N+buried layer) lamination layer, N-type heavily doped layer (N+
Implant layer) or N-type deep trap.
First heavily doped region 141N is arranged in the first trap 121P, and the second heavily doped region 143P is arranged at the first trap 121P
Interior, the second heavily doped region 143P and the first heavily doped region 141N are asked to separate and.3rd heavily doped region 145N is arranged at the first doping
In area 130N.The doping concentration of first heavily doped region 141N, the second heavily doped region 143P and the 3rd heavily doped region 145N are more than the
The doping concentration of one trap 121P and the first doped region 130N, to provide good Ohmic contact (Ohmic contact).First weight
Doped region 141N, the second heavily doped region 143P and the 3rd heavily doped region 145N are, for example, p-type heavily doped region (P type heavily
Doping region, P+) or N-type heavily doped region (N type heavily doping region, N+).
Second heavily doped region 143P is electrically connected at the 3rd heavily doped region 145N via resistive element 150.Resistive element 150
An e.g. polysilicon layer.
It (is, for example, p-type or N that substrate 110P, the first trap 121P and the second heavily doped region 143P, which have one first dopant profile,
Type), the first doped region 130N, the first heavily doped region 141N and the 3rd heavily doped region 145N have one second dopant profile (such as
It is N-type or p-type), the first dopant profile is complementary to the second dopant profile.In the present embodiment, the first dopant profile is p-type, the
Two dopant profiles are N-type.
As shown in Figure 1, in embodiment, semiconductor device 100 more may include field oxide (field oxide, FOX) 161,
Field oxide 161 is arranged on the first trap 121P, and between the first heavily doped region 141N and the second heavily doped region 143P,
And both are spaced apart by this.In addition, in the semiconductor device 100 of the present embodiment, it more may include field oxide 160, field oxidation
Layer 160 may be disposed on the adjoiner of the first trap 121P and the first doped region 130N.The material of field oxide 160 and 161 is for example
It is silica (Si02), its structure is, for example, zone oxidation silicon (LOCOS) as shown in Figure 1, can also be shallow trench isolation
(STI)。
In embodiment, resistive element 150 can be arranged in the internal structure of semiconductor device 100, or is arranged at one
In external structure.In the present embodiment, as shown in Figure 1, polysilicon layer (resistive element 150) is arranged at the field on the first trap 121P
In oxide layer 161, compared to external structure is arranged on, resistive element 150 is arranged in the internal structure of semiconductor device 100,
Integrally-built size can effectively be reduced.
In embodiment, as shown in Figure 1, semiconductor device 100 more may include the second trap 123P.Second trap 123P is arranged at lining
On the 110P of bottom.First doped region 130N is arranged between the first trap 121P and the second trap 123P, and the second trap 123P has first to mix
Miscellaneous kenel.
In embodiment, as shown in Figure 1, semiconductor device 100 more may include the 4th heavily doped region 147P.4th heavily doped region
147P is arranged in the second trap 123P, and the 4th heavily doped region 147P has the first dopant profile.
As shown in Figure 1, first electrode 171, the first heavily doped region 141N, the first trap 121P, the second heavily doped region 143P, electricity
The path of resistance element 150 and second electrode 172 forms an insulated transistor (isolation diode)., will in forward bias voltage drop
The impedance of at least 0.7 volt (V)；In reverse bias, 30 volts of impedance will have at least.
In addition, can more be electrically connected the first heavily doped region 141N in first electrode 171, electrically connect via resistive element 150
Meet the second heavily doped region 143P and be electrically connected to the 3rd heavily doped region 145N at the same time in second electrode 172, second electrode 172, with
And the 4th heavily doped region 147P is electrically connected in the 3rd electrode 173.The e.g. cathode of first electrode 171, second electrode 172
An anode in this way, the 3rd electrode 173 are, for example, a ground terminal.Due to resistive element 150 so that where the 3rd heavily doped region 145N
The first doped region 130N and the first trap 121P between there is voltage difference so that in forward bias voltage drop, the first doped region 130N's
Current potential is higher than the current potential of the first trap 121P, can be by unwanted conduct current second electrode 172, and then reduces substrate leakage
(substrate leakage), while also improve static discharge (electrostatic discharge, ESD) protection effect.
Detailed mechanism of action will be in this paper paragraphs below discussion.
In addition, the configuration of polysilicon layer (resistive element 150), except with reduction substrate leakage such as described previously herein and carrying
Outside the effect of high electrostatic discharge protection, since polysilicon layer still has the effect of field effect battery plate, still to improve insulating crystal
The breakdown voltage of pipe.
Fig. 2A~Fig. 2 D are refer to, it illustrates the flow chart of the manufacture method of the semiconductor element 100 of first embodiment.It is first
First, as shown in Figure 2 A, there is provided substrate 110P.
Then, as shown in Figure 2 B, the first doped region 130N is formed on substrate 110P, and forms the first trap 121P in the
In one doped region 130N.In embodiment, the second trap 123P can be more formed on substrate 110P, the first doped region 130N is formed at
Between one trap 121P and the second trap 123P.In embodiment, the first doped region 130N, the first trap 121P and the second trap 123P are, for example,
Made with three traps (triple well) technique, without extra epitaxial step is increased, manufacture cost can be reduced.
Then, as shown in Figure 2 C, formed field oxide 161 in the first trap 121P on and be located at the first heavily doped region 141N and
Between second heavily doped region 143P, field oxide 160 can be also formed in the first trap 121P and the adjoiner of the first doped region 130N
On.
Then, as shown in Figure 2 C, the first heavily doped region 141N and the second heavily doped region 143P is formed in the first trap 121P,
Second heavily doped region 143P is spaced apart with the first heavily doped region 141N, forms the 3rd heavily doped region 145N in the first doped region
In 130N.In embodiment, the 4th heavily doped region 147P can be also formed in the second trap 123P.
Then, as shown in Figure 2 D, resistive element 150 is formed on field oxide 161., can also be in another embodiment
Formed before heavily doped region 141N, 143P, 145N and 147P, form electric open component 150 on field oxide 161.In embodiment,
Resistive element 150 is, for example, to be formed by a polysilicon layer.The semiconductor of the present embodiment can be smoothly completed through above-mentioned steps
Device 100.
Second embodiment
Fig. 3 is refer to, it illustrates the profile of the semiconductor device 200 of second embodiment.The semiconductor dress of the present embodiment
Put 200 designs for being the first doped region 230N with 100 difference of semiconductor device of first embodiment, remaining something in common
It is not repeated to describe.
As shown in figure 3, the first doped region 230N includes buried regions (buried layer) 231N and the 3rd trap 125N.Implement
In example, the doping concentration of buried regions 231N is more than the doping concentration of the 3rd trap 125N.Buried regions 231N is arranged under the first trap 121P
Side, the 3rd trap 125N is arranged on buried regions 231N, and the 3rd trap 125N is arranged between the first trap 121P and the second trap 123P.This
The material of the buried regions 231N and the 3rd trap 125N of embodiment are substantially the same.In the present embodiment, buried regions 231N is, for example, that a N-type is buried
Layer (N type buried layer, NBL), a N-type epitaxy layer (N-epi), a N-type deep trap (deep N type well) or
One n-type doping lamination layer (multiple N+stacked layer).
Fig. 4 A~Fig. 4 F are refer to, it illustrates the flow chart of the manufacture method of the semiconductor element 200 of second embodiment.It is first
First, as shown in Figure 4 A, there is provided substrate 110P.
Then, as shown in Figure 4 B, buried regions 231N is formed on substrate 110P.In embodiment, buried regions 231N is formed at predetermined
The lower section of the first trap 121P formed.
Then, as shown in Figure 4 C, epitaxial layer 120 is formed on substrate 110P and buried regions 231N.
Then, as shown in Figure 4 D, the first trap 121P and the 3rd trap 125N is formed on buried regions 231N, buried regions 231N and the 3rd
Trap 125N forms the first doped region 230N.In embodiment, the second trap 123P can be more formed on substrate 110P, the 3rd trap 125N shapes
Into between the first trap 121P and the second trap 123P.In embodiment, the first trap 121P and the second trap 123P are, for example, with double traps
(twin well) technique makes, without the extra mask of increase or step.
Then, as shown in Figure 4 E, formed field oxide 161 in the first trap 121P on and be located at the first heavily doped region 141N and
Between second heavily doped region 143P, field oxide 160 can be also formed in the first trap 121P and the first doped region 230N (the 3rd traps
On adjoiner 125N).
Then, as shown in Figure 4 E, the first heavily doped region 141N and the second heavily doped region 143P is formed in first trap 121P
Interior, the second heavily doped region 143P and the first heavily doped region 141N are asked to separate and, and form the 3rd heavily doped region 145N in the first doping
In area 230N.In embodiment, the 4th heavily doped region 147P can be also formed in the second trap 123P.
Then, as illustrated in figure 4f, resistive element 150 is formed on field oxide 161.In embodiment, resistive element 150
Formed in this way by a polysilicon layer.The semiconductor device 200 of the present embodiment can be smoothly completed through above-mentioned steps.
3rd embodiment
Fig. 5 is refer to, it illustrates the profile of the semiconductor device 300 of 3rd embodiment.The semiconductor dress of the present embodiment
300 configurations for being resistive element 150 with 100 difference of semiconductor device of first embodiment are put, remaining something in common is not
Repeat narration.
In embodiment, as shown in figure 5, polysilicon layer (resistive element 150) is arranged on the first trap 121P, and positioned at the
Between one heavily doped region 141N and the second heavily doped region 143P, and both are spaced apart by this.
For the manufacture method of the semiconductor device 300 of the present embodiment, with the semiconductor device 100 of first embodiment
Difference, which essentially consists in, does not form field oxide 161 as shown in Figure 1.In other words, in the manufacturing process of semiconductor device 300
In, field oxide 160 is formed, and resistive element 150 is formed on the first trap 121P, resistive element 150 is positioned at predetermined formation
Between first heavily doped region 141N and predetermined the second heavily doped region 143P formed, each heavily doped region is then just formed.First shape
Into resistive element 150 still to possess the effect for being similar to field oxide (be, for example, as shown in Figure 1 field oxide 161),
Each heavily doped region can be formed according to the allocation position of field oxide 160 and resistive element 150.The manufacture method of the present embodiment
It is not repeated to describe with remaining something in common of the manufacture method of first embodiment.
Fourth embodiment
Fig. 6 is refer to, it illustrates the profile of the semiconductor device 400 of fourth embodiment.The semiconductor dress of the present embodiment
400 configurations for being resistive element 150 with 200 difference of semiconductor device of second embodiment are put, remaining something in common is not
Repeat narration.
In embodiment, as shown in fig. 6, polysilicon layer (resistive element 150) is arranged on the first trap 121P, and positioned at the
Between one heavily doped region 141N and the second heavily doped region 143P, and both are spaced apart by this.
For the manufacture method of the semiconductor device 400 of the present embodiment, with the semiconductor device 200 of first embodiment
Difference, which essentially consists in, does not form a field oxide 161 as shown in Figure 2.In other words, in the manufacture of semiconductor device 400
Cheng Zhong, forms field oxide 160, and forms resistive element 150 on the first trap 121P, and resistive element 150 is formed positioned at predetermined
The first heavily doped region 141N and predetermined the second heavily doped region 143P formed between, then just form each heavily doped region.First
The resistive element 150 of formation is still to possess the effect for being similar to field oxide (be, for example, as shown in Figure 2 field oxide 161)
Fruit, can form each heavily doped region according to the allocation position of field oxide 160 and resistive element 150.The manufacture of the present embodiment
Remaining something in common of the manufacture method of method and second embodiment is not repeated to describe.
It is the electrical property feature for the structure for illustrating present invention by taking semiconductor device 200 as an example below.But the electricity
Property feature is not limited to semiconductor device 200, semiconductor device 100 to semiconductor device 400 and is not departing from this case
Structure in spirit and scope, which changes and retouches, to be applicable in.
Fig. 7 is refer to, it illustrates the equivalent transistor schematic diagram of the semiconductor device 200 of second embodiment.Such as Fig. 7 institutes
Show, substrate 110P, the first doped region 230N, the first trap 121P and the first heavily doped region 141N form a thyristor
(thyristor), which has an equivalent NPN transistor (being, for example, equivalent N PN transistors 181,183) and one
Equivalent PNP transistor (being, for example, equivalent N PN transistors 185,187).Equivalent N PN transistors for example by the first doped region 230N,
First trap 121P and the first heavily doped region 141N are formed, equivalent PNP transistor for example by substrate 110P, the first doped region 230N and
First trap 121P is formed.The base stage (being, for example, the second heavily doped region 143P) of equivalent N PN transistors is electrical via resistive element 150
It is connected to the base stage (being, for example, the 3rd heavily doped region 145N) of equivalent PNP transistor.In thyristor, equivalent PNP transistor
Base stage at the same time be also equivalent N PN transistors collector.
As shown in fig. 7, resistive element 150 is arranged on field oxide 161, the first doped region 230N (is, for example, the 3rd trap
125N and/or buried regions 231N) via metal layer ML2, resistive element 150 and metal layer MLl the first trap 121P is electrically connected at, electricity
Resistance element 150 is so that the first trap 121P (being, for example, the base stage of equivalent N PN transistors 181,183) and the first doped region 230N (examples
The collector of equivalent N PN transistors 181,183 in this way) between produce pressure difference, and the current potential of the first doped region 230N is higher than the first trap
The current potential of 121P, so that in the first trap 121P (being, for example, the base stage of equivalent N PN transistors 181,183) and the first doped region
230N's (being, for example, the collector of equivalent N PN transistors 181,183) asks middle generation exhaustion region, is conducive to the flowing of electric current, into
And be conducive to the running of equivalent N PN transistors (being, for example, equivalent N PN transistors 181 and equivalent N PN transistors 183).Such one
Come, based on the running of equivalent N PN transistors, drive electric current by the first doped region 230N and electric toward second via metal layer ML2
172 end of pole (being, for example, the collector terminal of equivalent N PN transistors 181,183) flowing, and electric current can be reduced via the second trap 123P
And/or substrate 110P is flowed toward 173 end of the 3rd electrode, and then the situation of substrate leakage is reduced, and improve overall static discharge
Protection effect.
Fig. 8 is refer to, it illustrates the equivalent circuit diagram of the semiconductor device of some embodiments of content according to the present invention.Such as
Shown in Fig. 8, resistive element 150 is so that produce pressure difference, and then reduce substrate between the base stage and collector of NPN equivalent transistors
The effect of electric leakage.
Fig. 9 is refer to, it illustrates the I-V curve figure of the semiconductor device 200 of second embodiment, and wherein curve I is represented
The substrate leakage for the insulated transistor known represents semiconductor relative to the relation between the anode voltage Vanode of application, curve II
The substrate leakage of device 200 is relative to the relation between putting on the anode voltage Vanode of second electrode 172.In embodiment,
3rd electrode 173 as shown in Figure 7 is, for example, a test electrode, and the current values of substrate leakage are surveyed via the 3rd electrode 173
Measure and obtain.As shown in figure 9, when anode voltage Vanode rises to over more than about 6.2 volts by 5 volts, the substrate shown in curve I
Electric leakage has arrived at milliampere (mA) grade, and the substrate leakage shown in curve II still differs extremely in microampere (μ A) grade, both this
It is more than two grades (order).In other words, the semiconductor device of the embodiment of present invention, effectively can significantly drop
The substrate leakage of low insulation transistor.
Although in conclusion the present invention with preferred embodiment invention as above, so its be not limited to the present invention.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims scope.
Claims (16)
1. a kind of semiconductor device, including：
One substrate；
One first doped region (doping region), is arranged on the substrate；
One first trap (well), is arranged in first doped region；
One first heavily doped region (heavily doping region), is arranged in first trap；
One second heavily doped region, is arranged in first trap, which be spaced apart with first heavily doped region；
One the 3rd heavily doped region, is arranged in first doped region；And
One resistive element, second heavily doped region are electrically connected at the 3rd heavily doped region via the resistive element；
Wherein the resistive element is a polysilicon layer, and the substrate, first trap and second heavily doped region have one first doping
Kenel, first doped region, first heavily doped region and the 3rd heavily doped region have one second dopant profile, first doping
Kenel is complementary to second dopant profile.
2. semiconductor device according to claim 1, further includes one second trap, is arranged on the substrate, wherein this first
Doped region is arranged between first trap and second trap, which has first dopant profile.
3. semiconductor device according to claim 2, further includes one the 4th heavily doped region, it is arranged in second trap, should
4th heavily doped region has first dopant profile.
4. semiconductor device according to claim 1, the wherein polysilicon layer be arranged on first trap and positioned at this
Between one heavily doped region and second heavily doped region.
5. semiconductor device according to claim 1, further includes a field oxide (field oxide, FOX), this oxygen
Change layer to be arranged on first trap and between first heavily doped region and second heavily doped region.
6. semiconductor device according to claim 5, the wherein resistive element are a polysilicon layer, which is set
In on the field oxide.
7. semiconductor device according to claim 2, wherein first doped region include：
One buried regions (buried layer), is arranged at the lower section of first trap；And
One the 3rd trap, is arranged on the buried regions, and wherein the 3rd trap is arranged between first trap and second trap.
8. a kind of semiconductor device, including：
One thyristor (thyristor), has an equivalent NPN transistor and an equivalent PNP transistor；And
One resistive element, the base stage of the equivalent NPN transistor are directly electrically connected at the equivalent PNP crystal via the resistive element
The base stage of pipe；
Wherein the resistive element is a polysilicon layer, and the collector of the equivalent NPN transistor is electrically connected at a second electrode, and
The emitter of the equivalent PNP transistor is electrically connected at via the resistive element, the emitter of the equivalent NPN transistor electrically connects
It is connected to first electrode；The emitter of the equivalent PNP transistor is electrically connected to the second electrode via the resistive element, this is equivalent
The collector of PNP transistor is electrically connected at the 3rd electrode.
9. semiconductor device according to claim 8, the wherein thyristor include：
One substrate；
One first doped region, is arranged on the substrate；
One first trap, is arranged in first doped region；And
One first heavily doped region, is arranged in first trap；
Wherein the substrate and first trap have one first dopant profile, and first doped region and first heavily doped region have one
Second dopant profile, first dopant profile are complementary to second dopant profile.
10. a kind of manufacture method of semiconductor device, including：
One substrate is provided；
One first doped region is formed on the substrate；
One first trap is formed in first doped region；
One first heavily doped region is formed in first trap；
One second heavily doped region is formed in first trap, which be spaced apart with first heavily doped region；
One the 3rd heavily doped region is formed in first doped region；And
A resistive element is formed, which is electrically connected at the 3rd heavily doped region via the resistive element；
Wherein the resistive element is a polysilicon layer, and the substrate, first trap and second heavily doped region have one first doping
Kenel, first doped region, first heavily doped region and the 3rd heavily doped region have one second dopant profile, first doping
Kenel is complementary to second dopant profile.
11. the manufacture method of semiconductor device according to claim 10, further includes：
One second trap is formed on the substrate, wherein first doped region is formed between first trap and second trap, this
Two traps have first dopant profile.
12. the manufacture method of semiconductor device according to claim 11, further includes：
One the 4th heavily doped region is formed in second trap, the 4th heavily doped region has first dopant profile.
13. the manufacture method of semiconductor device according to claim 10, wherein the step of forming the resistive element includes：
The polysilicon layer is formed on first trap and between first heavily doped region and second heavily doped region.
14. the manufacture method of semiconductor device according to claim 10, further includes：
A field oxide is formed on first trap and between first heavily doped region and second heavily doped region.
15. the manufacture method of semiconductor device according to claim 14, wherein the step of forming the resistive element includes：
The polysilicon layer is formed on the field oxide.
16. the manufacture method of semiconductor device according to claim 11, wherein forming first doped region in the substrate
On step include：
A buried regions is formed in the lower section of first trap；And
One the 3rd trap is formed on the buried regions, wherein the 3rd trap is formed between first trap and second trap.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE392783B (en) * | 1975-06-19 | 1977-04-18 | Asea Ab | SEMICONDUCTOR DEVICE INCLUDING A THYRIST AND A FIELD POWER TRANSISTOR PART |
| US5854504A (en) * | 1997-04-01 | 1998-12-29 | Maxim Integrated Products, Inc. | Process tolerant NMOS transistor for electrostatic discharge protection |
| US7327541B1 (en) * | 1998-06-19 | 2008-02-05 | National Semiconductor Corporation | Operation of dual-directional electrostatic discharge protection device |
| US7427787B2 (en) * | 2005-07-08 | 2008-09-23 | Texas Instruments Incorporated | Guardringed SCR ESD protection |
| KR20100089519A (en) * | 2009-02-04 | 2010-08-12 | 서경대학교 산학협력단 | Electro-static discharge protection circuit using grounded-gate nmosfet and thyristor |
| US8378422B2 (en) * | 2009-02-06 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection device comprising a plurality of highly doped areas within a well |
| TWI447861B (en) * | 2011-04-20 | 2014-08-01 | Macronix Int Co Ltd | Semiconductor device and manufacturing method for the same |
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