CN104425480B

CN104425480B - High-voltage electrostatic protection structure

Info

Publication number: CN104425480B
Application number: CN201310362902.5A
Authority: CN
Inventors: 苏庆; 邓樟鹏; 苗彬彬; 张强
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-08-19
Filing date: 2013-08-19
Publication date: 2017-02-15
Anticipated expiration: 2033-08-19
Also published as: CN104425480A

Abstract

The invention discloses a high-voltage electrostatic protection structure which includes an N-type LDMOS which is arranged in a P-type burial layer on a silicon substrate; a polysilicon gate right-side active region which is an LDMOS drain region and includes a high-voltage N well arranged on the right side of the P-type burial layer and a first N+ diffusion region, wherein a field oxide region is arranged between the first N+ diffusion region and a polysilicon gate, and both of the first N+ diffusion region and the field oxide region are surrounded by the high-voltage N well; and a polysilicon gate left-side active region which is an LDMOS source region and includes a high-voltage P well arranged on the left side of the P-type burial layer and an N well. Part of a second N+ diffusion region and a first P+ diffusion region are on the N well and the remaining part of the second N+ diffusion region is on the high-voltage P well. A second P+ diffusion region is on the high-voltage P well. Oxide regions are arranged among the first P+ diffusion region, the second P+ diffusion region, and the second N+ diffusion region. The first P+ diffusion region, the second P+ diffusion region and the polysilicon gate are lead out and grounded. The first N+ diffusion region is lead out and used as an electrostatic input end. The invention provides the high-voltage electrostatic protection structure which is unlikely to trigger a latch-up effect.

Description

High-voltage electrostatic protection structure

Technical field

The present invention relates to IC manufacturing field, more particularly to a kind of high-voltage electrostatic protection structure.

Background technology

Static discharge (ESD) is always masty problem for the injury of electronic product, for high-pressure process, Electrostatic protection device not only needs to meet the pressure requirement being greater than supply voltage, and its electrostatic trigger voltage also needs to be less than and protected The damage voltage of shield device is just permissible.As shown in figure 1, the high pressure NLDMOS structure being generally used for electrostatic protection occurs in electrostatic Under, ESD positive charge, after import and export weld pad enters this structure drain region, raises the current potential of N- diffusion region, avalanche breakdown occurs, punctures The P+ diffusion region that electric current passes through in p-well is drawn, and raises the current potential of p-well simultaneously, leads to the parasitic triode in this structure to turn on.Should Parasitic triode be made up of the high pressure p-well under drain region N-type diffusion region, the N+ diffusion region of source electrode and its raceway groove horizontal three Pole pipe.This parasitic triode is opened and mainly leans on the junction breakdown between N- diffusion region and high pressure p-well to open come the NPN to trigger parasitism Open, rapid pressure of wiring back is very low, and is difficult to adjust, easy trigger latch effect.

Content of the invention

The technical problem to be solved in the present invention is to provide a kind of high-voltage electrostatic protection structure being difficult trigger latch effect.

For solve above-mentioned technical problem, the high-voltage electrostatic protection structure of the present invention, including：One N-type LDMOS (horizontal proliferation Metal field effect transistor), it is integrally placed in the p type buried layer above a silicon substrate；

The right side active area of polysilicon gate is the drain region of described LDMOS, including：It is arranged at the height of p type buried layer right upper portion Pressure N trap, positioned at a N+ type diffusion region on high pressure N trap top, is mutually separated with one between the wherein the first N+ diffusion region and polysilicon gate Field oxide region, a N+ diffusion region and field oxide region are all surrounded by high pressure N trap；

The left side active area of polysilicon gate is the source region of described LDMOS, including：It is arranged at the height of p type buried layer left upper portion Pressure p-well, positioned at the N trap on high pressure p-well top；

Part the 2nd N+ diffusion region and a P+ diffusion region are located above N trap, and remainder the 2nd N+ diffusion region is located at height Pressure p-well top, the 2nd P+ diffusion region is located above high pressure p-well；

Between first P+ diffusion region, the 2nd P+ diffusion region and the 2nd N+ diffusion region, there is field oxide region；Wherein, a P+ expands Field oxide region part between scattered area and the 2nd P+ diffusion region is located at high pressure p-well top, and remainder is located at N trap top, a P Field oxide region between+diffusion region and the 2nd N+ diffusion region is located at N trap top；

First P+ diffusion region, the 2nd P+ diffusion region and polysilicon gate are drawn and ground connection, and conduct is drawn in a N+ diffusion region Electrostatic input.

Wherein, described N trap can adopt low pressure N trap.

Fashionable when there being electrostatic to enter from drain region, the present invention passes through the height under drain region high pressure N trap, the N trap of source region and its raceway groove The parasitic triode of pressure p-well composition opens leakage current.With respect to common LDMOS structure (as shown in Figure 1), this structure exists Source region increased N trap and the 2nd P+ diffusion region.After parasitic triode triggering and conducting, electric current flows into from drain region high pressure N trap, flows to Source region N trap, by needing reverse breakdown come leakage current to ground by the diode that source region N trap and the 2nd P+ diffusion region are formed.Now Rapid telegram in reply pressure be common LDMOS rapid telegram in reply pressure and this diode reverse breakdown voltage sum.And by adjusting source region N The 2nd N+ diffusion region in trap and the distance of the 2nd P+ diffusion region, can adjust two poles that this N trap and the 2nd P+ diffusion region are formed The breakdown reverse voltage of pipe, is so also achieved that effective rapid telegram in reply pressure adjusting this inventive structure.The structure of the present invention is favourable In the generation preventing latch-up, the protective capacities that overall electrostatic and breech lock are improved with this, can operate with the high-pressure side of BCD technique In the electrostatic protection application of mouth.

Brief description

The present invention is further detailed explanation with specific embodiment below in conjunction with the accompanying drawings：

Fig. 1 is a kind of existing high pressure NLDMOS structural representation for electrostatic protection.

Fig. 2 is the structural representation of the present invention.

Description of reference numerals

1 is silicon substrate

2 is p type buried layer

3 is high pressure N trap

4 is a N+ expanding area

5 is polysilicon gate

6 is high pressure p-well

7 is N trap

8 is the 2nd N+ diffusion region

9 is a P+ diffusion region

10 is the 2nd P+ diffusion region

11 is the first field oxide region

12 is the second field oxide region

13 is the 3rd field oxide region

G is ground

E is electrostatic input

Specific embodiment

As shown in figure 1, one embodiment of the invention includes：One N-type LDMOS, the p-type being integrally placed at a silicon substrate 1 top is buried In layer 2；

The right side active area of polysilicon gate 5 is the drain region of described LDMOS, including：It is arranged at p type buried layer 2 right upper portion High pressure N trap 3, positioned at a N+ type diffusion region 4 on high pressure N trap 3 top, phase between the wherein the first N+ diffusion region 4 and polysilicon gate 5 It is separated with the first field oxide region 11, a N+ diffusion region 4 and the first field oxide region 11 are all surrounded by high pressure N trap；

The left side active area of polysilicon gate 5 is the source region of described LDMOS, including：It is arranged at p type buried layer 2 left upper portion High pressure p-well 6, positioned at the N trap 7 on high pressure p-well 6 top, in the present embodiment, N trap 7 is low pressure N trap；

Part the 2nd N+ diffusion region 8 and a P+ diffusion region 9 are located above N trap 7, remainder the 2nd N+ diffusion region 8 In high pressure p-well 6 top, the 2nd P+ diffusion region 10 is located above high pressure p-well 6；

Between 2nd N+ diffusion region 8 and the 2nd P+ diffusion region 10, there is the second field oxide region 12, a P+ diffusion region 9 and Between two P+ diffusion regions 10, there is the 3rd field oxide region 13；Wherein, between a P+ diffusion region 9 and the 2nd P+ diffusion region 10 Three field oxide region 13 part is located at high pressure p-well 6 top, and remainder is located at N trap 7 top, and a P+ diffusion region 9 and the 2nd N+ expand The second field oxide region 12 between scattered area 8 is located at N trap 7 top；

G is drawn and be grounded to first P+ diffusion region 9, the 2nd P+ diffusion region 10 and polysilicon gate 5, and a N+ diffusion region 4 is drawn Go out as electrostatic input E.

Fashionable when there being electrostatic to enter from drain region, the present invention passes through under drain region high pressure N trap 3, the N trap 7 of source region and its raceway groove The parasitic triode of high pressure p-well 6 composition opens leakage current.With respect to common LDMOS structure (as shown in Figure 1), this knot Structure increased N trap 7 and the 2nd P+ diffusion region 10 in source region；After parasitic triode triggering and conducting, electric current is from drain region high pressure N trap 3 Flow into, flow to source region N trap 7, by needing reverse breakdown to release by the diode that source region N trap 7 and the 2nd P+ diffusion region 10 are formed Electric current is to ground.Rapid telegram in reply pressure now is rapid telegram in reply pressure and this diode reverse breakdown voltage sum of common LDMOS.And By adjusting the distance of the 2nd N+ diffusion region 8 in source region N trap 7 and the 2nd P+ diffusion region 10, this N trap 7 and the 2nd P can be adjusted The breakdown reverse voltage of the diode that+diffusion region 10 is formed, is so also achieved that effective rapid telegram in reply adjusting this inventive structure Pressure.

Above by specific embodiment and embodiment, the present invention has been described in detail, but these not constitute right The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art also can make many deformation and change Enter, these also should be regarded as protection scope of the present invention.

Claims

1. a kind of high-voltage electrostatic protection structure, is characterized in that, including：One N-type LDMOS, is integrally placed at the p-type above a silicon substrate In buried regions；

The right side active area of polysilicon gate is the drain region of described LDMOS, including：It is arranged at the high pressure N of p type buried layer right upper portion Trap, positioned at a N+ type diffusion region on high pressure N trap top, is mutually separated with an oxygen between the wherein the first N+ diffusion region and polysilicon gate Change area, a N+ diffusion region and this field oxide region are all surrounded by high pressure N trap；

The left side active area of polysilicon gate is the source region of described LDMOS, including：It is arranged at the high pressure P of p type buried layer left upper portion Trap, positioned at the N trap on high pressure p-well top；

Part the 2nd N+ diffusion region and a P+ diffusion region are located above N trap, and remainder the 2nd N+ diffusion region is located at high pressure p-well Top, the 2nd P+ diffusion region is located above high pressure p-well；

Between first P+ diffusion region, the 2nd P+ diffusion region and the 2nd N+ diffusion region, there is field oxide region；Wherein, a P+ diffusion region And the 2nd the field oxide region part between P+ diffusion region be located at high pressure p-well top, remainder is located at N trap top, and a P+ expands Field oxide region between scattered area and the 2nd N+ diffusion region is located at N trap top；

First P+ diffusion region, the 2nd P+ diffusion region and polysilicon gate are drawn and ground connection, and a N+ diffusion region is drawn as electrostatic Input.

2. high-voltage electrostatic protection structure as claimed in claim 1, is characterized in that：Described N trap is low pressure N trap.