CN104425348A - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
- Publication number
- CN104425348A CN104425348A CN201310410802.5A CN201310410802A CN104425348A CN 104425348 A CN104425348 A CN 104425348A CN 201310410802 A CN201310410802 A CN 201310410802A CN 104425348 A CN104425348 A CN 104425348A
- Authority
- CN
- China
- Prior art keywords
- semiconductor substrate
- isolation structure
- fleet plough
- plough groove
- groove isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention provides a preparation method of a semiconductor device. The preparation method comprises the following steps: providing a semiconductor substrate and forming a hard mask layer with a plurality of patterns forming shallow trench isolation structures on the semiconductor substrate; forming a plurality of shallow trench isolation structures in the semiconductor substrate; implementing dry etching and wet etching to remove the parts, higher than the semiconductor substrate, of the plurality of shallow trench isolation structures; removing the hard mask layer. According to the invention, by implementing dry etching and wet etching to remove the parts, higher than the semiconductor substrate, of the plurality of shallow trench isolation structures, the heights of the shallow trench isolation structures in different regions on the semiconductor substrate after the parts are removed can be consistent.
Description
Technical field
The present invention relates to semiconductor fabrication process, form the method for shallow trench isolation from (STI) structure in particular to one.
Background technology
In semiconductor fabrication process, the performance of the fleet plough groove isolation structure formed is most important for the electric property of the last semiconductor device formed.Along with the continuous reduction of feature sizes of semiconductor devices, fill in order to ensure the zero-clearance realizing the oxide forming fleet plough groove isolation structure in the groove formed in the semiconductor substrate, usually implement the filling that Multiple depositions technique completes described oxide.Owing to being subject to the restriction of the characteristic size of described groove, the deposition rate deposited each time in described Multiple depositions technique is caused to there are differences, thus, after carrying out high annealing, the compactness extent depositing the oxide formed each time in described Multiple depositions technique there are differences.After formation fleet plough groove isolation structure, need to remove the part that fleet plough groove isolation structure exceeds Semiconductor substrate, usual employing wet etching completes the removal that described fleet plough groove isolation structure exceeds the part of Semiconductor substrate, and such as corrosive liquid is the wet etching of the hydrofluoric acid (DHF) of dilution.Because the compactness extent of the multilevel oxide forming fleet plough groove isolation structure there are differences, the etch-rate of described wet etching to described multilevel oxide is caused to there are differences, thus, after described wet etching, the fleet plough groove isolation structure being positioned at the zones of different of Semiconductor substrate exceeds the removal effect difference of the part of Semiconductor substrate, the removal completely had, some removal major parts, some removal sub-fractions.
As shown in Figure 1A, after described wet etching, the height being positioned at the fleet plough groove isolation structure 101 in the larger region of the formation device density of Semiconductor substrate 100 is lower than the height of the fleet plough groove isolation structure 102 in the less region of the formation device density being positioned at Semiconductor substrate 100.The reason of this phenomenon is caused to be, the characteristic size of the width of the fleet plough groove isolation structure 101 formed in the region that the formation device density of Semiconductor substrate 100 is larger is less than the characteristic size of the width of the fleet plough groove isolation structure 102 formed in the region that the formation device density of Semiconductor substrate 100 is less, and the multilevel oxide of the formation fleet plough groove isolation structure 101 causing described Multiple depositions technique to be formed compares the difference that the multilevel oxide forming fleet plough groove isolation structure 102 has small compactness extent; In described wet etch process, relative to the multilevel oxide forming fleet plough groove isolation structure 102, the corrosive liquid of described wet etching has larger etch-rate to the multilevel oxide forming fleet plough groove isolation structure 101.
Relative to described wet etching, remove according to dry etching the part that described fleet plough groove isolation structure exceeds Semiconductor substrate, then the difference in height between the fleet plough groove isolation structure 101 forming the larger region of device density in Semiconductor substrate 100 caused by above-mentioned reason and the fleet plough groove isolation structure 102 forming the less region of device density in Semiconductor substrate 100 will obviously reduce.But, as shown in Figure 1B, after described dry etching, the height being positioned at the fleet plough groove isolation structure 101 in the larger region of the formation device density of Semiconductor substrate 100 is slightly higher than the height of the fleet plough groove isolation structure 102 in the less region of the formation device density that is positioned at Semiconductor substrate 100.
Because the height of the fleet plough groove isolation structure being formed in the zones of different of Semiconductor substrate is inconsistent, cause follow-up formation on a semiconductor substrate after gate dielectric and gate material layers, the height of the grid structure be made up of gate dielectric and gate material layers is also inconsistent, and then causes the difference of electric property of device of the zones of different being formed in Semiconductor substrate.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, form the hard mask layer with the pattern of multiple fleet plough groove isolation structure on the semiconductor substrate; Described multiple fleet plough groove isolation structure is formed in described Semiconductor substrate; Enforcement dry etching and wet etching remove the part that described multiple fleet plough groove isolation structure exceeds described Semiconductor substrate; Remove described hard mask layer.
Further, be formed in described multiple fleet plough groove isolation structure described Semiconductor substrate have that the different Partial Height forming the region of device density is identical and width different, the Partial Height with the region of same formation device density being formed at described Semiconductor substrate in described multiple fleet plough groove isolation structure is identical and width is identical.
Further, described hard mask layer is silicon nitride layer.
Further, the step forming described multiple fleet plough groove isolation structure comprises: with described hard mask layer for mask, etches the groove for the formation of described multiple fleet plough groove isolation structure in described Semiconductor substrate; Depositing isolation material in the trench and on described hard mask layer; Perform chemical mechanical milling tech to grind described isolated material, until expose described hard mask layer.
Further, described isolated material is oxide.
Further, described deposition completes several times, and the isolated material of each deposition is identical.
Further, after described deposition and described grinding, implement annealing respectively.
Further, the etching gas of described dry etching is for comprising NF
3and NH
3mixture or comprise H
2and NF
3mixture, the corrosive liquid of described wet etching is the hydrofluoric acid of dilution.
Further, the implementation process of described dry etching comprises the steps: described etching gas to be converted under the action of radio of periphery to comprise F ion, HF ion and NH
4the plasma of ion; Described plasma is imported the etching cavity having placed described Semiconductor substrate, at 25-30 DEG C, described plasma reacts with the isolated material forming described multiple fleet plough groove isolation structure and generates volatile complex compound; The temperature of described Semiconductor substrate is brought up to more than 100 DEG C, described complex compound is volatilized and discharges from described etching cavity.
Further, the pressure of described dry etching is 2-3Torr, and the power of described radio frequency is 15-50W.
Further, wet-etching technology is adopted to implement the removal of described hard mask layer.
Further, after the removal of described hard mask layer, also comprise the step described Semiconductor substrate and described multiple fleet plough groove isolation structure being implemented to wet-cleaned.
Further, after described wet-cleaned, also comprise the step forming grid structure on the semiconductor substrate, described grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top
According to the present invention, enforcement dry etching and wet etching remove the part that described multiple fleet plough groove isolation structure exceeds half described conductive substrate, and the height being positioned at the fleet plough groove isolation structure of the zones of different in described Semiconductor substrate after can making described removal is consistent.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A is that inconsistent schematic cross sectional view appears in the height being formed in the fleet plough groove isolation structure of the zones of different of Semiconductor substrate adopt wet etching removal fleet plough groove isolation structure to exceed the part of Semiconductor substrate when forming fleet plough groove isolation structure after;
Figure 1B is that inconsistent schematic cross sectional view appears in the height being formed in the fleet plough groove isolation structure of the zones of different of Semiconductor substrate adopt dry etching removal fleet plough groove isolation structure to exceed the part of Semiconductor substrate when forming fleet plough groove isolation structure after;
The schematic cross sectional view of the device that Fig. 2 A-Fig. 2 C obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 3 is that method forms the flow chart of fleet plough groove isolation structure according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the method for the formation fleet plough groove isolation structure that the present invention proposes.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below, describe method according to an exemplary embodiment of the present invention with reference to Fig. 2 A-Fig. 2 C and Fig. 3 and form the detailed step of fleet plough groove isolation structure.
With reference to Fig. 2 A-Fig. 2 C, the schematic cross sectional view of the device that the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively obtains respectively.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, the constituent material of Semiconductor substrate 200 can to adopt on unadulterated monocrystalline silicon, monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), insulator stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate 200 selects monocrystalline silicon.
For Semiconductor substrate 200, the region that the device density that will be formed is larger is formed with fleet plough groove isolation structure 201, and the region that the device density that will be formed is less is formed with fleet plough groove isolation structure 202.Those skilled in the art should know, the region that will form device of Semiconductor substrate 200 is not limited to above-mentioned two regions, in this case simplification, and what Fig. 2 A illustrate only Semiconductor substrate 200 will form the different region of two of device.Fleet plough groove isolation structure 201 and 202 is synchronous formation, the characteristic size of the width of fleet plough groove isolation structure 201 is less than the characteristic size of the width of fleet plough groove isolation structure 202, and the characteristic size of the height of fleet plough groove isolation structure 201 is identical with the characteristic size of the height of fleet plough groove isolation structure 202.Also be formed with various trap (well) structure in Semiconductor substrate 200, in order to simplify, be omitted in diagram.
In an one exemplary embodiment of the present invention, the processing step forming fleet plough groove isolation structure 201 and 202 comprises: form hard mask layer 203 on semiconductor substrate 200, the various suitable technology adopting those skilled in the art to have the knack of forms hard mask layer 203, such as chemical vapor deposition method, the material preferred nitrogen SiClx of hard mask layer 203; Patterned hard mask layer 203, to form the opening being formed the pattern of fleet plough groove isolation structure 201 and 202 in hard mask layer 203, this process comprises: on hard mask layer 203, form the photoresist layer with the pattern of fleet plough groove isolation structure 201 and 202, with described photoresist layer for mask, etching hard mask layer 203, until expose Semiconductor substrate 200, adopts cineration technics to remove described photoresist layer; With the hard mask layer 203 of patterning for mask, in Semiconductor substrate 200, etch the groove for the formation of fleet plough groove isolation structure 201 and 202; Depositing isolation material in the trench and on hard mask layer 203, described isolated material is generally oxide, preferred HARP; Perform chemical mechanical milling tech to grind described isolated material, until expose hard mask layer 203.In above process, fill in order to ensure the zero-clearance realizing isolated material in the trench, the deposition of described isolated material (is generally three times) several times and completes, and the formation of isolated material formed each time is identical.After said deposition, perform annealing, to make the isolated material densification of formation, promote its mechanical strength.After described grinding, perform another annealing, to repair the damage of said process to Semiconductor substrate 200, improve the interfacial characteristics between fleet plough groove isolation structure 201 and 202 and Semiconductor substrate 200.
It should be noted that, in above-mentioned one exemplary embodiment, before forming hard mask layer 203, first can form one deck oxide thin layer thing as resilient coating, to discharge the stress between hard mask layer 203 and Semiconductor substrate 200; Before depositing isolation material, on hard mask layer 203 and form another oxide thin layer thing for the formation of the sidewall of the groove of fleet plough groove isolation structure 201 and 202 and bottom and form backing layer; In order to simplify, described resilient coating and backing layer are all not shown.
Then, as shown in Figure 2 B, enforcement dry etching and wet etching remove the part that fleet plough groove isolation structure 201 and 202 exceeds Semiconductor substrate 200.
In the present embodiment, the etching gas of dry etching is for comprising NF
3and NH
3mixture or comprise H
2and NF
3mixture.Described dry etching is different from conventional plasma dry etching, first, is converted into by above-mentioned etching gas and comprises F ion, HF ion and NH under the action of radio of periphery
4the plasma of ion; Then, above-mentioned plasma is imported the etching cavity having placed Semiconductor substrate 200, under normal temperature (25-30 DEG C), above-mentioned plasma reacts with the isolated material forming fleet plough groove isolation structure 201 and 202 and generates volatile complex compound; Then, the temperature of Semiconductor substrate 200 is brought up to more than 100 DEG C, described complex compound is volatilized and discharges from etching cavity.The pressure of described dry etching is 2-3Torr(millimetres of mercury), the power of described radio frequency is 15-50W.It should be noted that, under the action of radio of periphery, other can be converted into the etching gas that can react with described isolated material the plasma generating volatile complex compound and all fall within protection scope of the present invention.
In the present embodiment, the hydrofluoric acid that preferably dilutes of the corrosive liquid of wet etching.It should be noted that, the enforcement order in no particular order of described dry etching and described wet etching.
Compare existing technique to be used alone wet etching or dry etching and to remove the part that fleet plough groove isolation structure 201 and 202 exceeds Semiconductor substrate 200, the present invention adopts the mode of associating dry etching and wet etching to implement described removal, very little to the difference of the etch-rate of the multilevel oxide of formation fleet plough groove isolation structure 201 and 202, therefore, after dry etching described in Joint Implementation and described wet etching, the height of fleet plough groove isolation structure 201 and 202 is close to identical.
Then, as shown in Figure 2 C, hard mask layer 203 is removed.In the present embodiment, wet etching is adopted to implement the removal of hard mask layer 203, the preferred hot phosphoric acid of corrosive liquid of described wet etching.Then, wet cleaning processes is implemented, to remove residue (mainly from aforementioned etching process) and the impurity on Semiconductor substrate 200 and fleet plough groove isolation structure 201 and 202 surface.The cleaning fluid of described wet-cleaned is the hydrofluoric acid of dilution.
So far, the processing step that method is according to an exemplary embodiment of the present invention implemented is completed.Next, conventional semiconductor device front end fabrication process can be implemented:
In an exemplary embodiment, first, form grid structure on semiconductor substrate 200, exemplarily, grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top.
Particularly, the constituent material of gate dielectric comprises oxide, such as silicon dioxide (SiO
2).Select SiO
2during constituent material as gate dielectric, form gate dielectric by rapid thermal oxidation process (RTO), its thickness is 8-50 dust, but is not limited thereto thickness.
The constituent material of gate material layers comprise in polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide one or more, wherein, metal can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride comprises titanium nitride (TiN); Conductive metal oxide comprises yttrium oxide (IrO
2); Metal silicide comprises titanium silicide (TiSi).When selecting the constituent material of polysilicon as gate material layers, low-pressure chemical vapor phase deposition (LPCVD) technique can be selected to form gate material layers, and its process conditions comprise: reacting gas is silane (SiH
4), its flow is 100 ~ 200sccm, preferred 150sccm; Temperature in reaction chamber is 700 ~ 750 DEG C; Pressure in reaction chamber is 250 ~ 350mTorr, preferred 300mTorr; Described reacting gas can also comprise buffer gas, and described buffer gas is helium (He) or nitrogen (N
2), its flow is 5 ~ 20 liters/min (slm), preferred 8slm, 10slm or 15slm.
The constituent material of grid hard masking layer comprise in oxide, nitride, nitrogen oxide and amorphous carbon one or more, wherein, oxide comprises boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethoxysilane (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); Nitride comprises silicon nitride (SiN); Nitrogen oxide comprises silicon oxynitride (SiON).Any prior art that the formation method of grid hard masking layer can adopt those skilled in the art to have the knack of, preferred chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).
Then, form the side wall construction near grid structure in grid structure both sides, its constituent material is SiO
2, a kind of in SiN, SiON or their combination.Then, take side wall construction as mask, perform LDD and inject, in the Semiconductor substrate 200 of side wall construction both sides, form LDD injection region.Next, form the offset side wall near side wall construction in grid structure both sides, exemplarily, offset side wall comprises at least one deck oxide skin(coating) and/or nitride layer.Then, take offset side wall as mask, perform source/drain region and inject, in the Semiconductor substrate 200 of offset side wall both sides, form source/drain region.
Then, implement self-alignment silicide technology, the source/drain region of the top of grid structure and grid structure both sides forms self-aligned silicide.Then, formed successively on semiconductor substrate 200 and there is the contact etch stop layer and interlayer dielectric layer that can produce stress characteristics, in interlayer dielectric layer, form the contact hole being communicated with the self-aligned silicide be positioned on the top of grid structure and the source/drain region of grid structure both sides, fill metal (being generally tungsten) in contact hole, form the contact plug connecting interconnecting metal layer and described self-aligned silicide.
Next, conventional semiconductor device back end fabrication can be implemented, comprising: the formation of multiple interconnecting metal layer, usually adopt dual damascene process; The formation of metal pad, for implementing wire bonding during device package.
With reference to Fig. 3, the method according to an exemplary embodiment of the present invention that illustrated therein is forms the flow chart of fleet plough groove isolation structure, for schematically illustrating the flow process of whole manufacturing process.
In step 301, provide Semiconductor substrate, form the hard mask layer with the pattern of multiple fleet plough groove isolation structure on a semiconductor substrate;
In step 302, multiple fleet plough groove isolation structure is formed in the semiconductor substrate;
In step 303, enforcement dry etching and wet etching remove the part that multiple fleet plough groove isolation structure exceeds Semiconductor substrate;
In step 304, hard mask layer is removed.
According to the present invention, enforcement dry etching and wet etching remove the part that fleet plough groove isolation structure 201 and 202 exceeds Semiconductor substrate 200, and the height being positioned at the fleet plough groove isolation structure of the zones of different in Semiconductor substrate 200 after can making described removal is consistent.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, forms the hard mask layer with the pattern of multiple fleet plough groove isolation structure on the semiconductor substrate;
Described multiple fleet plough groove isolation structure is formed in described Semiconductor substrate;
Enforcement dry etching and wet etching remove the part that described multiple fleet plough groove isolation structure exceeds described Semiconductor substrate;
Remove described hard mask layer.
2. method according to claim 1, it is characterized in that, be formed in described multiple fleet plough groove isolation structure described Semiconductor substrate have that the different Partial Height forming the region of device density is identical and width different, the Partial Height with the region of same formation device density being formed at described Semiconductor substrate in described multiple fleet plough groove isolation structure is identical and width is identical.
3. method according to claim 1, is characterized in that, described hard mask layer is silicon nitride layer.
4. method according to claim 1, is characterized in that, the step forming described multiple fleet plough groove isolation structure comprises: with described hard mask layer for mask, etches the groove for the formation of described multiple fleet plough groove isolation structure in described Semiconductor substrate; Depositing isolation material in the trench and on described hard mask layer; Perform chemical mechanical milling tech to grind described isolated material, until expose described hard mask layer.
5. method according to claim 4, is characterized in that, described isolated material is oxide.
6. method according to claim 4, is characterized in that, described deposition completes several times, and the isolated material of each deposition is identical.
7. method according to claim 4, is characterized in that, after described deposition and described grinding, implements annealing respectively.
8. method according to claim 1, is characterized in that, the etching gas of described dry etching is for comprising NF
3and NH
3mixture or comprise H
2and NF
3mixture, the corrosive liquid of described wet etching is the hydrofluoric acid of dilution.
9. method according to claim 8, is characterized in that, the implementation process of described dry etching comprises the steps: described etching gas to be converted under the action of radio of periphery to comprise F ion, HF ion and NH
4the plasma of ion; Described plasma is imported the etching cavity having placed described Semiconductor substrate, at 25-30 DEG C, described plasma reacts with the isolated material forming described multiple fleet plough groove isolation structure and generates volatile complex compound; The temperature of described Semiconductor substrate is brought up to more than 100 DEG C, described complex compound is volatilized and discharges from described etching cavity.
10. method according to claim 9, is characterized in that, the pressure of described dry etching is 2-3Torr, and the power of described radio frequency is 15-50W.
11. methods according to claim 1, is characterized in that, adopt wet-etching technology to implement the removal of described hard mask layer.
12. methods according to claim 1, is characterized in that, after the removal of described hard mask layer, also comprise the step described Semiconductor substrate and described multiple fleet plough groove isolation structure being implemented to wet-cleaned.
13. methods according to claim 12, it is characterized in that, after described wet-cleaned, also comprise the step forming grid structure on the semiconductor substrate, described grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310410802.5A CN104425348B (en) | 2013-09-10 | 2013-09-10 | A kind of manufacture method of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310410802.5A CN104425348B (en) | 2013-09-10 | 2013-09-10 | A kind of manufacture method of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104425348A true CN104425348A (en) | 2015-03-18 |
| CN104425348B CN104425348B (en) | 2017-09-01 |
Family
ID=52973992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310410802.5A Active CN104425348B (en) | 2013-09-10 | 2013-09-10 | A kind of manufacture method of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104425348B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945724A (en) * | 1998-04-09 | 1999-08-31 | Micron Technology, Inc. | Trench isolation region for semiconductor device |
| US6372605B1 (en) * | 2000-06-26 | 2002-04-16 | Agere Systems Guardian Corp. | Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing |
| CN103236416A (en) * | 2013-04-09 | 2013-08-07 | 上海华力微电子有限公司 | Method for manufacturing shallow trench isolation structure |
-
2013
- 2013-09-10 CN CN201310410802.5A patent/CN104425348B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945724A (en) * | 1998-04-09 | 1999-08-31 | Micron Technology, Inc. | Trench isolation region for semiconductor device |
| US6372605B1 (en) * | 2000-06-26 | 2002-04-16 | Agere Systems Guardian Corp. | Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing |
| CN103236416A (en) * | 2013-04-09 | 2013-08-07 | 上海华力微电子有限公司 | Method for manufacturing shallow trench isolation structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104425348B (en) | 2017-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI641085B (en) | Differential sg/eg spacer integration with equivalent nfet/pfet spacer widths & dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage eg device on fdsoi | |
| KR20120036185A (en) | Semiconductor device and method for manufacturing the same | |
| CN105336609B (en) | A kind of FinFET and its manufacturing method, electronic device | |
| CN102148191B (en) | Formation method for contact hole | |
| CN103390644A (en) | Semiconductor device and manufacturing method thereof | |
| CN106653675A (en) | Method of forming isolation structure of shallow trench | |
| CN104882379A (en) | FinFET device and manufacturing method thereof | |
| CN103545185A (en) | Method of producing semiconductor device by pseudo-gate | |
| CN104779284B (en) | A kind of FinFET and its manufacturing method | |
| CN104282614B (en) | A kind of method for forming fleet plough groove isolation structure | |
| CN103151264B (en) | A kind of manufacture method of semiconductor devices | |
| CN105097517B (en) | A kind of FinFET and its manufacturing method, electronic device | |
| CN107464741A (en) | A kind of semiconductor devices and its manufacture method, electronic installation | |
| CN103137451B (en) | A kind of manufacture method of semiconductor device | |
| CN105470296A (en) | Semiconductor device and manufacturing method thereof and electronic device | |
| CN105097516A (en) | FinFET device, manufacturing method thereof and electronic device | |
| CN105575786B (en) | A kind of semiconductor devices and its manufacturing method, electronic device | |
| CN104051245B (en) | A kind of preparation method of semiconductor devices | |
| CN103594412A (en) | Manufacturing method of shallow trench isolation structure and shallow trench isolation structure | |
| CN104425268B (en) | A kind of FinFET and its manufacture method | |
| CN104425349B (en) | A kind of manufacture method of semiconductor devices | |
| CN104425348A (en) | Preparation method of semiconductor device | |
| CN107968122B (en) | Fin type field effect transistor and preparation method thereof | |
| CN108550578B (en) | Three-dimensional memory manufacturing method | |
| CN116053298B (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |