CN104409445A - Silicon wafer redundant graph filling method and product - Google Patents
Silicon wafer redundant graph filling method and product Download PDFInfo
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- CN104409445A CN104409445A CN201410693133.1A CN201410693133A CN104409445A CN 104409445 A CN104409445 A CN 104409445A CN 201410693133 A CN201410693133 A CN 201410693133A CN 104409445 A CN104409445 A CN 104409445A
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- redundant pattern
- efficient circuit
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Abstract
The invention discloses a silicon wafer redundant graph filling method. The silicon wafer redundant graph filling method comprises the following steps of dividing a redundant graph filling area into n regions according to the distances from the regions to an effective circuit of a silicon wafer; and setting filling density values of the n redundant graph filling regions under the conditions that the filling density value of the regions which are close to the effective circuit are small, and the filling density values of the regions which are far away from the effective circuit are large. By setting different filling density values of the regions which are distant from the effective circuit by different distances, influences of a redundant graph on the effective circuit are reduced and high uniformity of the density in a chip is guaranteed.
Description
Technical field
The invention belongs to integrated circuit fields, particularly relate to the filling graph method in integrated circuit fabrication process.
Background technology
In integrated circuit fabrication process, usually can the technique less than 0.25 micron when needing cmp or in the layer etched, add redundant pattern, improve the homogeneity of chemical mechanical grinder etching technics with this.As shown in Figure 1, the redundant filling pattern density in prior art around efficient circuit is all the same.But, comparatively near or that distance cabling the is nearer redundant pattern of the redundant pattern of filling, particularly distance device can be able to have a negative impact to the electric property of device or cabling, thus reduces product yield, the redundant pattern quantity of therefore filling should be the least possible, to reduce its impact on circuit performance.But, based on the existing fill method of above-mentioned consideration, there is the problem that the density in chip cannot balance very well, the density homogeneity in chip is deteriorated, finally still can affect the homogeneity of cmp or silicon chip planarization.
Summary of the invention
One of technical purpose of the present invention is to provide a kind of silicon chip redundant pattern fill method, to solve above-mentioned technological deficiency.This fill method is characterised in that:
According to the distance of efficient circuit on distance silicon chip, redundant pattern fill area is divided into n district;
The packed density value of setting n redundant pattern fill area, principle is, the area filling density value nearer apart from efficient circuit is less, and the area filling density value that distance efficient circuit is far away is larger.
Be to provide a kind of silicon chip containing redundant pattern as another technical purpose of the present invention, comprise silicon chip, efficient circuit and redundant pattern, it is characterized in that: according to the distance apart from described efficient circuit, the fill area of described redundant pattern is divided into n district, and its redundant pattern packed density of the region nearer apart from described efficient circuit is less, and region its redundancy colleague packed density far away apart from described efficient circuit is larger.
The invention has the beneficial effects as follows: the region of being differed by efficient circuit distance of adjusting the distance sets different packed density values, not only reduces the impact of redundant pattern for efficient circuit, but also ensure that the good homogeneity of density in chip.
Accompanying drawing explanation
Fig. 1 is that prior art fills schematic layout pattern
Fig. 2 is that the redundant pattern of one of specific embodiments of the invention fills schematic layout pattern.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.But it is pointed out that following examples are only as to illustrative and non restrictive description of the present invention, therefore any other variations based on these specific embodiments, modification, improves, and replace, extension all should fall into protection scope of the present invention.
As shown in Figure 2, in integrated circuit fabrication process, after the layout determining efficient circuit on silicon chip (efficient circuit 1 and efficient circuit 2), subregion can be carried out to the region of paripheral zone redundant filling, in the present embodiment, assuming that 0.2um is for the redundant pattern that allows in design rule is to the minimum range of efficient circuit, according to the distance apart from efficient circuit distance, redundant pattern fill area is divided into 3 blocks, these 3 blocks are respectively 0.2um ~ 3um, 3um ~ 10um to the distance of efficient circuit and are greater than 10um.The packed density target setting these 3 blocks more successively be respectively 30%, 40% and 50%, figure in the diagrammatic representation of different densities.As figure, be set to minimum packed density, 30% from the block that efficient circuit is nearest, block farthest arranges the highest density, and 50%, middle block packed density is set to 40%.The effect of such filling is, the filling block nearest apart from efficient circuit will reduce the interference of circuit, and in chip, density homogeneity increases.
Certainly, according to actual conditions and specific requirement, fill block and can be divided into varying number, difformity, increase progressively according to distinct methods density.Such as in order to increase density homogeneity in chip larger, can filling block be got thinner.For another example, the shape of block can change according to the shape of efficient circuit and distribution, and density increases progressively can be made also can be at random regularly.The packed density desired value of each block can be a series of given constant, and its value is according to process requirements setting.Fill area also can be a series of given constant to the distance of limited circuit, and its value according to process requirements setting, and should be more than or equal to the redundant pattern that allows in the design rule minimum range to efficient circuit.
Claims (8)
1. a silicon chip redundant pattern fill method, is characterized in that comprising:
According to the distance of efficient circuit on distance silicon chip, redundant pattern fill area is divided into n district;
The packed density value of setting n redundant pattern fill area, the area filling density value nearer apart from efficient circuit is less, and the area filling density value that distance efficient circuit is far away is larger.
2. fill method as claimed in claim 1, is characterized in that: the size of described redundant pattern fill area, and shape and packed density increase principle can be different according to specific requirement.
3. fill method as claimed in claim 1, is characterized in that: described redundant pattern fill area is divided into 3 districts, is from the close-by examples to those far off and respectively that to determine packed density value be 30%, 40%, 50% according to the distance apart from efficient circuit.
4. the silicon chip containing redundant pattern, comprise silicon chip, efficient circuit and redundant pattern, it is characterized in that: according to the distance apart from described efficient circuit, the fill area of described redundant pattern is divided into n district, and its redundant pattern packed density of the region nearer apart from described efficient circuit is less, and region its redundancy colleague packed density far away apart from described efficient circuit is larger.
5. silicon chip as claimed in claim 4, is characterized in that: the size of described redundant pattern fill area, and shape and density increase principle can be different according to specific requirement.
6. silicon chip as claimed in claim 4, is characterized in that: described redundant pattern fill area is divided into 3 districts, is from the close-by examples to those far off and respectively that to determine packed density value be 30%, 40%, 50% according to the distance apart from efficient circuit.
7. an integrated circuit (IC) products, is characterized in that, comprises the silicon chip that one of at least one piece of claim 4-6 is described wherein.
8. integrated circuit (IC) products as claimed in claim 7, is characterized in that: described product can be smart mobile phone or panel computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410693133.1A CN104409445A (en) | 2014-11-26 | 2014-11-26 | Silicon wafer redundant graph filling method and product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410693133.1A CN104409445A (en) | 2014-11-26 | 2014-11-26 | Silicon wafer redundant graph filling method and product |
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| CN104409445A true CN104409445A (en) | 2015-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410693133.1A Pending CN104409445A (en) | 2014-11-26 | 2014-11-26 | Silicon wafer redundant graph filling method and product |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107153720A (en) * | 2016-03-02 | 2017-09-12 | 中国科学院微电子研究所 | A kind of method and system of redundancy metal filling |
| CN111125992A (en) * | 2019-12-26 | 2020-05-08 | 上海华虹宏力半导体制造有限公司 | Filling method of redundant metal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446756A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for improving homogeneity of figure density of metal layer of silicon chip |
| CN102945302A (en) * | 2012-11-02 | 2013-02-27 | 上海华力微电子有限公司 | Method for dividing high-filling-rate redundant graph |
| CN103441096A (en) * | 2013-08-02 | 2013-12-11 | 上海华力微电子有限公司 | Filling method of redundant graphs |
-
2014
- 2014-11-26 CN CN201410693133.1A patent/CN104409445A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446756A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for improving homogeneity of figure density of metal layer of silicon chip |
| CN102945302A (en) * | 2012-11-02 | 2013-02-27 | 上海华力微电子有限公司 | Method for dividing high-filling-rate redundant graph |
| CN103441096A (en) * | 2013-08-02 | 2013-12-11 | 上海华力微电子有限公司 | Filling method of redundant graphs |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107153720A (en) * | 2016-03-02 | 2017-09-12 | 中国科学院微电子研究所 | A kind of method and system of redundancy metal filling |
| CN107153720B (en) * | 2016-03-02 | 2020-10-16 | 中国科学院微电子研究所 | Method and system for filling redundant metal |
| CN111125992A (en) * | 2019-12-26 | 2020-05-08 | 上海华虹宏力半导体制造有限公司 | Filling method of redundant metal |
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Application publication date: 20150311 |
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| RJ01 | Rejection of invention patent application after publication |