CN103116663A - Method for filling redundant metal and method for establishing redundant metal filling mode lookup table - Google Patents

Method for filling redundant metal and method for establishing redundant metal filling mode lookup table Download PDF

Info

Publication number
CN103116663A
CN103116663A CN201110364853XA CN201110364853A CN103116663A CN 103116663 A CN103116663 A CN 103116663A CN 201110364853X A CN201110364853X A CN 201110364853XA CN 201110364853 A CN201110364853 A CN 201110364853A CN 103116663 A CN103116663 A CN 103116663A
Authority
CN
China
Prior art keywords
filling
geometric parameter
fill pattern
look
structural unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201110364853XA
Other languages
Chinese (zh)
Other versions
CN103116663B (en
Inventor
马天宇
陈岚
叶甜春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201110364853.XA priority Critical patent/CN103116663B/en
Publication of CN103116663A publication Critical patent/CN103116663A/en
Application granted granted Critical
Publication of CN103116663B publication Critical patent/CN103116663B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention relates to the technical field of electronic design automation and semiconductor process manufacturing, in particular to a method for filling redundant metal. The method comprises the steps of firstly, conducting geometric parameter representation on a plurality of interconnection structures, filling redundant metal, conducting flatness simulation and capacitance extraction after filling to establish a filling lookup table of a redundant metal filling mode, then conducting structural unit division on a circuit layout and extracting geometric parameters of structural units, inquiring the filling lookup table according to the geometric parameters of the structural units, and obtaining the redundant metal filling mode of the structural units. The invention also provides a method for establishing the redundant metal filling mode lookup table. The invention not only satisfies the flatness requirement and the capacitance requirement, but also concentrates the workload in the process of establishing the filling lookup table, thereby reducing the workload when filling the redundant metal in the real design and accelerating the development speed.

Description

Fill method and the redundancy metal fill pattern look-up table method for building up of redundancy metal
Technical field
The present invention relates to electric design automation and semiconductor technology manufacturing technology field, be specifically related to a kind of method and redundancy metal fill pattern look-up table method for building up of filling redundancy metal.
Background technology
At integrated circuit (Integrated Circuit, IC) in manufacture process, usually adopt to comprise that the various deposition process of physical vapour deposition (PVD), chemical vapor deposition are deposited to metal, dielectric and other materials on the surface of silicon chip, to form the metal construction of layering.Circuit generally includes multi-layer metal structure, is connected by a plurality of metal filled through holes again between every one deck metal.Therefore, in manufacture process, the step of a key is to form the metal construction that connects between each layer with circuit, makes circuit have very high complicacy and current densities.
In order to obtain to make the necessary flatness of multilayer circuit, usually use chemically mechanical polishing (ChemicalMechanical Polishing, CMP) technique to make the planarization of metallic dielectric layer pattern.CMP technique is that the abrasive action of a kind of chemical corrosion effect by polishing fluid and ultramicron forms the grinding technics of bright and clean flat surfaces on polished dielectric surface, is acknowledged as present VLSI (very large scale integrated circuit) stage best material overall situation flattening method.
But be reduced to below 90nm when the circuit technology node, especially arrive 65nm and 45nm when following, CMP process surface thickness afterwards highlights the Dependence Problem of underlying metal pattern, because the variation in thickness that metal pattern difference produces can be greater than 30%.Also bring simultaneously two major issues: metal dish and oxide layer corrode.These two problems are also closely related with domain graphic feature such as metal live width and distance between centers of tracks.
Redundancy metal is filled a process as the domain post-processed, can be used for reducing the CMP flatness problem that causes due to pattern dependency.Before the CMP process, the redundancy metal filling material is filled out on wafer, thereby made the thickness after IC chip design CMP more consistent.And the problem that the redundancy metal filling brings is, owing to having added unnecessary metal between metal interconnecting wires, make line capacitance increase, and the increase of line capacitance can affect signal integrity (the Signal Integrity of circuit, and then cause the capability error of circuit SI).
Can affect the performance of circuit due to the increase of line capacitance after filling at redundancy metal, therefore need to guarantee the increase of line capacitance within the acceptable range in the redundancy metal filling process, so just must consider simultaneously that the flatness of redundancy metal filling requires and the electric capacity requirement.Satisfy simultaneously flatness requirement and electric capacity requirement in order to make redundancy metal fill, can carry out flatness information and capacitance information after flatness simulation and electric capacity extract the acquisition filling, if do not meet the demands, the redundancy metal fill pattern is improved.Extract to guarantee that the redundancy metal filling of carrying out meets a large amount of time of corresponding requirements needs but repeatedly carry out flatness simulation and electric capacity in design process, can affect the launch progress like this.
Summary of the invention
The object of the present invention is to provide a kind of method of filling redundancy metal, can either satisfy chip flatness and capacitance characteristic, can implement again redundancy metal within a short period of time and fill.
Another object of the present invention is to provide a kind of redundancy metal fill pattern look-up table method for building up.
In order to achieve the above object, the technical solution used in the present invention is:
A kind of method of filling redundancy metal comprises the steps:
(1) circuit layout is divided into one or more structural units;
(2) extract the geometric parameter of described structural unit;
(3) inquire about according to the geometric parameter of the described structural unit that extracts the geometric parameter filling look-up table corresponding with the redundancy metal fill pattern of having set up, obtain the redundancy metal fill pattern of described structural unit.
In such scheme, the geometric parameter of the described structural unit of described extraction comprises that interconnection line live width, interconnection line spacing and interconnection line in the structural unit that extracts described circuit layout is over against length.
In such scheme, described step (3) specifically comprises: if having the geometric parameter consistent with the geometric parameter of described structural unit in described filling look-up table, with the fill pattern of the fill pattern under the index of described consistent geometric parameter as described structural unit; If there is no the geometric parameter consistent with the geometric parameter of described structural unit in described filling look-up table, calculate the deviate of geometric parameter in the geometric parameter of described structural unit and described filling look-up table, with in described filling look-up table with the geometric parameter index of the geometric parameter deviate minimum of described structural unit under fill pattern as the fill pattern of described structural unit.
In such scheme, described redundancy metal fill pattern comprises with ranks or dislocation form fills redundancy metal to form the redundancy metal piece of geometric configuration.
A kind of method for building up of redundancy metal fill pattern look-up table comprises the steps:
A. after adopting respectively a plurality of geometric parameters to characterize to a plurality of interconnection structures, adopt respectively multiple redundancy metal fill pattern to fill;
B. every kind of redundancy metal fill pattern of each described interconnection structure is carried out flatness simulation and electric capacity extraction;
C. the fill pattern and the corresponding geometric parameter that all meet the demands according to flatness and electric capacity are set up the corresponding look-up table of filling.
In such scheme, described interconnection structure is two or many parallel metal line structures.
In such scheme, the geometric parameter in described steps A comprises that interconnection line live width, interconnection line spacing and interconnection line in described interconnection structure is over against length.
In such scheme, described step C specifically comprises: with the index of described geometric parameter as described filling look-up table, will with the corresponding fill pattern of described geometric parameter as search content, set up described index and search content and fill accordingly look-up table.
In such scheme, the interconnection line number of described structural unit equates with the interconnection line number of described interconnection structure.
Compare with the prior art scheme, the beneficial effect that the technical solution used in the present invention produces is as follows:
The present invention is by setting up the method for redundancy metal fill pattern look-up table, thereby realizes rapidly the redundancy metal of interconnection structure domain is filled.Adopt the present invention to carry out the redundancy metal filling and not only satisfied simultaneously flatness requirement and electric capacity requirement, but also being concentrated on to set up, workload fills in the look-up table process, thereby the workload when having reduced to carry out the redundancy metal filling in true design is with Speeding up development speed.
Description of drawings
The process flow diagram of the method for the filling redundancy metal that Fig. 1 provides for the embodiment of the present invention;
Fig. 2 is the schematic diagram of interconnection structure in the embodiment of the present invention;
Fig. 3-5 are the schematic diagram of three kinds of redundancy metal fill patterns in the embodiment of the present invention;
Fig. 6 is the schematic diagram of circuit layout in the embodiment of the present invention;
Fig. 7 carries out to circuit layout the schematic diagram that structural unit is divided in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, technical solution of the present invention is described in detail.
As shown in Figure 1, fill look-up table by foundation and realize interconnection structure in circuit layout is carried out the metal filled method of fast-speed redundancy thereby the embodiment of the present invention provides a kind of, the method realizes by following steps:
Step 100 designs a plurality of interconnection structures.Interconnection structure shown in the embodiment of the present invention comprises two parallel metal lines longitudinally, as shown in Figure 2.Parallel metal line structure shown in Figure 2 is only the example in the embodiment of the present invention, and in practice, interconnection structure can also be various interconnection structures common in circuit design, can be for example the network that many parallel metal lines consist of.Be pointed out that, these interconnection structures can comprise the interconnect line segment more than ten or ten.
Step 110 adopts a plurality of geometric parameters to characterize to each interconnection structure.In embodiments of the present invention, as shown in Figure 2, metal wire AB in the interconnection structure and A ' B ' are as example, geometric parameter comprises the live width w1 of metal wire AB and the live width w2 of metal wire A ' B ', distance s 1 between metal wire AB metal wire A ' in parallel B ', and metal wire AB with respect to its parallel metal lines A ' B ' over against length l.As shown in table 1 to the geometric parameter that interconnection structure extracts.During more than two, in like manner can extract corresponding geometric parameter when parallel metal lines in interconnection structure.
Table 1
w1，w2，s1，l 0.3，0.5，0.4，0.3 0.6，0.4，0.5，0.4 0.8，0.3，0.7，0.3
Step 120 adopts respectively a plurality of redundancy metal fill patterns to fill to each interconnection structure.In embodiments of the present invention, be the redundancy metal with the square shape of ranks form filling, as Fig. 3, Fig. 4 and shown in Figure 5.In practice, can adopt multiple fill pattern, fill redundancy metal to form the redundancy metal piece of the geometric configuratioies such as rectangle, circle with ranks or dislocation form, the present invention is not limited to this.And, spacing between each redundancy metal piece (being each square in Fig. 3, Fig. 4, Fig. 5) can be identical or different, and the distance of each redundancy metal piece distance interconnection line (being the metal wire in the embodiment of the present invention) also can be identical or different.In addition, due to the metal constructions that adopt in copper structure circuit in existing semiconductor technology, therefore the material of described redundancy metal is correspondingly selected copper more.But, those skilled in the art will appreciate that described redundancy metal is not limited to copper, so long as consistent the getting final product of Metal Phase of adopting with metal construction in the side circuit domain of electric capacity to be extracted.
Step 130 is carried out the flatness simulation to the redundancy metal fill pattern of each interconnection structure, finds out the fill pattern that meets the flatness requirement.The method of flatness simulation comprises the various chemically mechanical polishing simulation softwards of employing and chemically mechanical polishing modeling algorithm, for example can adopt commercial chemically mechanical polishing simulation softward (as the CMPAnalyzer of Mentor Graphics), the present invention is not restricted this.After flatness simulation, adopts certain rule to select and meet the fill pattern that flatness requires, rule can be for the metal dish of interconnection line less than the threshold value of presetting, but is not limited to this.As shown in Fig. 3-5, if fill pattern shown in Figure 5 can't satisfy the flatness requirement, and Fig. 3, fill pattern shown in Figure 4 satisfy the flatness requirement, choose Fig. 3, fill pattern shown in Figure 4.
Step 140 is carried out electric capacity and is extracted the fill pattern that flatness requires of meeting of each interconnection structure, finds out the fill pattern that meets the electric capacity requirement.The method that electric capacity extracts comprises that the various electric capacity of employing extract softwares and electric capacity extraction algorithm, for example can adopt commercial 3D electric capacity extracting tool, and the present invention is not restricted this.Then, according to certain rule, the fill pattern of carrying out the electric capacity extraction is distinguished, found out the fill pattern that meets the electric capacity requirement.Rule can be after using this fill pattern, and the recruitment of coupling capacitance is less than the threshold value that presets, but is not limited to this.Fig. 3, fill pattern shown in Figure 4 satisfy the flatness requirement, if fill pattern shown in Figure 3 can't satisfy the electric capacity requirement, and fill pattern shown in Figure 4 satisfies the electric capacity requirement, finally chooses fill pattern shown in Figure 4.
Step 150 to the fill pattern that resulting flatness and electric capacity all meet the demands, is set up the corresponding look-up table of filling.The filling look-up table that table 2 utilizes resulting fill pattern to set up for the embodiment of the present invention.
Table 2
w1，w2，s1，l 0.3，0.5，0.4，0.3 0.6，0.4，0.5，0.4 0.8，0.3，0.7，0.3
Fill pattern Pattern 1 Pattern 2 Mode 3
Wherein, fill look-up table comprise with geometric parameter (in the embodiment of the present invention, live width w1, w2 that step 110 is cited, distance s 1 and over against length l) as the index of look-up table, with the fill pattern that obtains as searching content.Be pointed out that, index is not limited to table 2 example, and the corresponding fill pattern of each index also can have a plurality of and be not limited to shown in table 2.In addition, for different fill patterns, only distinguished with pattern 1, pattern 2 etc. in table 2 example illustrated, can different fill patterns be numbered in practice, and be not limited only to the mode of differentiation shown in table 2.The present invention concentrates on workload to set up and fills in the look-up table process (step 110-step 140), thus the calculated amount when reducing circuit layout is carried out the redundancy metal filling, with Speeding up development speed.
Step 160 provides the circuit layout that comprises interconnection structure.Fig. 6 is for need filling the domain schematic diagram of redundancy metal, only for example and be not used in limitation the present invention.
Step 170 is carried out structure to circuit layout and is divided, to form one or more structural units.Particularly, the interconnection line number of the structural unit of circuit layout division equates with the interconnection line number of interconnection structure in step 100.Fig. 7 is the cited a kind of possible division methods of the embodiment of the present invention, and shown in Figure 7 is only example, and all division methods that meets above-mentioned requirements all are included in protection domain of the present invention.
Step 180 is extracted real geometric parameter to structural unit.The geometric parameter that this step is extracted is identical with the geometric parameter of sign in step 110.Needs are filled the geometric parameter that the structural unit of redundancy metal extracts as shown in table 3.
Table 3
w1，w2，s1，l 0.3，0.5，0.4，0.3 0.7，0.4，0.6，0.4 0.6，0.4，0.9，0.2
In embodiments of the present invention, one of them structural unit of choosing Fig. 7 extracts geometric parameter, the geometric parameter that extracts is live width w1, the w2 of two parallel metal lines in this structural unit, distance s 1 between every described metal wire metal wire in parallel, and wherein a wires with respect to its parallel metal lines over against length l, each parameter does not mark in Fig. 7, can be with reference to mark shown in Figure 2.
Step 190 is filled look-up table according to the real geometric parameter inquiry of extracting, and obtains the fill pattern of structural unit.Two kinds of situations are arranged this moment: situation one has the geometric parameter consistent with the real geometric parameter that extracts if fill, with the fill pattern of the fill pattern under the index of consistent geometric parameter as structural unit in look-up table; Situation two, if there is no the geometric parameter consistent with the geometric parameter of structural unit in the filling look-up table, can adopt the geometric parameter and the deviate of filling geometric parameter in look-up table of least square method or additive method computation structure unit, to fill in look-up table fill pattern under the geometric parameter index with the geometric parameter deviate minimum of structural unit as the fill pattern of structural unit.
Table 4 fills for inquiry the example that look-up table obtains the fill pattern of structural unit, wherein, the first row of data rows (be that geometric parameter is respectively " 0.3; 0.5; 0.4; 0.3 ", fill pattern is " pattern one ") is the example of situation one, and rear two row of data rows are the example of situation two.
Table 4
w1，w2，s1，l 0.3，0.5，0.4，0.3 0.7，0.4，0.6，0.4 0.6，0.4，0.9，0.2
Fill pattern Pattern 1 Pattern 2 Mode 3
By above step, can obtain the fill pattern of arbitrary structural unit in the circuit layout of interconnection structure.
The interconnection structure in circuit layout is carried out fast-speed redundancy metal filled before, set up in advance and fill look-up table, carrying out fast-speed redundancy when metal filled, need not to set up again the filling look-up table at every turn, can directly carry out structure to circuit layout divides, to form one or more structural units, then structural unit is extracted real geometric parameter, according to the geometric parameter filling look-up table corresponding with the redundancy metal fill pattern that the geometric parameter inquiry of the structural unit that extracts has been set up, obtain the redundancy metal fill pattern of structural unit.The present invention is by setting up the method for redundancy metal fill pattern look-up table, thereby realizes rapidly the redundancy metal of interconnection structure domain is filled.The invention has the advantages that: on the one hand, considered flatness that redundancy metal is filled and electrical characteristics this two aspects, the requirement of this two aspect has been satisfied in the filling of adopting the present invention to carry out simultaneously; On the other hand, workload is concentrated on to set up fill in the look-up table process, thus the workload when having reduced to carry out the redundancy metal filling in true design, with Speeding up development speed.By the method that redundancy metal provided by the invention is filled, can either guarantee to fill the chip after the redundancy metal and meet that flatness requires and the electric capacity constraint, can guarantee again time that filling process needs and workload within the acceptable range.
The above is only the preferred embodiments of the present invention, is not limited to the present invention, and to those skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (9)

1. a method of filling redundancy metal, is characterized in that, comprises the steps:
(1) circuit layout is divided into one or more structural units;
(2) extract the geometric parameter of described structural unit;
(3) inquire about according to the geometric parameter of the described structural unit that extracts the geometric parameter filling look-up table corresponding with the redundancy metal fill pattern of having set up, obtain the redundancy metal fill pattern of described structural unit.
2. the method for filling redundancy metal as claimed in claim 1, is characterized in that, the geometric parameter of the described structural unit of described extraction comprises that interconnection line live width, interconnection line spacing and interconnection line in the structural unit that extracts described circuit layout is over against length.
3. the method for filling redundancy metal as claimed in claim 1, it is characterized in that, described step (3) specifically comprises: if having the geometric parameter consistent with the geometric parameter of described structural unit in described filling look-up table, with the fill pattern of the fill pattern under the index of described consistent geometric parameter as described structural unit; If there is no the geometric parameter consistent with the geometric parameter of described structural unit in described filling look-up table, calculate the deviate of geometric parameter in the geometric parameter of described structural unit and described filling look-up table, with in described filling look-up table with the geometric parameter index of the geometric parameter deviate minimum of described structural unit under fill pattern as the fill pattern of described structural unit.
4. the method for filling redundancy metal as claimed in claim 1, is characterized in that, described redundancy metal fill pattern comprises with ranks or dislocation form fills redundancy metal to form the redundancy metal piece of geometric configuration.
5. the method for building up of a redundancy metal fill pattern look-up table, comprise the steps:
A. after adopting respectively a plurality of geometric parameters to characterize to a plurality of interconnection structures, adopt respectively multiple redundancy metal fill pattern to fill;
B. every kind of redundancy metal fill pattern of each described interconnection structure is carried out flatness simulation and electric capacity extraction;
C. the fill pattern and the corresponding geometric parameter that all meet the demands according to flatness and electric capacity are set up the corresponding look-up table of filling.
6. the method for building up of redundancy metal fill pattern look-up table as claimed in claim 5, is characterized in that, described interconnection structure is two or many parallel metal line structures.
7. the method for building up of redundancy metal fill pattern look-up table as claimed in claim 5, is characterized in that, the geometric parameter in described steps A comprises that interconnection line live width, interconnection line spacing and interconnection line in described interconnection structure is over against length.
8. the method for building up of redundancy metal fill pattern look-up table as claimed in claim 5, it is characterized in that, described step C specifically comprises: with the index of described geometric parameter as described filling look-up table, to with the corresponding fill pattern of described geometric parameter as search content, set up described index and search content and fill accordingly look-up table.
9. the method for building up of redundancy metal fill pattern look-up table as claimed in claim 5, is characterized in that, the interconnection line number of described structural unit equates with the interconnection line number of described interconnection structure.
CN201110364853.XA 2011-11-17 2011-11-17 Method for filling redundant metal and method for establishing redundant metal filling mode lookup table Active CN103116663B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110364853.XA CN103116663B (en) 2011-11-17 2011-11-17 Method for filling redundant metal and method for establishing redundant metal filling mode lookup table

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110364853.XA CN103116663B (en) 2011-11-17 2011-11-17 Method for filling redundant metal and method for establishing redundant metal filling mode lookup table

Publications (2)

Publication Number Publication Date
CN103116663A true CN103116663A (en) 2013-05-22
CN103116663B CN103116663B (en) 2016-01-20

Family

ID=48415036

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110364853.XA Active CN103116663B (en) 2011-11-17 2011-11-17 Method for filling redundant metal and method for establishing redundant metal filling mode lookup table

Country Status (1)

Country Link
CN (1) CN103116663B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103400014A (en) * 2013-08-14 2013-11-20 上海华力微电子有限公司 Method for improving filling rate of redundant figures in long and narrow zone
CN106503374A (en) * 2016-10-28 2017-03-15 上海空间电源研究所 The structure of the compound semiconductor device of labyrinth describes method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024083A (en) * 2010-12-15 2011-04-20 中国科学院微电子研究所 Method for extracting capacitance of interconnection structure containing redundant metal
CN102063528A (en) * 2010-12-20 2011-05-18 西安电子科技大学 Method for extracting rhombus redundant filling parasitic capacitance based on lookup table algorithm
CN102130043A (en) * 2010-12-30 2011-07-20 中国科学院微电子研究所 Method for filling redundant metal

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024083A (en) * 2010-12-15 2011-04-20 中国科学院微电子研究所 Method for extracting capacitance of interconnection structure containing redundant metal
CN102063528A (en) * 2010-12-20 2011-05-18 西安电子科技大学 Method for extracting rhombus redundant filling parasitic capacitance based on lookup table algorithm
CN102130043A (en) * 2010-12-30 2011-07-20 中国科学院微电子研究所 Method for filling redundant metal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103400014A (en) * 2013-08-14 2013-11-20 上海华力微电子有限公司 Method for improving filling rate of redundant figures in long and narrow zone
CN106503374A (en) * 2016-10-28 2017-03-15 上海空间电源研究所 The structure of the compound semiconductor device of labyrinth describes method
CN106503374B (en) * 2016-10-28 2018-06-29 上海空间电源研究所 The structure of the compound semiconductor device of labyrinth describes method

Also Published As

Publication number Publication date
CN103116663B (en) 2016-01-20

Similar Documents

Publication Publication Date Title
CN102024083B (en) Method for extracting capacitance of interconnection structure containing redundant metal
CN102130043B (en) Method for filling redundant metal
CN103187522B (en) Manufacturing method of semiconductor device
US8645879B2 (en) Algorithm of Cu interconnect dummy inserting
CN102543853B (en) redundant metal filling method and integrated circuit layout structure
CN104077460A (en) Chemical mechanical polishing method and chip layout equivalent characteristic parameter extraction method
CN102495925B (en) Method and system for realizing redundant metal filling template
CN102222643A (en) Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device
Cho et al. Design and analysis of power distribution network (PDN) for high bandwidth memory (HBM) interposer in 2.5 D terabyte/s bandwidth graphics module
CN102521468A (en) Method and device for extracting parasitic parameters of interconnection line
CN109033580A (en) A kind of Layer assignment method applied to three dimensional integrated circuits
CN102063528A (en) Method for extracting rhombus redundant filling parasitic capacitance based on lookup table algorithm
CN103116663B (en) Method for filling redundant metal and method for establishing redundant metal filling mode lookup table
CN107004601A (en) Benefiting from the via autoregistration and short circuit of air gap integrated capacitance improves
Duplessis et al. Physical implementation of 3D integrated solenoids within silicon substrate for hybrid IC applications
CN107195561B (en) Chemical mechanical polishing defect detection method
CN103413001A (en) Through-silicon-via (TSV) three-dimensional coupling crosstalk noise model and modeling method thereof
CN105632956A (en) Method and system for evaluating surface appearance of chip after chemical mechanical polishing
CN102543858A (en) Manufacture method for improving W-CMP rear-surface flatness
Guiller et al. Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer
CN102881586A (en) Method for improving flatness of contact hole subjected to tungsten chemical mechanical polishing (CMP)
JP5431037B2 (en) Multilayer wiring, multilayer wiring dummy wiring arrangement method, semiconductor device and manufacturing method thereof
US20180165402A1 (en) Forming multi-sized through-silicon-via (tsv) structures
CN105097768A (en) Capacitor structure and manufacturing method thereof
CN102054068A (en) Method and device for distributing line network in chip design

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant