CN104409351A - Pmos晶体管的形成方法 - Google Patents
Pmos晶体管的形成方法 Download PDFInfo
- Publication number
- CN104409351A CN104409351A CN201410686773.XA CN201410686773A CN104409351A CN 104409351 A CN104409351 A CN 104409351A CN 201410686773 A CN201410686773 A CN 201410686773A CN 104409351 A CN104409351 A CN 104409351A
- Authority
- CN
- China
- Prior art keywords
- side wall
- pmos transistor
- silicon
- formation method
- transistor according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 21
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 230000002708 enhancing effect Effects 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 24
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract 3
- 125000004432 carbon atom Chemical group C* 0.000 abstract 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000010504 bond cleavage reaction Methods 0.000 description 24
- 230000007017 scission Effects 0.000 description 24
- 150000001721 carbon Chemical group 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- WSLDOOZREJYCGB-UHFFFAOYSA-N 1,2-Dichloroethane Chemical group ClCCCl WSLDOOZREJYCGB-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明公开了一种PMOS晶体管的形成方法,其通过在填充锗硅以形成源漏区之前,先对栅极的侧墙进行碳离子注入和退火工艺,使碳原子与侧墙表面的硅断键相结合,以消除硅断键,从而在后续填充锗硅时,阻止锗原子以及掺杂的硼原子与硅断键相结合,从而抑制栅极侧墙表面锗硅的淀积,改善侧墙缺陷。本发明较佳地还可使注入的碳原子与侧墙表面的氮断键相结合,以消除氮断键。本发明工艺与现有工艺兼容,具有较大应用价值。
Description
技术领域
本发明涉及半导体器件的制造技术领域,尤其涉及一种PMOS晶体管的形成方法。
背景技术
晶体管作为最基本的半导体器件目前正被广泛应用,随着半导体器件的元件密度和集成度的提高,晶体管的栅极尺寸变得比以往更短;然而,晶体管的栅极尺寸变短会使晶体管产生短沟道效应,进而产生漏电流,最终影响半导体器件的电学性能。目前,现有技术主要通过提高晶体管沟道区的应力,以提高载流子迁移,进而提高晶体管的驱动电流,减少晶体管中的漏电流。
一般而言,CMOS器件制造技术中将P型金属氧化物半导体场效应(PMOS)和N型金属氧化物半导体场效应(NMOS)分开处理,例如在PMOS器件的制造工艺中采用压应力的材料,而在NMOS器件中采用张应力的材料,以向沟道区施加适当的应力,从而提高载流子的迁移率。其中,嵌入锗硅技术(eSiGe)在PMOS晶体管的源漏区形成锗硅应力层,能够提高沟道空穴的迁移率而成为PMOS应力工程的主要技术之一。
现有技术在进行锗硅淀积时,不希望在栅极的氮化硅侧墙上出现锗硅层而影响后续工艺,所以选择性淀积工艺,工艺采用硅烷(SiH4)和二氯乙烯(DCS)作为硅源,采用锗烷(GeH4)作为锗源,并通入HCl改善外延生长的选择性,即使得锗硅层在硅衬底的外延生长速度较快,而在氮化硅侧墙上生长较慢,甚至不生长,通过一边淀积,一边利用HCl腐蚀的工艺步骤,去除侧墙上的锗硅。通常,为了确保良好的表面选择性,还需要用高温或其他工艺进行表面处理,以清理侧墙表面和源漏区表面的杂质。
然而,栅极的侧墙表面往往存在许多残留的硅断键,在外延锗硅时会与Ge相结合,使侧墙上的锗硅初始生长速度加快,在选择性淀积过后,仍然会在PMOS器件区域的侧墙上留下多余的锗硅,从而影响后续的工艺进行。同时,栅极侧墙表面还可能存在少量的氮断键,在进行选择性外延锗硅工艺时,Ge还会与侧墙表面的氮断键结合,而用来掺杂的B也会和侧墙中的硅断键和氮断键结合,从而在侧墙上产生大量的缺陷。
有鉴于此,急需开发一种新的PMOS晶体管形成方法,来改善现有锗硅选择性外延引起的栅极侧墙缺陷。
发明内容
本发明的目的在于弥补上述现有技术的不足,提供一种PMOS晶体管的形成方法,通过离子注入改善锗硅选择性外延引起的侧墙缺陷。
为实现上述目的,本发明提供一种PMOS晶体管的形成方法,其包括以下步骤:
步骤S01,提供半导体衬底,所述衬底上形成有栅极结构及栅极结构两侧的源漏区;
步骤S02,在所述栅极结构的侧壁上形成侧墙;
步骤S03,对所述侧墙表面进行碳离子注入并退火;
步骤S04,在所述栅极结构两侧的源漏区形成源漏凹槽;
步骤S05,在所述源漏凹槽内填充锗硅以形成锗硅源漏区。
进一步地,步骤S03中碳离子注入时注入倾斜角度为与硅片表面垂直线成22~30度。
进一步地,步骤S03中碳离子注入的注入能量为1Kev~5Kev,注入剂量为3E14~1E15。
进一步地,步骤S03中退火温度为900-1050℃。
进一步地,所述侧墙为氮化硅。
进一步地,步骤S02中形成侧墙包括采用等离子体增强化学气相沉积工艺(PECVD)沉积氮化硅。
进一步地,步骤S02形成侧墙的反应气体包括硅烷和氨气。
进一步地,步骤S02形成侧墙的反应温度为350-480℃,反应直流功率为350-600W。
进一步地,所述侧墙厚度为
进一步地,步骤S04采用刻蚀形成源漏凹槽,步骤S05采用选择性外延工艺生长锗硅。
本发明提供的PMOS晶体管的形成方法,在填充锗硅以形成源漏区之前,先对栅极的侧墙进行碳离子注入和退火工艺,使碳原子与侧墙表面的硅断键相结合,以消除硅断键,从而在后续填充锗硅时,阻止锗原子以及掺杂的硼原子与硅断键相结合,从而抑制栅极侧墙表面锗硅的淀积,改善侧墙缺陷。本发明较佳地还可使注入的碳原子与侧墙表面的氮断键相结合,以消除氮断键。本发明工艺与现有工艺兼容,具有较大应用价值。
附图说明
为能更清楚理解本发明的目的、特点和优点,以下将结合附图对本发明的较佳实施例进行详细描述,其中:
图1至图5为本发明一实施例的PMOS晶体管形成方法的各步骤结构示意图。
具体实施方式
在本发明的一个实施例中,提供一种PMOS晶体管的形成方法,本实施例以CMOS器件中的一组NMOS区和PMOS区为例说明PMOS晶体管的形成过程,但不以此为限。本实施例的形成方法具体包括以下步骤:
步骤S01,提供半导体衬底,衬底包括有NMOS区和PMOS区,NMOS区和PMOS区上各自形成有栅极结构及栅极结构两侧的源漏区。
具体地,如图1所示,提供一P型半导体衬底100,在衬底100上外延生长一层P型单晶硅层101,在单晶硅层101中制作P阱110、N阱120以及浅沟槽隔离102,在P阱110中形成N+源漏区112并形成PMOS栅极结构111,在N阱120中形成P+源漏区122并形成NMOS栅极结构121。
步骤S02,如图1所示,在PMOS栅极结构111的侧壁上形成第一侧墙113,在NMOS栅极结构121的侧壁上形成第二侧墙123。
其中,第一侧墙和第二侧墙为氮化硅,形成第一侧墙和第二侧墙包括采用等离子体增强化学气相沉积工艺(PECVD)沉积氮化硅,第一侧墙和第二侧墙的厚度优选为实际应用中,形成侧墙的反应温度较佳地为350-480℃,反应直流功率较佳地为350-600W,反应气体包括硅烷和氨气。
步骤S03,由于本实施例NMOS区的存在,在制作PMOS晶体管时,需要把NMOS区用光刻掩模103覆盖住,如图2所示;随后,如图3所示,对第一侧墙113表面进行碳离子注入并退火。由于步骤S02形成的氮化硅第一侧墙113表面会存在很多未结合的硅断键,本步骤通过碳离子注入和退火工艺,可以使注入的碳原子与第一侧墙113表面的硅断键相结合,以消除硅断键。
本步骤中,碳离子注入的注入剂量可以根据实际需要进行调节,优选为至少与第一侧墙表面的所有硅断键相结合;碳离子注入的注入倾斜角度较佳地为与硅片表面垂直线成22-30度,以使注入可以完全覆盖第一侧墙的表面。实际应用中,碳离子注入的注入能量优选1Kev~5Kev,注入剂量可以是3E14~1E15。本步骤中,采用高温退火以激活碳原子,以与硅断键相结合,较佳地退火温度为900-1050℃,退火时间可根据器件要求而定。
步骤S04,如图4所示,在PMOS栅极结构111两侧的P+源漏区112形成源漏凹槽114。
其中,本步骤可采用本领域常用的刻蚀工艺。
步骤S05,如图5所示,在源漏凹槽114内填充锗硅以形成锗硅源漏区115,从而完成PMOS晶体管的制作。
其中,本步骤可采用本领域常用的选择性外延工艺生长锗硅。由于在本步骤填充锗硅以形成源漏区之前,先对栅极的侧墙进行碳离子注入和退火工艺,使碳原子与侧墙表面的硅断键相结合,以消除硅断键,从而阻止本步骤中锗原子以及掺杂的硼原子与硅断键相结合,从而抑制栅极侧墙表面锗硅的淀积,改善侧墙缺陷。
在实际应用中,步骤S02形成的氮化硅侧墙表面还可能会存在未结合的氮断键,步骤S03中碳离子注入的注入剂量包括至少与所有硅断键和氮断键相结合。通过碳原子与侧墙表面的氮断键相结合,以消除氮断键,从而在后续填充锗硅时,阻止锗原子以及掺杂的硼原子与氮断键相结合,从而抑制栅极侧墙表面锗硅的淀积,改善侧墙缺陷。
实际应用中,步骤S05之后还包括形成CMOS器件的铜后道等工艺,可采用本领域常规手段,故不再赘述。
Claims (10)
1.一种PMOS晶体管的形成方法,其特征在于,其包括以下步骤:
步骤S01,提供半导体衬底,所述衬底上形成有栅极结构及栅极结构两侧的源漏区;
步骤S02,在所述栅极结构的侧壁上形成侧墙;
步骤S03,对所述侧墙表面进行碳离子注入并退火;
步骤S04,在所述栅极结构两侧的源漏区形成源漏凹槽;
步骤S05,在所述源漏凹槽内填充锗硅以形成锗硅源漏区。
2.根据权利要求1所述的PMOS晶体管的形成方法,其特征在于:步骤S03中碳离子注入时注入倾斜角度为与硅片表面垂直线成22~30度。
3.根据权利要求1所述的PMOS晶体管的形成方法,其特征在于:步骤S03中碳离子注入的注入能量为1Kev~5Kev,注入剂量为3E14~1E15。
4.根据权利要求1至3任一项所述的PMOS晶体管的形成方法,其特征在于:步骤S03中退火温度为900-1050℃。
5.根据权利要求1至3任一项所述的PMOS晶体管的形成方法,其特征在于:所述侧墙为氮化硅。
6.根据权利要求5所述的PMOS晶体管的形成方法,其特征在于:步骤S02中形成侧墙包括采用等离子体增强化学气相沉积工艺沉积氮化硅。
7.根据权利要求6所述的PMOS晶体管的形成方法,其特征在于:步骤S02形成侧墙的反应气体包括硅烷和氨气。
8.根据权利要求7所述的PMOS晶体管的形成方法,其特征在于:步骤S02形成侧墙的反应温度为350-480℃,反应直流功率为350-600W。
9.根据权利要求1至3任一项所述的PMOS晶体管的形成方法,其特征在于:所述侧墙厚度为
10.根据权利要求1至3任一项所述的PMOS晶体管的形成方法,其特征在于:步骤S04采用刻蚀形成源漏凹槽,步骤S05采用选择性外延工艺生长锗硅。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410686773.XA CN104409351B (zh) | 2014-11-25 | 2014-11-25 | Pmos晶体管的形成方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410686773.XA CN104409351B (zh) | 2014-11-25 | 2014-11-25 | Pmos晶体管的形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104409351A true CN104409351A (zh) | 2015-03-11 |
CN104409351B CN104409351B (zh) | 2018-04-06 |
Family
ID=52646968
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410686773.XA Active CN104409351B (zh) | 2014-11-25 | 2014-11-25 | Pmos晶体管的形成方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104409351B (zh) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060228842A1 (en) * | 2005-04-07 | 2006-10-12 | Freescale Semiconductor, Inc. | Transistor fabrication using double etch/refill process |
CN102362344A (zh) * | 2008-12-31 | 2012-02-22 | 先进微装置公司 | 有具逐渐成形构造的嵌入应变引发材料的晶体管 |
US20120068268A1 (en) * | 2010-09-22 | 2012-03-22 | Hsiao Tsai-Fu | Transistor structure and method of fabricating the same |
CN103035523A (zh) * | 2011-09-30 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | 一种晶体管形成方法 |
-
2014
- 2014-11-25 CN CN201410686773.XA patent/CN104409351B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060228842A1 (en) * | 2005-04-07 | 2006-10-12 | Freescale Semiconductor, Inc. | Transistor fabrication using double etch/refill process |
CN102362344A (zh) * | 2008-12-31 | 2012-02-22 | 先进微装置公司 | 有具逐渐成形构造的嵌入应变引发材料的晶体管 |
US20120068268A1 (en) * | 2010-09-22 | 2012-03-22 | Hsiao Tsai-Fu | Transistor structure and method of fabricating the same |
CN103035523A (zh) * | 2011-09-30 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | 一种晶体管形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN104409351B (zh) | 2018-04-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7482211B2 (en) | Junction leakage reduction in SiGe process by implantation | |
US9698249B2 (en) | Epitaxy in semiconductor structure and manufacturing method of the same | |
US7553717B2 (en) | Recess etch for epitaxial SiGe | |
US8610175B2 (en) | Semiconductor device and manufacturing method thereof | |
KR100657395B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US7968413B2 (en) | Methods for forming a transistor | |
KR101720835B1 (ko) | Mos 디바이스에 매립된 게르마늄 배리어 | |
US20070298557A1 (en) | Junction leakage reduction in SiGe process by tilt implantation | |
US8889501B2 (en) | Methods for forming MOS devices with raised source/drain regions | |
US20080017931A1 (en) | Metal-oxide-semiconductor transistor device, manufacturing method thereof, and method of improving drain current thereof | |
US20150001583A1 (en) | Novel embedded shape sige for nfet channel strain | |
US10763328B2 (en) | Epitaxial semiconductor material grown with enhanced local isotropy | |
US9209299B2 (en) | Transistor device and fabrication method | |
CN102569082B (zh) | 用于制作嵌入式锗硅应变pmos器件结构的方法 | |
CN104064521B (zh) | 半导体工艺方法以及半导体结构 | |
CN103943504A (zh) | 一种半导体器件及其制备方法 | |
US20080206965A1 (en) | STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY | |
US8587026B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2007227721A (ja) | 半導体装置およびその製造方法 | |
US9412869B2 (en) | MOSFET with source side only stress | |
CN104409351A (zh) | Pmos晶体管的形成方法 | |
CN110364436B (zh) | 半导体器件及其形成方法 | |
WO2011052108A1 (ja) | 半導体装置及びその製造方法 | |
US9112054B2 (en) | Methods of manufacturing semiconductor devices | |
US20170213897A1 (en) | Method of fabricating pmos devices with embedded sige |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
EXSB | Decision made by sipo to initiate substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |