CN104409342A - Front metal evaporation method for wafer - Google Patents
Front metal evaporation method for wafer Download PDFInfo
- Publication number
- CN104409342A CN104409342A CN201410667912.4A CN201410667912A CN104409342A CN 104409342 A CN104409342 A CN 104409342A CN 201410667912 A CN201410667912 A CN 201410667912A CN 104409342 A CN104409342 A CN 104409342A
- Authority
- CN
- China
- Prior art keywords
- wafer
- steams
- tin layer
- front metal
- golden method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000001883 metal evaporation Methods 0.000 title abstract 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 230000008020 evaporation Effects 0.000 claims abstract description 6
- 238000001704 evaporation Methods 0.000 claims abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 29
- 239000010931 gold Substances 0.000 claims description 29
- 229910052737 gold Inorganic materials 0.000 claims description 29
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000010025 steaming Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000009825 accumulation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010327 methods by industry Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physical Vapour Deposition (AREA)
Abstract
The invention provides a front metal evaporation method for a wafer. The method comprises the steps: step 1, forming a TiN layer on the front metal evaporation surface of a wafer to be performed with front metal evaporation; step 2, arranging the wafer to be performed with front metal evaporation on a wafer bearing ring, exposing the TiN layer on the front metal evaporation surface at the lower side and covering an anti-pollution cover on the top of the wafer to be performed with front metal evaporation; and step 3, forming front metal by the evaporation process on the TiN layer of the front metal evaporation surface. In the front metal evaporation method for the wafer, one TiN layer is arranged on the wafer before the front metal layer is formed; secondary electrons generated in the evaporation process are educed by utilizing a grounding ring and the electrons are prevented from being accumulated in the oxide layer of a gate electrode, so that the threshold voltage deviation of the device formed in the wafer can be prevented.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of wafer frontside and steam golden method.
Background technology
In wafer process engineering, when manufacturing some semiconductor device or when manufacturing the integrated circuit of certain type, the situation needing wafer to be carried out to front metal (front meta l) deposition (namely wafer frontside steams gold process) can be run into.
Particularly, Fig. 1 schematically shows and steams according to the wafer frontside of prior art the structure that golden method adopts.Fig. 2 schematically shows and steams according to the wafer frontside of prior art the structure that golden method obtains.
As depicted in figs. 1 and 2, steam golden method according to the wafer frontside of prior art and generally will treat that front is steamed golden wafer 30 and is arranged on wafer carrying ring 20, thus expose from below treat front steam gold surface, and treating front steam gold wafer 30 top cover on anti-pollution cover 10.Subsequently, can treat steaming gold surface in front forms front metal 40.Generally, from treating that front is steamed on the outside direction of gold surface, front metal 40 comprises the lamination of Ti/Ni/Ag.
But between the front metal depositional stage of wafer, threshold voltage (Vt) produces serious skew due to evaporation technology.Specifically, between front metal depositional stage, because sub-bundle clashes into source metal, can produce secondary high energy electron thus, then secondary high energy electron enters into grid oxic horizon, and accumulation electronics, causes threshold voltage (Vt) to offset.
Therefore, it is desirable to provide a kind of wafer frontside of threshold voltage shift that can prevent to steam golden method.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of wafer frontside of threshold voltage shift that can prevent to steam golden method.
In order to realize above-mentioned technical purpose, according to the present invention, providing a kind of wafer frontside and steaming golden method, comprise the following step performed successively:
First step, for treating that treating that front is steamed in gold surface and forming TiN layer of the wafer of gold is steamed in front;
Second step, for treating that front is steamed golden wafer and is arranged in wafer carrying ring, thus exposes the TiN layer treated in front steaming gold surface from below, and is treating that anti-pollution cover in golden wafer top cover is steamed in front;
Third step, for treating the TiN layer in front steaming gold surface forms front metal by evaporation technology.
Preferably, treating that treating that front is steamed in gold surface and forming TiN layer of the wafer of gold is steamed in front by the mode of sputtering in a first step.
Preferably, in a first step, TiN layer cover completely by treat front steam gold wafer treat front steam gold surface.
Preferably, on the direction outside from TiN layer, front metal comprises the lamination of Ti/Ni/Ag.
Preferably, described wafer frontside is steamed golden method and is also comprised and carry out wet etching to TiN layer after the third step.
Preferably, structure and the pattern of front metal is formed by wet etching.
Preferably, structure and the pattern of front metal is formed by selective wet etching.
Preferably, described wafer frontside steams golden method for semiconductor device manufacture.
Preferably, described wafer frontside steams golden method for MOS transistor manufacture.
Steam in golden method in wafer frontside of the present invention, on wafer, a TiN layer was arranged before front metal layer is formed, and utilize ground loop to derive the secondary electron produced in evaporate process, prevent accumulation electronics in grid oxic horizon, thus the threshold voltage shift of the device formed in wafer can be prevented.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows and steams according to the wafer frontside of prior art the process unit and wafer arrangement that golden method adopts.
Fig. 2 schematically shows and steams according to the wafer frontside of prior art the semiconductor crystal circle structure that golden method obtains.
Fig. 3 schematically shows the first step that wafer frontside according to the preferred embodiment of the invention steams golden method.
Fig. 4 schematically shows the second step that wafer frontside according to the preferred embodiment of the invention steams golden method.
Fig. 5 schematically shows the third step that wafer frontside according to the preferred embodiment of the invention steams golden method.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 3 to Fig. 5 schematically show each step that wafer frontside according to the preferred embodiment of the invention steams golden method.
As shown in Figures 3 to 5, wafer frontside is steamed golden method and is comprised the following step performed successively according to the preferred embodiment of the invention:
First step, for treating that treating that front is steamed in gold surface and forming TiN layer 50 of the wafer 30 of gold is steamed in front, as shown in Figure 3;
Such as, preferably, can treat that treating that front is steamed in gold surface and forming TiN layer 50 of the wafer 30 of gold is steamed in front by the mode of sputtering.Preferably, TiN layer 50 cover completely by treat front steam gold wafer 30 treat front steam gold surface.
Second step, for treating that front is steamed golden wafer 30 and is arranged in wafer carrying ring 20, thus exposes the TiN layer 50 treated in front steaming gold surface from below, and is treating that anti-pollution cover 10 in golden wafer 30 top cover is steamed in front, as shown in Figure 4.
Third step, for treating the TiN layer 50 in front steaming gold surface forms front metal 40 by evaporation technology, as shown in Figure 5.
Generally, on the direction outside from TiN layer 50, front metal 40 comprises the lamination of Ti/Ni/Ag.For any those of ordinary skill in the art, be understandable that, in third step, front metal 40 structure and pattern that wet etching (preferably, alternative wet etching) forms expectation can be passed through.
And, for any those of ordinary skill in the art, be understandable that, the etching of TiN layer 50 can be carried out after the third step, to form the structure of expectation.
Such as, preferably, described wafer frontside steams golden method for semiconductor device manufacture.
Such as, preferably, described wafer frontside steams golden method for MOS transistor manufacture.
Thus, steam in golden method in the wafer frontside of the preferred embodiment of the present invention, on wafer, a TiN layer was arranged before front metal layer is formed, and utilize ground loop to derive the secondary electron produced in evaporate process, avoid accumulation electronics in grid oxic horizon, thus the threshold voltage shift of the device formed in wafer can be prevented.
The wafer frontside of the preferred embodiment of the present invention is steamed golden method and be can be used for MOS transistor manufacture.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the term " first " in specification, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in specification, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. wafer frontside steams a golden method, it is characterized in that comprising the following step performed successively:
First step, for treating that treating that front is steamed in gold surface and forming TiN layer of the wafer of gold is steamed in front;
Second step, for treating that front is steamed golden wafer and is arranged in wafer carrying ring, thus exposes the TiN layer treated in front steaming gold surface from below, and is treating that anti-pollution cover in golden wafer top cover is steamed in front;
Third step, for treating the TiN layer in front steaming gold surface forms front metal by evaporation technology.
2. wafer frontside according to claim 1 steams golden method, it is characterized in that, is treating that treating that front is steamed in gold surface and forming TiN layer of the wafer of gold is steamed in front in a first step by the mode of sputtering.
3. wafer frontside according to claim 1 and 2 steams golden method, it is characterized in that, in a first step, TiN layer cover completely by treat front steam gold wafer treat front steam gold surface.
4. wafer frontside according to claim 1 and 2 steams golden method, it is characterized in that, on the direction outside from TiN layer, front metal comprises the lamination of Ti/Ni/Ag.
5. wafer frontside according to claim 1 and 2 steams golden method, characterized by further comprising and carries out wet etching to TiN layer after the third step.
6. wafer frontside according to claim 1 and 2 steams golden method, characterized by further comprising: the structure and the pattern that form front metal.
7. wafer frontside according to claim 6 steams golden method, it is characterized in that, is formed structure and the pattern of front metal by wet etching.
8. wafer frontside according to claim 7 steams golden method, it is characterized in that, is formed structure and the pattern of front metal by selective wet etching.
9. wafer frontside according to claim 1 and 2 steams golden method, it is characterized in that, described wafer frontside steams golden method for semiconductor device manufacture.
10. wafer frontside according to claim 1 and 2 steams golden method, it is characterized in that, described wafer frontside steams golden method for MOS transistor manufacture.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410667912.4A CN104409342A (en) | 2014-11-20 | 2014-11-20 | Front metal evaporation method for wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410667912.4A CN104409342A (en) | 2014-11-20 | 2014-11-20 | Front metal evaporation method for wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104409342A true CN104409342A (en) | 2015-03-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410667912.4A Pending CN104409342A (en) | 2014-11-20 | 2014-11-20 | Front metal evaporation method for wafer |
Country Status (1)
| Country | Link |
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| CN (1) | CN104409342A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7122414B2 (en) * | 2002-12-03 | 2006-10-17 | Asm International, Inc. | Method to fabricate dual metal CMOS devices |
| CN101217112A (en) * | 2007-01-04 | 2008-07-09 | 中国科学院微电子研究所 | A preparation method of nanometer scale W/TiN compound refractory metal bar |
| US20100155860A1 (en) * | 2008-12-24 | 2010-06-24 | Texas Instruments Incorporated | Two step method to create a gate electrode using a physical vapor deposited layer and a chemical vapor deposited layer |
| US20130001708A1 (en) * | 2011-06-30 | 2013-01-03 | Pierre Caubet | Transistors having a gate comprising a titanium nitride layer and method for depositing this layer |
| CN203878204U (en) * | 2014-05-23 | 2014-10-15 | 北方广微科技有限公司 | Device for enhancing film uniformity on sputtering system |
-
2014
- 2014-11-20 CN CN201410667912.4A patent/CN104409342A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7122414B2 (en) * | 2002-12-03 | 2006-10-17 | Asm International, Inc. | Method to fabricate dual metal CMOS devices |
| CN101217112A (en) * | 2007-01-04 | 2008-07-09 | 中国科学院微电子研究所 | A preparation method of nanometer scale W/TiN compound refractory metal bar |
| US20100155860A1 (en) * | 2008-12-24 | 2010-06-24 | Texas Instruments Incorporated | Two step method to create a gate electrode using a physical vapor deposited layer and a chemical vapor deposited layer |
| US20130001708A1 (en) * | 2011-06-30 | 2013-01-03 | Pierre Caubet | Transistors having a gate comprising a titanium nitride layer and method for depositing this layer |
| CN203878204U (en) * | 2014-05-23 | 2014-10-15 | 北方广微科技有限公司 | Device for enhancing film uniformity on sputtering system |
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| RJ01 | Rejection of invention patent application after publication | ||
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Application publication date: 20150311 |