CN104407617A - Programmable aircraft attitude control IP core - Google Patents

Abstract

The invention discloses a programmable aircraft attitude control IP core, which comprises a first on-chip peripheral, a first DMA channel, a filtering arithmetic unit for respectively performing filtering processing on triaxial acceleration, triaxial angular velocity and triaxial magnetic field data, an attitude fusion computing cluster which is connected with the filtering arithmetic unit and is used for performing attitude fusion on the filtered triaxial acceleration, triaxial angular velocity and triaxial magnetic field data to comput and output an Euler angle of an aircraft, a PID arithmetic cluster connected with the attitude fusion computing cluster, a second DMA channel, and a second on-chip peripheral for transferring the Euler angle transferred from the second DMA channel to the aircraft. The attitude of the aircraft is correspondingly controlled by a hardware mode, the reaction delay of a control system is substantially reduced by the use of a special circuit compared with a singlechip microcomputer or CPU control, and the singlechip microcomputer or CPU which is originally in an attitude control state is freed from an algorithm.

Description

Aircraft manufacturing technology IP kernel able to programme

Technical field

The present invention relates to aircraft manufacturing technology field, be specially a kind of aircraft manufacturing technology IP kernel able to programme.

Background technology

Aircraft when orbital motion, in order to complete born task, must have certain attitude according to track flight and spacecraft, during as four rotor hovering flights, needs and state that reference field keeps attitude parallel.For aircraft, when it is in state of flight, attitude control system needs the deflection angle of each axis obtaining aircraft, then by filtering algorithm by each sensing data filtering process, obtain the stable data of each sensor, then attitude blending algorithm also will be used to carry out drift correction and fusion to each sensor, and integration goes out hypercomplex number and the Eulerian angle of aircraft, is revised aircraft propulsion finally by pid algorithm; Aforementioned each sensor generally comprises acceleration transducer, angular-rate sensor and magnetic field sensor.

Attitude control system of the prior art, generally adopt the framework that universal cpu+general A/D sampling+general D/A exports, this architecture design is simple, and universal cpu is identical with existing programming model.Adopt and mean that universal cpu needs the moment to carry out the output of the acquisition of A/D sampling, the filtering of sensing data, the fusion of attitude, the calculating of pid control parameter and D/A in this way, for general flush bonding processor, this operand is very huge, processor often cannot be reallocated among other application, some designs and framework is made to have to adopt plural universal cpu, one of them is for gesture stability, and another is for realizing airborne application; Meanwhile, for gesture stability process, its sensing data has the data characteristic of obvious Producer-consumer problem, and existing universal cpu is for control intensive applications, and cannot accomplish these data stream of parallel processing, thus the treatment effeciency of whole system reduces greatly; Attitude control system of the prior art, some adopts the design of universal cpu+hardware PID, and this design only can alleviate the computing pressure of PID part, very micro-for the effect improving whole attitude control system.

Summary of the invention

The present invention is directed to the proposition of above problem, and develop a kind of aircraft manufacturing technology IP kernel able to programme.

Technological means of the present invention is as follows:

A kind of aircraft manufacturing technology IP kernel able to programme, described IP kernel comprises:

First On-Chip peripheral; Described first On-Chip peripheral is for receiving the 3-axis acceleration of aircraft, three axis angular rates and three-axle magnetic field data;

Connect the first On-Chip peripheral and filtering operation device, for 3-axis acceleration, three axis angular rates and three-axle magnetic field data being transferred to a DMA passage of filtering operation device;

For carrying out the filtering operation device of filtering process respectively to 3-axis acceleration, three axis angular rates and three-axle magnetic field data; Described filtering operation device comprises 9 filtering operation unit; A kind of data in each filtering operation unit difference corresponding 3-axis acceleration, three axis angular rates and three-axle magnetic field data; Each filtering operation unit includes at least one in FIR filter, iir digital filter and sliding-window filtering device;

Connect filtering operation device, export the attitude fusion calculation bunch of the Eulerian angle of aircraft for carrying out attitude fusion calculation according to filtered 3-axis acceleration, three axis angular rates and three-axle magnetic field data;

Connect attitude fusion calculation bunch, for carrying out the PID arithmetic bunch of PID correction to the attitude fusion calculation bunch Eulerian angle exported;

Connect PID arithmetic bunch, for revised for PID Eulerian angle to be transferred to the 2nd DMA passage of aircraft by the second On-Chip peripheral;

Second On-Chip peripheral; The Eulerian angle that 2nd DMA channel transfer is come are transferred to aircraft by described second On-Chip peripheral;

Described attitude fusion calculation bunch comprises:

Connect filtering operation device, for the 3-axis acceleration after input filter, three axis angular rates and three-axle magnetic field data, and unitization input data processing bunch is carried out to 3-axis acceleration wherein and three-axle magnetic field data;

Connect quaternion product sub-clustering, for the hypercomplex number q0 exported for quaternion product sub-clustering, q1, q2, q3, obtains the intermediate flow compute cluster of hypercomplex number intermediate flow q0*q0, q0*q1, q0*q2, q0*q3, q1*q1, q1*q2, q1*q3, q2*q2, q2*q3 and q3*q3;

Connect input data processing bunch and intermediate flow compute cluster, for being converted to earth axes to the input data processing bunch three-axle magnetic field data exported by body axis system, and according to input data processing bunch 3-axis acceleration exported, three axis angular rates and three-axle magnetic field data, the hypercomplex number intermediate flow in conjunction with the output of intermediate flow compute cluster draws the coordinate conversion compute cluster of the hypercomplex number margin of error; Described coordinate conversion compute cluster utilizes formula $\left\{\begin{array}{c}{b}_x=\sqrt{[\left({h_x}^2\right)+\left({h_y}^2\right)]}\\ b_y=0\\ b_z=h_z\\ \end{array}\right.$ Calculate the three-axle magnetic field data (b being converted to earth axes by body axis system _x, b _y, b _z), wherein $\left\{\begin{array}{c}{h}_x=2*m_x*(0.5-q2*q2-q3*q3)+2*m_y*(q1*q2-q0*q3)+2*m_z*(q1*q3+q0*q2)\\ h_y=2*m_x*(q1*q2+q0*q3)+2*m_y*(0.5-q1*q1-q3*q3)+2*m_z*(q2*q3-q0*q1)\\ h_z=2*m_x*(q1*q3-q0*q2)+2*m_y*(q2*q3+q0*q1)+2*m_z*(0.5-q1*q1-q2*q2)\end{array}\right.$ , (m _x, m _y, m _z) be the input data processing bunch 3-axis acceleration data exported; Described coordinate conversion compute cluster utilizes formula $\left\{\begin{array}{c}{e}_x=(a_y*v_z-a_z*v_y)+(m_y*w_z-m_z*w_y)\\ e_y=(a_z*v_x-a_x*v_z)+(m_z*w_x-m_x*w_z)\\ e_z=(a_x*v_y-a_y*v_x)+(m_x*w_y-m_y*w_x)\end{array}\right.$ Calculate the hypercomplex number margin of error (e _x, e _y, e _z), wherein (a _x, a _y, a _z) export for input data processing bunch 3-axis acceleration data, $\left\{\begin{array}{c}{v}_x=2*(q1*q3-q0*q2)\\ v_y=2*(q0*q1+q2*q3)\\ v_z=q0*q0-q1*q1-q2*q2-q3*q3\end{array}\right.,$ $\left\{\begin{array}{c}{w}_x=2*b_x*(0.5-q2*q2-q3*q3)+2*b_z*(q1*q3-q0*q2)\\ w_y=2*b_x*(q1*q2-q0*q3)+2*b_z*(q0*q1+q2*q3)\\ w_z=2*b_x*(q0*q2+q1*q3)+2*b_z*(0.5-q1*q1-q2*q2)\end{array}\right.;$

Connection coordinate conversion compute cluster, performs the PI correction bunch of proportional integral correction for utilizing the hypercomplex number margin of error to three axis angular rate data; Described PI correction bunch utilizes formula $\left\{\begin{array}{c}{u}_x=g_x+K_p*e_x+{e_x}^{\′}\mathrm{Int}\\ u_y=g_y+K_p*e_y+{e_y}^{\′}\mathrm{Int}\\ u_z=g_z+K_p*e_z+{e_z}^{\′}\mathrm{Int}\end{array}\right.$ Obtain the revised three axis angular rate data (u of PI _x, u _y, u _z), wherein (g _x, g _y, g _z) input data processing bunch three axis angular rate data, the K that export _pfor the scale-up factor, (e of setting _x, e _y, e _z) for the hypercomplex number margin of error, $\left\{\begin{array}{c}{e_x}^{\′}\mathrm{Int}=e_x\mathrm{Int}+e_x*K_i\\ {e_y}^{\′}\mathrm{Int}=e_y\mathrm{Int}+e_y*K_i\\ {e_z}^{\′}\mathrm{Int}=e_z\mathrm{Int}+e_z*K_i\end{array}\right.,$ (e _xint, e _yint, e _zint) be to (the e in a upper integration period _x, e _y, e _z) respective integration, K _pfor the integral coefficient of setting;

Connect PI correction bunch, for generating the hypercomplex number integration compute cluster of current integration cycle hypercomplex number according to the hypercomplex number of revised three axis angular rate data and a upper integration period; Described hypercomplex number integration compute cluster utilizes formula $\left\{\begin{array}{c}{q0}^{\′}={q0}_b+(-{q1}_b*u_x-{q2}_b*u_y-{q3}_b*u_z)*\mathrm{halfT}\\ {q1}^{\′}={q1}_b+({q0}_b*u_x+{q2}_b*u_z-{q3}_b*u_y)*\mathrm{halfT}\\ {q2}^{\′}={q2}_b+({q0}_b*u_y-{q1}_b*u_z+{q3}_b*u_x)*\mathrm{halfT}\\ {q3}^{\′}={q3}_b+({q0}_b*u_z-{q1}_b*u_y-{q2}_b*u_x)*\mathrm{halfT}\end{array}\right.$ Draw the hypercomplex number q0 ' in current integration cycle, q1 ', q2 ', q3 ', wherein q0 _b, q1 _b, q2 _b, q3 _bfor the hypercomplex number, (u of a upper integration period _x, u _y, u _z) for the revised three axis angular rate data of PI, halfT be setup parameter; At generation current integration cycle hypercomplex number q0 ', q1 ', q2 ', the rear described hypercomplex number integration compute cluster of q3 ' also for q0 ', q1 ', q2 ', q3 ' carry out unitization and obtain q0, q1, q2, q3 export to intermediate flow compute cluster and rapid translating bunch;

Connect quaternion product sub-clustering, for the q0 exported according to quaternion product sub-clustering, q1, q2, q3 obtain the rapid translating bunch of Eulerian angle; Described rapid translating bunch utilizes formula $\left\{\begin{array}{c}\tan \left(\mathrm{Roll}\right)=\frac{(q1*q2+q3*q0)}{(q3*q3-q0*q0-q1*q1+q2*q2)}\\ \sin \left(\mathrm{Pitch}\right)=-2*(q0*q2-q3*q1)\\ \tan \left(\mathrm{Yaw}\right)=\frac{2*(q0*q1+q3*q2)}{(q3*q3+q0*q0-q1*q1-q2*q2)}\end{array}\right.$ Calculate the tangent trigonometric function value tan (Roll) of roll angle Roll, the sine trigonometric function value sin (Pitch) of angle of pitch Pitch, the tangent trigonometric function value tan (Yaw) of crab angle Yaw; Described rapid translating bunch also comprises and prestores the tangent trigonometric function value of each angle with corresponding each angle and the look-up table of sine trigonometric function value; Described rapid translating bunch according to tangent trigonometric function value tan (Roll), sine trigonometric function value sin (Pitch) and tangent trigonometric function value tan (Yaw), in conjunction with look-up table determination roll angle Roll, angle of pitch Pitch and crab angle Yaw;

In addition, described IP kernel also comprises quick interconnection; Described quick interconnection for connecting a DMA passage and filtering operation device, and connects attitude fusion calculation bunch and PID arithmetic bunch;

Further, described sliding-window filtering device comprises the first FIFO memory, adder unit, addition selector switch and the barrel shift register with 8 storage unit; The data sum that data sum, front 4 storage unit that described adder unit is deposited for front 2 storage unit calculating the first FIFO memory are deposited and the data sum that 8 storage unit are deposited; Described addition selector switch is used for selecting above-mentioned three data sums and exporting barrel shift register to;

Further, the output channel of the input selector that a described DMA passage all has 9 input channels with the 2nd DMA passage, input end is connected 9 input channels, the second FIFO memory connecting input selector output terminal, the outlet selector connecting the second FIFO memory and connection outlet selector;

Further, described quick interconnection comprises multiple input bus and multiple output bus; The selection being realized data by the break-make controlling each input bus and output bus is inputed or outputed;

In addition, IP kernel also comprises the control register group of connection the one DMA passage, fast interconnection, attitude fusion calculation bunch, PID arithmetic bunch; Described control register group is for controlling the selection operation of described input selector, control the break-make of each input bus and output bus, the scale-up factor that setting PI revises bunch and integral coefficient, and scale-up factor, integral coefficient and the differential coefficient of setting PID arithmetic bunch;

In addition, described IP kernel also comprises general quick compute cluster, and this general quick compute cluster comprises the bus monitor connecting each output bus and the microprocessor being connected bus monitor;

Described bus monitor comprise the Ll data caches register connecting output bus, the secondary data buffer register connecting Ll data caches register, connect Ll data caches register and receive with reference to limit value the first comparing unit, be connected the second comparing unit of Ll data caches register and secondary data buffer register and be connected the first result selector switch of the first comparing unit and the second comparing unit; Described first comparing unit is used for the current data deposited in Ll data caches register to compare with reference to limit value, and exceedes with reference to output abnormality signal during limit value in current data; Described second comparing unit is used for the current data deposited in upper data of the current data deposited in secondary data buffer register and Ll data caches register to compare, the second comparing unit output abnormality signal when the difference of data exceeds certain limit in current data and its; Described first result selector switch is selected above-mentioned two abnormal signals and sends to interrupt event maker; Described bus monitor also comprises the supervision register depositing preliminary data, the second result selector switch connecting output bus and supervision register; Described microprocessor disconnecting event generating and described second result selector switch, for when receiving the look-at-me that interrupt event maker sends, controlling the second result selector switch and exporting and monitor that the preliminary data deposited of register is on result bus;

Further, described microprocessor adopts very long instruction word (VLIW) collection framework, and Deep integrating is inner in IP kernel.

Owing to have employed technique scheme, aircraft manufacturing technology IP kernel able to programme provided by the invention, have employed hardware mode and corresponding control has been carried out to the attitude of aircraft, the use of special circuit makes the response delay of control system compare single-chip microcomputer or CPU controls significantly to reduce, and the single-chip microcomputer or CPU that were originally in gesture stability is freed from algorithm.

Accompanying drawing explanation

Fig. 1 is the structural representation of IP kernel of the present invention;

Fig. 2 is the structural representation of a DMA passage of the present invention and the 2nd DMA passage;

Fig. 3 is the structural representation of filtering operation device of the present invention;

Fig. 4 is the structural representation of filtering operation unit of the present invention;

Fig. 5 is the structural representation of sliding-window filtering device of the present invention;

Fig. 6 is the structural representation of attitude fusion calculation of the present invention bunch;

Fig. 7 is that the present invention inputs data processing bunch and carries out unitization schematic diagram;

Fig. 8 is the structural representation of PID arithmetic of the present invention bunch;

Fig. 9 is the schematic diagram that PID arithmetic unit of the present invention carries out PID arithmetic;

Figure 10 is the structural representation of the quick interconnection of the present invention;

Figure 11 is the structural representation of bus monitor of the present invention

Figure 12 is the structural representation of microprocessor of the present invention.

Embodiment

As shown in Figures 1 to 12, a kind of aircraft manufacturing technology IP kernel able to programme, described IP kernel comprises: the first On-Chip peripheral; Described first On-Chip peripheral is for receiving the 3-axis acceleration of aircraft, three axis angular rates and three-axle magnetic field data; Connect the first On-Chip peripheral and filtering operation device, for 3-axis acceleration, three axis angular rates and three-axle magnetic field data being transferred to a DMA passage of filtering operation device; For carrying out the filtering operation device of filtering process respectively to 3-axis acceleration, three axis angular rates and three-axle magnetic field data; Described filtering operation device comprises 9 filtering operation unit; A kind of data in each filtering operation unit difference corresponding 3-axis acceleration, three axis angular rates and three-axle magnetic field data; Each filtering operation unit includes at least one in FIR filter, iir digital filter and sliding-window filtering device; Connect filtering operation device, export the attitude fusion calculation bunch of the Eulerian angle of aircraft for carrying out attitude fusion calculation according to filtered 3-axis acceleration, three axis angular rates and three-axle magnetic field data; Connect attitude fusion calculation bunch, for carrying out the PID arithmetic bunch of PID correction to the attitude fusion calculation bunch Eulerian angle exported; Connect PID arithmetic bunch, for revised for PID Eulerian angle to be transferred to the 2nd DMA passage of aircraft by the second On-Chip peripheral; Second On-Chip peripheral; The Eulerian angle that 2nd DMA channel transfer is come are transferred to aircraft by described second On-Chip peripheral; Described attitude fusion calculation bunch comprises: connect filtering operation device, for the 3-axis acceleration after input filter, three axis angular rates and three-axle magnetic field data, and carry out unitization input data processing bunch to 3-axis acceleration wherein and three-axle magnetic field data; Connect quaternion product sub-clustering, for the hypercomplex number q0 exported for quaternion product sub-clustering, q1, q2, q3, obtains the intermediate flow compute cluster of hypercomplex number intermediate flow q0*q0, q0*q1, q0*q2, q0*q3, q1*q1, q1*q2, q1*q3, q2*q2, q2*q3 and q3*q3; Connect input data processing bunch and intermediate flow compute cluster, for being converted to earth axes to the input data processing bunch three-axle magnetic field data exported by body axis system, and according to input data processing bunch 3-axis acceleration exported, three axis angular rates and three-axle magnetic field data, the hypercomplex number intermediate flow in conjunction with the output of intermediate flow compute cluster draws the coordinate conversion compute cluster of the hypercomplex number margin of error; Described coordinate conversion compute cluster utilizes formula $\left\{\begin{array}{c}{b}_x=\sqrt{[\left({h_x}^2\right)+\left({h_y}^2\right)]}\\ b_y=0\\ b_z=h_z\\ \end{array}\right.$ Calculate the three-axle magnetic field data (b being converted to earth axes by body axis system _x, b _y, b _z), wherein $\left\{\begin{array}{c}{h}_x=2*m_x*(0.5-q2*q2-q3*q3)+2*m_y*(q1*q2-q0*q3)+2*m_z*(q1*q3+q0*q2)\\ h_y=2*m_x*(q1*q2+q0*q3)+2*m_y*(0.5-q1*q1-q3*q3)+2*m_z*(q2*q3-q0*q1)\\ h_z=2*m_x*(q1*q3-q0*q2)+2*m_y*(q2*q3+q0*q1)+2*m_z*(0.5-q1*q1-q2*q2)\end{array}\right.$ , (m _x, m _y, m _z) be the input data processing bunch 3-axis acceleration data exported; Described coordinate conversion compute cluster utilizes formula $\left\{\begin{array}{c}{e}_x=(a_y*v_z-a_z*v_y)+(m_y*w_z-m_z*w_y)\\ e_y=(a_z*v_x-a_x*v_z)+(m_z*w_x-m_x*w_z)\\ e_z=(a_x*v_y-a_y*v_x)+(m_x*w_y-m_y*w_x)\end{array}\right.$ Calculate the hypercomplex number margin of error (e _x, e _y, e _z), wherein (a _x, a _y, a _z) export for input data processing bunch 3-axis acceleration data, $\left\{\begin{array}{c}{v}_x=2*(q1*q3-q0*q2)\\ v_y=2*(q0*q1+q2*q3)\\ v_z=q0*q0-q1*q1-q2*q2-q3*q3\end{array}\right.,$ $\left\{\begin{array}{c}{w}_x=2*b_x*(0.5-q2*q2-q3*q3)+2*b_z*(q1*q3-q0*q2)\\ w_y=2*b_x*(q1*q2-q0*q3)+2*b_z*(q0*q1+q2*q3)\\ w_z=2*b_x*(q0*q2+q1*q3)+2*b_z*(0.5-q1*q1-q2*q2)\end{array}\right.;$ Connection coordinate conversion compute cluster, performs the PI correction bunch of proportional integral correction for utilizing the hypercomplex number margin of error to three axis angular rate data; Described PI correction bunch utilizes formula $\left\{\begin{array}{c}{u}_x=g_x+K_p*e_x+{e_x}^{\′}\mathrm{Int}\\ u_y=g_y+K_p*e_y+{e_y}^{\′}\mathrm{Int}\\ u_z=g_z+K_p*e_z+{e_z}^{\′}\mathrm{Int}\end{array}\right.$ Obtain the revised three axis angular rate data (u of PI _x, u _y, u _z), wherein (g _x, g _y, g _z) input data processing bunch three axis angular rate data, the K that export _pfor the scale-up factor, (e of setting _x, e _y, e _z) for the hypercomplex number margin of error, $\left\{\begin{array}{c}{e_x}^{\′}\mathrm{Int}=e_x\mathrm{Int}+e_x*K_i\\ {e_y}^{\′}\mathrm{Int}=e_y\mathrm{Int}+e_y*K_i\\ {e_z}^{\′}\mathrm{Int}=e_z\mathrm{Int}+e_z*K_i\end{array}\right.,$ (e _xint, e _yint, e _zint) be to (the e in a upper integration period _x, e _y, e _z) respective integration, K _pfor the integral coefficient of setting; Connect PI correction bunch, for generating the hypercomplex number integration compute cluster of current integration cycle hypercomplex number according to the hypercomplex number of revised three axis angular rate data and a upper integration period; Described hypercomplex number integration compute cluster utilizes formula $\left\{\begin{array}{c}{q0}^{\′}={q0}_b+(-{q1}_b*u_x-{q2}_b*u_y-{q3}_b*u_z)*\mathrm{halfT}\\ {q1}^{\′}={q1}_b+({q0}_b*u_x+{q2}_b*u_z-{q3}_b*u_y)*\mathrm{halfT}\\ {q2}^{\′}={q2}_b+({q0}_b*u_y-{q1}_b*u_z+{q3}_b*u_x)*\mathrm{halfT}\\ {q3}^{\′}={q3}_b+({q0}_b*u_z-{q1}_b*u_y-{q2}_b*u_x)*\mathrm{halfT}\end{array}\right.$ Draw the hypercomplex number q0 ' in current integration cycle, q1 ', q2 ', q3 ', wherein q0 _b, q1 _b, q2 _b, q3 _bfor the hypercomplex number, (u of a upper integration period _x, u _y, u _z) for the revised three axis angular rate data of PI, halfT be setup parameter; At generation current integration cycle hypercomplex number q0 ', q1 ', q2 ', the rear described hypercomplex number integration compute cluster of q3 ' also for q0 ', q1 ', q2 ', q3 ' carry out unitization and obtain q0, q1, q2, q3 export to intermediate flow compute cluster and rapid translating bunch; Connect quaternion product sub-clustering, for the q0 exported according to quaternion product sub-clustering, q1, q2, q3 obtain the rapid translating bunch of Eulerian angle; Described rapid translating bunch utilizes formula $\left\{\begin{array}{c}\tan \left(\mathrm{Roll}\right)=\frac{(q1*q2+q3*q0)}{(q3*q3-q0*q0-q1*q1+q2*q2)}\\ \sin \left(\mathrm{Pitch}\right)=-2*(q0*q2-q3*q1)\\ \tan \left(\mathrm{Yaw}\right)=\frac{2*(q0*q1+q3*q2)}{(q3*q3+q0*q0-q1*q1-q2*q2)}\end{array}\right.$ Calculate the tangent trigonometric function value tan (Roll) of roll angle Roll, the sine trigonometric function value sin (Pitch) of angle of pitch Pitch, the tangent trigonometric function value tan (Yaw) of crab angle Yaw; Described rapid translating bunch also comprises and prestores the tangent trigonometric function value of each angle with corresponding each angle and the look-up table of sine trigonometric function value; Described rapid translating bunch according to tangent trigonometric function value tan (Roll), sine trigonometric function value sin (Pitch) and tangent trigonometric function value tan (Yaw), in conjunction with look-up table determination roll angle Roll, angle of pitch Pitch and crab angle Yaw; In addition, described IP kernel also comprises quick interconnection; Described quick interconnection for connecting a DMA passage and filtering operation device, and connects attitude fusion calculation bunch and PID arithmetic bunch; Further, described sliding-window filtering device comprises the first FIFO memory, adder unit, addition selector switch and the barrel shift register with 8 storage unit; The data sum that data sum, front 4 storage unit that described adder unit is deposited for front 2 storage unit calculating the first FIFO memory are deposited and the data sum that 8 storage unit are deposited; Described addition selector switch is used for selecting above-mentioned three data sums and exporting barrel shift register to; Further, the output channel of the input selector that a described DMA passage all has 9 input channels with the 2nd DMA passage, input end is connected 9 input channels, the second FIFO memory connecting input selector output terminal, the outlet selector connecting the second FIFO memory and connection outlet selector; Further, described quick interconnection comprises multiple input bus and multiple output bus; The selection being realized data by the break-make controlling each input bus and output bus is inputed or outputed; In addition, IP kernel also comprises the control register group of connection the one DMA passage, fast interconnection, attitude fusion calculation bunch, PID arithmetic bunch; Described control register group is for controlling the selection operation of described input selector, control the break-make of each input bus and output bus, the scale-up factor that setting PI revises bunch and integral coefficient, and scale-up factor, integral coefficient and the differential coefficient of setting PID arithmetic bunch; In addition, described IP kernel also comprises general quick compute cluster, and this general quick compute cluster comprises the bus monitor connecting each output bus and the microprocessor being connected bus monitor; Described bus monitor comprise the Ll data caches register connecting output bus, the secondary data buffer register connecting Ll data caches register, connect Ll data caches register and receive with reference to limit value the first comparing unit, be connected the second comparing unit of Ll data caches register and secondary data buffer register and be connected the first result selector switch of the first comparing unit and the second comparing unit; Described first comparing unit is used for the current data deposited in Ll data caches register to compare with reference to limit value, and exceedes with reference to output abnormality signal during limit value in current data; Described second comparing unit is used for the current data deposited in upper data of the current data deposited in secondary data buffer register and Ll data caches register to compare, the second comparing unit output abnormality signal when the difference of data exceeds certain limit in current data and its; Described first result selector switch is selected above-mentioned two abnormal signals and sends to interrupt event maker; Described bus monitor also comprises the supervision register depositing preliminary data, the second result selector switch connecting output bus and supervision register; Described microprocessor disconnecting event generating and described second result selector switch, for when receiving the look-at-me that interrupt event maker sends, controlling the second result selector switch and exporting and monitor that the preliminary data deposited of register is on result bus; Further, described microprocessor adopts very long instruction word (VLIW) collection framework, and Deep integrating is inner in IP kernel; The general quick compute cluster comprising bus monitor and microprocessor can perform user-defined auxiliary control program or auxiliary watchdog routine.

The present invention first On-Chip peripheral and the second On-Chip peripheral all have the A/D interface, SPI interface, UART interface, the I that are connected aircraft ²the general-purpose interfaces such as C interface, the first On-Chip peripheral is connected acceleration transducer, angular-rate sensor and magnetic field sensor with the second On-Chip peripheral by these interfaces; First On-Chip peripheral and the second On-Chip peripheral also have and a DMA passage or the channel attached DMA Fabric Interface of the 2nd DMA; Fig. 2 shows the structural representation of a DMA passage of the present invention and the 2nd DMA passage, as shown in Figure 2, one DMA passage is selected 9 and is transported in input channel by significance bit and data from multiple peripheral hardware, wherein significance bit is arranged by control register group, input selector selects one group of significance bit and data, when significance bit is effective, triggers the second FIFO memory and read in data; Similarly, for output channel, the marker (whether hurrying) of output channel gives the second FIFO memory through outlet selector, and when being in non-effective by busy position, data export each peripheral hardware by the second FIFO memory to via output channel.

Fig. 3 shows the structural representation of filtering operation device of the present invention, and Fig. 4 shows the structural representation of filtering operation unit of the present invention, and described filtering operation device comprises 9 filtering operation unit; Each filtering operation unit includes at least one in FIR filter, iir digital filter and sliding-window filtering device; As shown in Figure 3 and Figure 4, when the inner integrated three kinds of different hardware filter of filtering operation device, connected by cross interconnected bus between each wave filter.

Fig. 7 shows the present invention and inputs data processing bunch and carry out unitization schematic diagram, and as shown in Figure 7, three number of axle add do involution respectively according to x, y, z and carry out SRT rapid division with the raw data of having done to manage in two-stage vacancy after calculating, and realize the unitization of raw data; Particularly, unitization by following process implementation 3-axis acceleration and three-axle magnetic field data of data processing bunch is inputted: set 3-axis acceleration data as (a _x, a _y, a _z), three-axle magnetic field data are (m _x, m _y, m _z), then the 3-axis acceleration data after unitization are $(\frac{a_x}{\sqrt{{a_x}^2+{a_y}^2+{a_z}^2}},\frac{a_y}{\sqrt{{a_x}^2+{a_y}^2+{a_z}^2}},\frac{a_z}{\sqrt{{a_x}^2+{a_y}^2+{a_z}^2}}),$ Three-axle magnetic field data after unitization are $(\frac{m_x}{\sqrt{{m_x}^2+{m_y}^2+{m_z}^2}},\frac{m_y}{\sqrt{{m_x}^2+{m_y}^2+{m_z}^2}},\frac{m_z}{\sqrt{{m_x}^2+{m_y}^2+{m_z}^2}}).$

Fig. 8 shows the structural representation of PID arithmetic of the present invention bunch, Fig. 9 shows the schematic diagram that PID arithmetic unit of the present invention carries out PID arithmetic, as shown in Figure 8 and Figure 9, PID arithmetic of the present invention bunch each PID arithmetic unit and bunch in interconnection form, wherein PID arithmetic unit adopts incremental digital pid algorithm.

Figure 10 shows the structural representation of the quick interconnection of the present invention, quick interconnection is the link bridge of each ingredient of IP kernel, the parallel connection of equipment choice in sheet can be connected in series together, the unit of each operation independent also can be formed a huge super arithmetic pipelining by connecting from beginning to end successively, input bus and output bus all draw a signal wire to control register group, (control of metal-oxide-semiconductor) is controlled by break-make, one can be selected as the input bus of data fast from all buses, and Output rusults selectivity is outputted on output bus, the parallel/serial flexible configuration between each ingredient can be realized.

Figure 11 shows the structural representation of bus monitor of the present invention, Figure 12 shows the structural representation of microprocessor of the present invention, as shown in figure 11, bus monitor is connected with output buss all on sheet, the data of each ingredient as interconnection quick on sheet between compute cluster can be monitored, by Ll data caches register, secondary data buffer register, first comparing unit, second comparing unit, some special events can be compared, as a certain supervisory signal occurs exceptional value or front and back two secondary data difference greatly, when this takes place, interrupt event maker produces interrupt level, according to interrupt mask, corresponding look-at-me is input to microprocessor, microprocessor, by the selection position of control second result selector switch, makes the data be input on result bus be data on output bus or monitors the preliminary data deposited in register, as shown in figure 12, described microprocessor is based on VLIW (very long instruction word (VLIW) collection) architecture design, its have become length instruction characteristic, in instruction system, contain dormancy instruction, dormancy can be entered when not using, and microprocessor of the present invention is integrated in IP kernel inside, only there is ALU and calculate core and control core, there is no other peripheral hardware, wherein ALU calculates the design (superscale core) that core have employed VLIW, can reduce other unnecessary design like this and make speed reach the most efficient simultaneously.

Intermediate flow compute cluster of the present invention adopts hardware ALU to calculate hypercomplex number intermediate flow q0*q0, q0*q1, q0*q2, q0*q3, q1*q1, q1*q2, q1*q3, q2*q2, q2*q3 and q3*q3, and these intermediate variables are for other compute cluster; Coordinate conversion compute cluster specifically can calculate the hypercomplex number margin of error in inside by cascade ALU, and PI correction bunch utilizes this hypercomplex number margin of error inclined to make PI correction angle speed pickup zero.The setup parameter halfT that quaternion product sub-clustering generates in hypercomplex number comes from user register, is that user can the parameter of self-defining; Initial hypercomplex number (first integral cycle) q0, q1, q2, q3 that described hypercomplex number integration compute cluster generates are (0,0,0,0); Except intermediate flow compute cluster is bunch general by all computings, other compute cluster all meets production-Consumer relationships, and namely data are calculated, and has one group of compute cluster to receive at once.Attitude fusion calculation bunch adopts hardware mode to perform AHRS (attitude heading reference system) algorithm.Look-up table in rapid translating bunch is stored in ROM.

It is too high that the present invention overcomes attitude control system master cpu resources occupation rate in prior art, and the problem that control lag is excessive; The 3-axis acceleration that each sensor obtains, three axis angular rates and three-axle magnetic field data are read in via the first On-Chip peripheral and a DMA passage, on quick interconnection, be then sent to filtering operation device and attitude fusion calculation bunch carry out filtering and attitude and merge and obtain Eulerian angle attitude data, then utilize PID arithmetic bunch to correct accordingly attitude data, export data finally by the 2nd DMA passage and reach the object controlling attitude.Present invention employs hardware mode and corresponding control has been carried out to the attitude of aircraft, the use of special circuit makes the response delay of control system compare single-chip microcomputer or CPU controls significantly to reduce, and the single-chip microcomputer or CPU that were originally in gesture stability is freed from algorithm.The present invention adopt multi input+multiagent cross interconnected+the hardware systems framework of superpipeline+multiple target, wherein multi input refers to the data input that multi-axial sensor can export by the input of IP kernel, cross interconnected and the superpipeline of multiagent refer to inner compute cluster and hardware PID on interconnection by according to composition googol of programming in advance according to circulation flow path, multiple goal refers to that data export according to the path of specifying by DMA under programmed control.

The above; be only the present invention's preferably embodiment; but protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the present invention discloses; be equal to according to technical scheme of the present invention and inventive concept thereof and replace or change, all should be encompassed within protection scope of the present invention.

Claims (8)

1. an aircraft manufacturing technology IP kernel able to programme, is characterized in that, described IP kernel comprises:

First On-Chip peripheral; Described first On-Chip peripheral is for receiving the 3-axis acceleration of aircraft, three axis angular rates and three-axle magnetic field data;

Connect the first On-Chip peripheral and filtering operation device, for 3-axis acceleration, three axis angular rates and three-axle magnetic field data being transferred to a DMA passage of filtering operation device;

For carrying out the filtering operation device of filtering process respectively to 3-axis acceleration, three axis angular rates and three-axle magnetic field data; Described filtering operation device comprises 9 filtering operation unit; A kind of data in each filtering operation unit difference corresponding 3-axis acceleration, three axis angular rates and three-axle magnetic field data; Each filtering operation unit includes at least one in FIR filter, iir digital filter and sliding-window filtering device;

Connect filtering operation device, export the attitude fusion calculation bunch of the Eulerian angle of aircraft for carrying out attitude fusion calculation according to filtered 3-axis acceleration, three axis angular rates and three-axle magnetic field data;

Connect attitude fusion calculation bunch, for carrying out the PID arithmetic bunch of PID correction to the attitude fusion calculation bunch Eulerian angle exported;

Connect PID arithmetic bunch, for revised for PID Eulerian angle to be transferred to the 2nd DMA passage of aircraft by the second On-Chip peripheral;

Second On-Chip peripheral; The Eulerian angle that 2nd DMA channel transfer is come are transferred to aircraft by described second On-Chip peripheral;

Described attitude fusion calculation bunch comprises:

Connect filtering operation device, for the 3-axis acceleration after input filter, three axis angular rates and three-axle magnetic field data, and unitization input data processing bunch is carried out to 3-axis acceleration wherein and three-axle magnetic field data;

Connect quaternion product sub-clustering, for the hypercomplex number q0 exported for quaternion product sub-clustering, q1, q2, q3, obtains the intermediate flow compute cluster of hypercomplex number intermediate flow q0*q0, q0*q1, q0*q2, q0*q3, q1*q1, q1*q2, q1*q3, q2*q2, q2*q3, q3*q3;

Connect input data processing bunch and intermediate flow compute cluster, for being converted to earth axes to the input data processing bunch three-axle magnetic field data exported by body axis system, and according to input data processing bunch 3-axis acceleration exported, three axis angular rates and three-axle magnetic field data, the hypercomplex number intermediate flow in conjunction with the output of intermediate flow compute cluster draws the coordinate conversion compute cluster of the hypercomplex number margin of error; Described coordinate conversion compute cluster utilizes formula

$\left\{\begin{array}{c}{b}_x=\sqrt{[\left({h_x}^2\right)+\left({h_y}^2\right)]}\\ b_y=0\\ b_z=h_z\end{array}\right.$ Calculate the three-axle magnetic field data (b being converted to earth axes by body axis system _x, b _y, b _z), wherein $\left\{\begin{array}{c}{h}_x=2*m_x*(0.5-q2*q2-q3*q3)+2*m_y*(q1*q2-q0*q3)+2*m_z*(q1*q3+q0*q2)\\ h_y=2*m_x*(q1*q2+q0*q3)+2*m_y*(0.5-q1*q1-q3*q3)+2*m_z*(q2*q3-q0*q1)\\ h_z=2*m_x*(q1*q3-q0*q2)+2*m_y*(q2*q3+q0*q1)+2*m_z*(0.5-q1*q1-q2*q2)\end{array}\right.$ , (m _x, m _y, m _z) be the input data processing bunch 3-axis acceleration data exported; Described coordinate conversion compute cluster utilizes formula $\left\{\begin{array}{c}{e}_x=(a_y*v_z-a_z*v_y)+(m_y*w_z-m_z*w_y)\\ e_y=(a_z*v_x-a_x*v_z)+(m_z*w_x-m_x*w_z)\\ e_z=(a_x*v_y-a_y*v_x)+(m_x*w_y-m_y*w_x)\end{array}\right.$ Calculate the hypercomplex number margin of error (e _x, e _y, e _z), wherein (a _x, a _y, a _z) export for input data processing bunch 3-axis acceleration data, $\left\{\begin{array}{c}{v}_x=2*(q1*q3-q0*q2)\\ v_y=2*(q0*q1+q2*q3)\\ v_z=q0*q0-q1*q1-q2*q2-q3*q3\end{array}\right.,$ $\left\{\begin{array}{c}{w}_x=2*b_x*(0.5-q2*q2-q3*q3)+2*b_z*(q1*q3-q0*q2)\\ w_y=2*b_x*(q1*q2-q0*q3)+2*b_z*(q0*q1+q2*q3)\\ w_z=2*b_x*(q0*q2+q1*q3)+2*b_z*(0.5-q1*q1-q2*q2)\end{array}\right.;$

Connection coordinate conversion compute cluster, performs the PI correction bunch of proportional integral correction for utilizing the hypercomplex number margin of error to three axis angular rate data; Described PI correction bunch utilizes formula $\left\{\begin{array}{c}{u}_x=g_x+K_p*e_x+{e_x}^{\′}\mathrm{Int}\\ u_y=g_y+K_p*e_y+{e_y}^{\′}\mathrm{Int}\\ u_z=g_z+K_p*e_z+{e_z}^{\′}\mathrm{Int}\end{array}\right.$ Obtain the revised three axis angular rate data (u of PI _x, u _y, u _z), wherein (g _x, g _y, g _z) be input data processing bunch three axis angular rate data, the K that export _pfor the scale-up factor, (e of setting _x, e _y, e _z) for the hypercomplex number margin of error, $\left\{\begin{array}{c}{e_x}^{\′}\mathrm{Int}=e_x\mathrm{Int}+e_x*K_i\\ {e_y}^{\′}\mathrm{Int}=e_y\mathrm{Int}+e_y*K_i\\ {e_z}^{\′}\mathrm{Int}=e_z\mathrm{Int}+e_z*K_i\end{array}\right.,$ (e _xint, e _yint, e _zint) be to (the e in a upper integration period _x, e _y, e _z) respective integration, K _pfor the integral coefficient of setting;

Connect PI correction bunch, for generating the hypercomplex number integration compute cluster of current integration cycle hypercomplex number according to the hypercomplex number of revised three axis angular rate data and a upper integration period; Described hypercomplex number integration compute cluster utilizes formula $\left\{\begin{array}{c}{q0}^{\′}={q0}_b+(-{q1}_b*u_x-{q2}_b*u_y-{q3}_b*u_z)*\mathrm{halfT}\\ {q1}^{\′}={q1}_b+({q0}_b*u_x+{q2}_b*u_z-{q3}_b*u_y)*\mathrm{halfT}\\ {q2}^{\′}={q2}_b+({q0}_b*u_y-{q1}_b*u_z+{q3}_b*u_x)*\mathrm{halfT}\\ {q3}^{\′}={q3}_b+({q0}_b*u_z-{q1}_b*u_y-{q2}_b*u_x)*\mathrm{halfT}\end{array}\right.$ Draw the hypercomplex number q0 ' in current integration cycle, q1 ', q2 ', q3 ', wherein q0 _b, q1 _b, q2 _b, q3 _bfor the hypercomplex number, (u of a upper integration period _x, u _y, u _z) for the revised three axis angular rate data of PI, halfT be setup parameter; At generation current integration cycle hypercomplex number q0 ', q1 ', q2 ', the rear described hypercomplex number integration compute cluster of q3 ' also for q0 ', q1 ', q2 ', q3 ' carry out unitization and obtain q0, q1, q2, q3 export to intermediate flow compute cluster and rapid translating bunch;

Connect quaternion product sub-clustering, for the q0 exported according to quaternion product sub-clustering, q1, q2, q3 obtain the rapid translating bunch of Eulerian angle; Described rapid translating bunch utilizes formula $\left\{\begin{array}{c}\tan \left(\mathrm{Poll}\right)=\frac{(q1*q2+q3*q0)}{(q3*q3-q0*q0-q1*q1+q2*q2)}\\ \sin \left(\mathrm{Pitch}\right)=-2*(q0*q2-q3*q1)\\ \tan \left(\mathrm{Yaw}\right)=\frac{2*(q0*q1+q3*q2)}{(q3*q3+q0*q0-q1*q1-q2*q2)}\end{array}\right.$ Calculate the tangent trigonometric function value tan (Roll) of roll angle Roll, the sine trigonometric function value sin (Pitch) of angle of pitch Pitch, the tangent trigonometric function value tan (Yaw) of crab angle Yaw; Described rapid translating bunch also comprises and prestores the tangent trigonometric function value of each angle with corresponding each angle and the look-up table of sine trigonometric function value; Described rapid translating bunch according to tangent trigonometric function value tan (Roll), sine trigonometric function value sin (Pitch) and tangent trigonometric function value tan (Yaw), in conjunction with look-up table determination roll angle Roll, angle of pitch Pitch and crab angle Yaw.

2. one according to claim 1 aircraft manufacturing technology IP kernel able to programme, is characterized in that described IP kernel also comprises quick interconnection; Described quick interconnection for connecting a DMA passage and filtering operation device, and connects attitude fusion calculation bunch and PID arithmetic bunch.

3. one according to claim 1 aircraft manufacturing technology IP kernel able to programme, is characterized in that described sliding-window filtering device comprises the first FIFO memory, adder unit, addition selector switch and the barrel shift register with 8 storage unit; The data sum that data sum, front 4 storage unit that described adder unit is deposited for front 2 storage unit calculating the first FIFO memory are deposited and the data sum that 8 storage unit are deposited; Described addition selector switch is used for selecting above-mentioned three data sums and exporting barrel shift register to.

4. one according to claim 3 aircraft manufacturing technology IP kernel able to programme, is characterized in that the output channel of the input selector that a described DMA passage all has 9 input channels with the 2nd DMA passage, input end is connected 9 input channels, the second FIFO memory connecting input selector output terminal, the outlet selector connecting the second FIFO memory and connection outlet selector.

5. one according to claim 4 aircraft manufacturing technology IP kernel able to programme, is characterized in that described quick interconnection comprises multiple input bus and multiple output bus; The selection being realized data by the break-make controlling each input bus and output bus is inputed or outputed.

6. one according to claim 5 aircraft manufacturing technology IP kernel able to programme, is characterized in that IP kernel also comprises the control register group of connection the one DMA passage, fast interconnection, attitude fusion calculation bunch, PID arithmetic bunch; Described control register group is for controlling the selection operation of described input selector, control the break-make of each input bus and output bus, the scale-up factor that setting PI revises bunch and integral coefficient, and scale-up factor, integral coefficient and the differential coefficient of setting PID arithmetic bunch.

7. one according to claim 5 aircraft manufacturing technology IP kernel able to programme, it is characterized in that described IP kernel also comprises general quick compute cluster, this general quick compute cluster comprises the bus monitor connecting each output bus and the microprocessor being connected bus monitor;

Described bus monitor comprise the Ll data caches register connecting output bus, the secondary data buffer register connecting Ll data caches register, connect Ll data caches register and receive with reference to limit value the first comparing unit, be connected the second comparing unit of Ll data caches register and secondary data buffer register and be connected the first result selector switch of the first comparing unit and the second comparing unit; Described first comparing unit is used for the current data deposited in Ll data caches register to compare with reference to limit value, and exceedes with reference to output abnormality signal during limit value in current data; Described second comparing unit is used for the current data deposited in upper data of the current data deposited in secondary data buffer register and Ll data caches register to compare, the second comparing unit output abnormality signal when the difference of data exceeds certain limit in current data and its; Described first result selector switch is selected above-mentioned two abnormal signals and sends to interrupt event maker; Described bus monitor also comprises the supervision register depositing preliminary data, the second result selector switch connecting output bus and supervision register; Described microprocessor disconnecting event generating and described second result selector switch, for when receiving the look-at-me that interrupt event maker sends, controlling the second result selector switch and exporting and monitor that the preliminary data deposited of register is on result bus.

8. one according to claim 7 aircraft manufacturing technology IP kernel able to programme, it is characterized in that described microprocessor adopts very long instruction word (VLIW) collection framework, and Deep integrating is inner in IP kernel.