CN104880190A - Intelligent chip for accelerating inertial navigation attitude fusion - Google Patents
Intelligent chip for accelerating inertial navigation attitude fusion Download PDFInfo
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- CN104880190A CN104880190A CN201510294532.5A CN201510294532A CN104880190A CN 104880190 A CN104880190 A CN 104880190A CN 201510294532 A CN201510294532 A CN 201510294532A CN 104880190 A CN104880190 A CN 104880190A
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- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/10—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration
- G01C21/12—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning
- G01C21/16—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning by integrating acceleration or speed, i.e. inertial navigation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/20—Instruments for performing navigational calculations
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Abstract
The invention discloses an intelligent chip for accelerating inertial navigation attitude fusion. The intelligent chip solidifies attitude calculation into hardware acceleration logic and combines software calculation with hardware acceleration. The intelligent chip comprises an SPI (serial peripheral interface) communication interface module (1), a quaternion initializing module (2), a high-speed storage module (3), a quaternion updating module (4) and a quaternion feedback and output module (5) from input to output according to the sequence of data flow so as to increase inertial navigation system attitude fusion speed and improve inertial navigation system attitude fusion precision.
Description
Technical field
The present invention relates to technical field of inertial, particularly relate to a kind of intelligent chip merging acceleration for inertial navigation attitude.
Background technology
The solving technique of course attitude reference system (Attitude Heading Reference System), is called for short attitude integration technology, is the most important and basic technology in field of navigating now, especially for inertial navigation field.The highest demand of this technology be exactly the inertia device that carried by carrier can be real-time high precision complete the attitude orientation of carrier under terrestrial coordinate system.Towards this direction, the realization based on the attitude integration technology of MEMS inertia device has 3 kinds of modes so far: based on MCU(Micro Control Unit) the inertial navigation attitude integration technology of embedded system; Based on MCU and DSP(Digital Signal Processor) the inertial navigation attitude integration technology of cascade; Based on the inertial navigation attitude integration technology of special IC (Application Specific Integrated Circuit) chip fixed logic.
In the attitude fusion application of the overwhelming majority, the work of the correction of error the most time-consuming effort often, evaluated error when these errors include the parasitic error between the Acquisition Error of inertia device itself, inertia vector and calculate, these computings eliminating error often occupy the computational resource more than 80 percent in whole attitude calculating process, therefore, in the attitude fusion application of reality, precision and speed need to find an equilibrium point that can compromise.
Kalman filtering method mathematically has unique advantage for the calculating of error concealment, the Kalman Filter Technology of MCU and the DSP cascade of France scholar Jose-Fermi Guerrero-Castellanos structure serves good error concealment effect on attitude merges, but renewal speed is comparatively slow, does not reach completely real-time requirement.This is mainly because of the complicacy that it calculates, in fact, Kalman filtering method is in the attitude fusion application of reality, due to the mutation of its characteristic parameter, often be difficult to grasp, and Kalman filtering method is often along with extremely huge calculated amount, need to pay high assessing the cost, usable range is narrow.
British scholar Sebastian O.H. Madgwick propose employing gradient-pole value-based algorithm be then another comparatively general attitude merge ERROR ALGORITHM, it is a kind of error function matrix being to construct inertia vector system, the gradient of error matrix is utilized constantly to approach, the method for last convergence error.This method is proved to be and can improves speed greatly in low frequency system, at Madgwick based in the attitude integration technology of MCU, the method has showed the feature being better than Kalman filtering.But, the solving technique of this MCU platform based on single CPU, can show obvious inferior position, moreover in frequency applications, limited equally due to computing power, the embedded inertial navigation attitude integration technology based on MCU does not still reach desirable requirement in precision and speed.
Comprehensively above-mentioned two kinds of attitude integration technologies, namely pure software system and software and DSP is adopted to accelerate cascade system, more good and bad on renewal speed, precision and cost: pure software system accuracy is general, response speed is passable at low frequency, distortion under high frequency error, and cost is lower; Software and DSP cascade system precision is pretty good, response speed is undesirable, cost costly.On the whole, two kinds of methods respectively have quality, but all not ideal enough, and basic reason is still that the computing power of two kinds of technology is limited.
Starting point of the present invention is the advantage drawing above-mentioned two kinds of attitude integration technologies, and avoids their inferior position.Specifically, the present invention algorithmically inherits the advantage of the easily expansion flexibly of gradient extreme value integration technology, simultaneously, in order to make up computing power, take the integrated circuit (IC) chip scheme of design specialized, the hardware logic designing special solidification resolves attitude emerging system, avoids the solution process that next rule sequential instructions collection of software way takes time and effort.For special integrated circuit (IC) chip, due to reaction time of hardware gate circuit logic (10-12 second) and the reaction time of microprocessor instruction set system (10-6 second) in the unit of Microsecond grade in the unit of picosecond, speed and calculated capacity have nearly millionfold capability improving, the raising of speed also means the quickening of renewal frequency simultaneously, so, the convergence of error can become rapider, and the precision of system also can obtain proportional raising.Emphasis of the present invention makes up defect in computing power with regard to being to utilize the advantage of dedicated IC chip, play the flexible advantage accurately of original gradient extreme value blending algorithm simultaneously, these two kinds time and space design upper the interlocking being organized in execution attitude fusion application are allowed to exist, work in perfect harmony, reach the most efficient attitude algorithm effect.
Therefore, provide a kind of and merge the intelligent chip accelerated for inertial navigation system attitude, to promote speed and the precision of the fusion of inertial navigation system attitude.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of intelligent chip merging acceleration for inertial navigation system attitude, to promote speed and the precision of the fusion of inertial navigation system attitude.
A kind of intelligent chip merging acceleration for inertial navigation attitude, the gradient-pole value-based algorithm of attitude algorithm is solidified into hardware-accelerated logic by described intelligent chip, resolved by software and combine with hardware-accelerated, described intelligent chip comprises from being input to output successively according to the order of data stream: SPI communication interface modules, hypercomplex number initialization module, high speed registration module, hypercomplex number update module and quaternion feedback and output module;
The data that described SPI communication interface modules is used for described intelligent chip and outside spi bus transmits, described hypercomplex number initialization module be used for buffer memory from MEMS inertia device via SPI communication interface modules input carrier three-dimensional inertia Vector Groups data and according to the initial value of described three-dimensional inertia Vector Groups data calculating hypercomplex number; Described high speed registration module is used for the three-dimensional inertia vector after to the normalization of hypercomplex number initialization module input and initialized quaternionic vector carries out high-speed cache; Described hypercomplex number update module is used for carrying out attitude fusion to the inertia vector sum initialization hypercomplex number inputted from high speed registration module, upgrades the solution of hypercomplex number and the solution of hypercomplex number is sent to quaternion feedback and output module; Described quaternion feedback and output module are used for the renewal quaternionic vector data from described hypercomplex number update module input are refilled to dress and export.
Preferably, be solidified into software described in hardware-accelerated logical and described in resolve and to exist in same system and the attitude algorithm that combined.
Preferably, the front-end interface of described SPI communication interface modules is connected with spi bus slot, and external signal is by the form turnover chip of SPI serial data packet; The SPI serial port of described intelligent chip is for receiving the inertia Vector Groups data gathered with the MEMS sensor of the SPI slot of High Speed Serial transmission mode on embedded microprocessor unit; The back end interface of described SPI communication interface modules is connected with hypercomplex number initialization module.
Preferably, described SPI communication interface modules comprises SPI communication core module and SPI application module, and wherein SPI communicates core module for performing Physical layer, the data link layer of exchanges data; SPI application module is for managing described hypercomplex number initialization module, described quaternion feedback and output module and outside host computer or the exchanges data between outside spi bus, inertia vector location and MEMS inertia device.
Preferably, described three-dimensional inertia vector comprises carrier acceleration, angular velocity and magnetic field intensity.
Preferably, described hypercomplex number initialization module comprises FIFO stack module, normalization engine modules, Eulerian angle initialization module and Eulerian angle and turns hypercomplex number module, described FIFO stack module is used for the three-dimensional inertia Vector Groups data that obtain from SPI communication interface modules of buffer memory and is transferred to described normalization engine modules and described Eulerian angle initialization module, described three-dimensional inertia Vector Groups data comprise carrier acceleration, angular velocity and magnetic field intensity, and the three-dimensional inertia vector data being transferred to described Eulerian angle initialization module comprises carrier acceleration and magnetic field intensity information;
Described normalization engine modules, for the three-dimensional inertia Vector Groups obtained from FIFO stack module being carried out the normalization computing of floating point vector, and is transferred to described Eulerian angle and turns hypercomplex number module and described high speed registration module by result; Be transferred to data that described Eulerian angle turn hypercomplex number module comprise normalization after vector acceleration, the data being transferred to described high speed registration module comprise vector acceleration, angular velocity vector and the magnetic field intensity vector after normalization;
Described Eulerian angle initialization module is for the synthesis of the Eulerian angle initial value of carrier, reference frame project is carried out by the vector acceleration that accepts to come from described FIFO stack module and magnetic field intensity vector, obtain the Eulerian angle initial value rotated, and initialized Eulerian angle array is passed to Eulerian angle turn hypercomplex number module, this Eulerian angle array comprises course angle, the angle of pitch and roll angle;
Described Eulerian angle turn hypercomplex number module for this Eulerian angle array being converted to corresponding quaternionic vector, and initialized quaternionic vector is transferred to high speed registration module.
Preferably, described normalization engine modules comprises acceleration normalization tube bank, angular velocity normalization tube bank and magnetic field intensity normalization tube bank, and they process three-dimensional floating add velocity vector normalization computing, three-dimensional floating-point angular velocity vector normalization computing and three-dimensional floating-point magnetic field intensity vector normalization computing respectively.
Preferably, described high speed registration module comprises 4 independently cache memories, and they work alone with the same area side by side, wherein:
Acceleration buffer for store the input of hypercomplex number initialization module normalization after vector acceleration, and send to hypercomplex number update module according to demand;
Angular velocity buffer for store the input of hypercomplex number initialization module normalization after angular velocity vector, and send to hypercomplex number update module according to demand;
Magnetic field intensity buffer for store the input of hypercomplex number initialization module normalization after magnetic field intensity vector, and send to hypercomplex number update module according to demand;
Hypercomplex number buffer for store the input of hypercomplex number initialization module initialization after quaternionic vector, and send to hypercomplex number update module according to demand.
Preferably, described hypercomplex number update module comprises renewal state machine module, angular velocity differential module, Jacobean matrix array module and Gradient Descent blending algorithm module,
Described renewal state machine module is used for angular velocity differential module described in control & monitor, order of operation between described Jacobean matrix array module and described Gradient Descent blending algorithm module and exchanges data;
Described angular velocity differential module is used for differentiating to the angular velocity vector of described high speed registration module transmission and initialization quaternionic vector, and result is passed to described Gradient Descent blending algorithm module under the control of described renewal state machine module;
Described Jacobean matrix array module is combined the computing solving Jacobi equation for the vector acceleration to described high speed registration module transmission, angular velocity vector, magnetic field intensity vector sum initialization quaternionic vector, and result is passed to described Gradient Descent blending algorithm module under the control of described renewal state machine module;
Described Gradient Descent blending algorithm module carries out fusion computing according to the gradient-pole value-based algorithm of multi-C vector function to described angular velocity differential module and described Jacobean matrix array module result out, obtain upgrading hypercomplex number, and under described renewal state machine module controls, result is passed to quaternion feedback and output module.
Preferably, described quaternion feedback and output module comprise feedback states machine, load module and output module again, wherein:
Feedback states machine module is for controlling operation and the exchanges data of loading module and output module again;
The quaternionic vector data loaded again after the renewal that described hypercomplex number update module inputs by module in charge write to the hypercomplex number buffer in high speed registration module again, and cover original initialization quaternionic vector data and produce the quaternion algebra certificate upgraded;
Output module is responsible for the quaternion algebra of described renewal according to exporting outside host computer to.
Technical scheme of the present invention has following beneficial effect:
1. the intelligent chip merging acceleration for inertial navigation attitude provided by the invention, compared with the instruction set operating speed utilizing the attitude integration technology of MCU or DSP of popular, chip gate leve computing velocity has the lifting of 103 times of levels.Meanwhile, the raising of renewal speed accelerates the speed of error convergence, and precision has the lifting of at least 102 times.On the other hand, the structure that the mounting hardware logic that the present invention adopts in the process of data stream is accelerated, the response frequency postponed with real-time gate leve psec (10-12 second) level surmounts the operating speed that MCU or DSP instruction set microsecond (10-6 second) postpones.
2. the intelligent chip merging acceleration for inertial navigation attitude provided by the invention, compared with general attitude integration technology, have employed modified gradient extreme value blending algorithm more flexibly, not only speed of convergence and precision satisfactory, and algorithm is made appropriate reconstruction, to coordinate the accelerating structure of hardware logic, the advantage of the advantage flexibly of algorithm and the speed of hardware is combined, makes the effect of algorithm itself perform to maximum efficiency.
Accompanying drawing explanation
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is that inertial navigation system attitude of the present invention merges the structural representation accelerating intelligent chip;
Fig. 2 is the structural representation of hypercomplex number initialization module in Fig. 1;
Fig. 3 is the structural representation of hypercomplex number update module in Fig. 1;
Fig. 4 is the structural representation of quaternion feedback and output module in Fig. 1.
Embodiment
In order to have a clear understanding of technical scheme of the present invention, its detailed structure will be proposed in the following description.Obviously, the concrete execution of the embodiment of the present invention also not enough specific details being limited to those skilled in the art and haveing the knack of.The preferred embodiments of the present invention are described in detail as follows, and except these embodiments described in detail, can also have other embodiments.
Inertial navigation system attitude merges the special IC intelligent chip that the structure accelerating intelligent chip is a high-speed digital video camera, be integrated with follow-on gradient-pole value-based algorithm and solidify with the form of hardware logic, be specifically designed to and accelerate and course wherein and attitude algorithm part, according to the three-dimensional inertial sensor be connected on carrier system, real-time resolving represents Eulerian angle required for carrier course and attitude and hypercomplex number.
With reference to described in Fig. 1, figure and be the overall architecture of the present invention's realization.MCU system in Fig. 1 and inertial navigation system attitude merge intelligent chip and are directly connected via chip pin, by the spi bus of the MCU bus marco end as association system, this is the tandem type project organization that a kind of MCU system and inertial navigation system attitude merge that intelligent chip shares same system board.The three-dimensional Inertial Sensor System of outside MEMS is then direct-connected with MCU system by the communication pin of SPI, and under the control of MCU system, the inertia Vector Groups data that inertial sensor gathers are transported on inertial navigation system attitude fusion intelligent chip endlessly.
In figure, the gradient-pole value-based algorithm of attitude algorithm is solidified into hardware-accelerated logic by intelligent chip, software is resolved and combines with hardware-accelerated, describedly be solidified into software described in hardware-accelerated logical and and resolve and to exist in same system and the attitude algorithm that combined, each inertial navigation system attitude merges intelligent chip and is made up of 5 modules, and the order according to data stream comprises successively from being input to output: SPI communication interface modules 1, hypercomplex number initialization module 2, high speed registration module 3, hypercomplex number update module 4, quaternion feedback and output module 5.
Wherein, SPI communication interface modules 1 transmits for the data realizing this attitude algorithm chip and outside spi bus, and front-end interface is connected with spi bus slot, and external signal is by the form turnover chip of SPI serial data packet; The inertia Vector Groups data that MEMS sensor gathers are transferred into the serial port of the SPI of this attitude algorithm speed-up chip with the SPI slot of High Speed Serial transmission mode on embedded microprocessor unit; The back end interface of SPI communication interface modules is connected with hypercomplex number initialization module 2.
Described SPI communication interface modules 1 comprises SPI communication core module and SPI application module, and wherein SPI communicates core module for performing Physical layer, the data link layer of exchanges data; SPI application module is for managing described hypercomplex number initialization module 2, described quaternion feedback and output module 5 and outside host computer or the exchanges data between outside spi bus, inertia vector location and MEMS inertia device.
Wherein, described hypercomplex number initialization module 2 carries out buffer memory and calculates the initial value of hypercomplex number from MEMS inertia device according to described three-dimensional inertia Vector Groups data via the three-dimensional inertia Vector Groups data of SPI communication interface modules 1 input carrier, and the inertia Vector Groups data that MEMS sensor gathers at least comprise: carrier three-dimensional angular velocity Vector Groups, carrier three-dimensional acceleration Vector Groups and carrier three-dimensional magnetic field intensity vector group.
Hypercomplex number initialization module 2 is responsible for these inertia vectors collected of process and is calculated initial quaternary numerical value, divide according to functional structure, hypercomplex number initialization module 2 comprises: FIFO stack module 21, normalization engine modules 22, Eulerian angle initialization module 23 and Eulerian angle turn hypercomplex number module 24.
With reference to accompanying drawing 2, we explain the structure of hypercomplex number initialization module 2 in detail:
First, angular velocity, acceleration and magnetic field strength date can be carried out buffer memory by the asynchronous FIFO of a high speed, object is the cross clock domain problem (cross clock domain: because clock rate differs to the metastable state caused and data exception problem in digit chip) between treatment S PI communication interface modules and hypercomplex number initialization module, another one is exactly the spilling in order to prevent data, and this module is called FIFO stack module 21;
Can be sent to normalization engine modules 22 after inertia vector data is by FIFO shaping, comprises angular velocity acceleration and magnetic field intensity, wherein part vector data is also sent to Eulerian angle initialization module 23, comprises acceleration and magnetic field intensity;
When inertia vector data comes normalization engine, can be arranged in three parallel bundle-shaped pipeline organizations, angular velocity normalizing bundle, acceleration normalizing bundle and magnetic field intensity normalizing bundle respectively, independent parallel carries out mathematical vectorial normalization computing, after normalization completes, whole data can send hypercomplex number initialization module 2, are sent to high speed registration module 3, and the Eulerian angle that partial data can be sent to hypercomplex number initialization module 2 inside simultaneously turn hypercomplex number module 24;
As mentioned before, acceleration information after FIFO arranges and magnetic field strength date are sent to Eulerian angle initialization module 23 simultaneously, here, according to the angled relationships of relatively-stationary gravitational acceleration vector and absolute force vector and the carrier vector acceleration that measures and magnetic field intensity vector, tentatively resolve the Eulerian angle of carrier, and the data obtained is transmitted to Eulerian angle and turns hypercomplex number module 24;
Eulerian angle turn hypercomplex number module 24 and are responsible for converting initialized Eulerian angle to initialized hypercomplex number, here the synthesis of hypercomplex number initial vector is except the initialized Eulerian angle of needs, the accekeration after normalization is also needed to participate in, finally, the initialization hypercomplex number obtained exports next module high speed registration module 3 to.
With reference to accompanying drawing 1, high speed registration module 3 be actually by 4 independently high-speed memory form, be responsible for buffer memory angular velocity data, acceleration information, magnetic field strength date and quaternionic vector data respectively, whole high speed registration module serves the effect of forming a connecting link, be responsible for shaping and the flow process of data stream, and the data of these buffer memorys issued next modular unit hypercomplex number update module 4 as required.Wherein, the input end of quaternionic vector buffer its in fact by two sources, one is the hypercomplex number data vector coming from initialization hypercomplex number module 2, another is from the quaternion algebra certificate of carrying with quaternion feedback module 5, this buffer is except writing quaternion algebra certificate by hypercomplex number initialization module when system initialization, other update time, then continuous write by feedback module covered, and object constantly updates hypercomplex number to reach the object of convergence error.
Hypercomplex number update module 4 is for carrying out attitude fusion to the inertia vector sum initialization hypercomplex number inputted from high speed registration module 3, upgrade the solution of hypercomplex number and the solution of hypercomplex number is sent to quaternion feedback and output module 5, according to its function, we are divided into the basic structure of two-stage four pieces.
With reference to accompanying drawing 3, as described in Figure, hypercomplex number update module 4 comprises renewal state machine module 41, angular velocity differential module 42, Jacobean matrix array module 43 and Gradient Descent blending algorithm module 44;
Upgrade state machine module 41 for the order of operation between control & monitor angular velocity differential module 42, Jacobean matrix array module 43 and Gradient Descent blending algorithm module 44 and exchanges data;
Result for differentiating to the angular velocity vector transmitted from high speed registration module 3 and initialization quaternionic vector, and is passed to Gradient Descent blending algorithm module 44 by angular velocity module of differentials 42 pieces under renewal state machine module 41 controls;
Result for combining to the vector acceleration transmitted from high speed registration module 3, angular velocity vector, magnetic field intensity vector sum initialization quaternionic vector the computing solving Jacobi equation, and is passed to Gradient Descent blending algorithm module 44 by Jacobean matrix array module 43 under renewal state machine module 41 controls;
Gradient Descent blending algorithm module 44 carries out fusion computing according to the gradient-pole value-based algorithm of multi-C vector function to from angular velocity differential module 42 and Jacobean matrix array module 43 result out, obtain the hypercomplex number upgraded, and control 41 times in renewal state machine module result is passed to quaternion feedback and output module 5.
After the solution of the hypercomplex number upgraded is sent to quaternion feedback and output module 5, quaternion feedback and output module 5 are for refilling dress and exporting to the renewal quaternionic vector data inputted from described hypercomplex number update module 4, specifically, quaternion feedback and output module 5 are responsible for the quaternionic vector data of renewal to load to the hypercomplex number buffer in high speed registration module 3 again, the data of this quaternionic vector are sent to outside host computer by the control of SPI communication interface modules 1 simultaneously.Therefore, it has two missions: one is the host computer exported to outside chip, declares that this has resolved; On the other hand, this solution also will be filled into rapidly in hypercomplex number buffer, as the starting point upgrading computing next time, can only do like this, and the error of the continuous convergence solution of renewal ability of hypercomplex number obtains the solution of high-precision attitude of carrier fusion.
Accordingly, with reference to accompanying drawing 4, quaternion feedback and output module 5 are implemented like this and organize:
Quaternion feedback and output module 5 load module and output module three modules form by feedback states machine, again;
Feedback states machine module is for controlling operation and the exchanges data of loading module and output module again;
The quaternionic vector data loaded again after the renewal that hypercomplex number update module 4 inputs by module in charge write to the hypercomplex number buffer in high speed registration module 3 again, and cover original initialization quaternionic vector data;
Output module is responsible for by the quaternion algebra of this renewal according to exporting outside host computer to, and complete that whole inertial navigation attitude merges resolve task.
The intelligent chip merging acceleration for inertial navigation attitude provided by the invention, compared with the instruction set operating speed utilizing the attitude integration technology of MCU or DSP of popular, chip gate leve computing velocity has the lifting of 103 times of levels.Meanwhile, the raising of renewal speed accelerates the speed of error convergence, and precision has the lifting of at least 102 times.On the other hand, the structure that the mounting hardware logic that the present invention adopts in the process of data stream is accelerated, the response frequency postponed with real-time gate leve psec (10-12 second) level surmounts the operating speed that MCU or DSP instruction set microsecond (10-6 second) postpones; Compared with general attitude integration technology, have employed modified gradient extreme value blending algorithm more flexibly, not only speed of convergence and precision satisfactory, and algorithm is made appropriate reconstruction, to coordinate the accelerating structure of hardware logic, the advantage of the advantage flexibly of algorithm and the speed of hardware is combined, makes the effect of algorithm itself perform to maximum efficiency.
Finally should be noted that: above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit; although with reference to above-described embodiment to invention has been detailed description; those of ordinary skill in the field still can modify to the specific embodiment of the present invention or equivalent replacement; these do not depart from any amendment of spirit and scope of the invention or equivalent replacement, are all applying within the claims awaited the reply.
Claims (10)
1. one kind merges the intelligent chip accelerated for inertial navigation attitude, it is characterized in that, the gradient-pole value-based algorithm of attitude algorithm is solidified into hardware-accelerated logic by described intelligent chip, resolved by software and combine with hardware-accelerated, described intelligent chip comprises from being input to output successively according to the order of data stream: SPI communication interface modules (1), hypercomplex number initialization module (2), high speed registration module (3), hypercomplex number update module (4) and quaternion feedback and output module (5);
Described SPI communication interface modules (1) is transmitted for the data of described intelligent chip and outside spi bus, and described hypercomplex number initialization module (2) according to described three-dimensional inertia Vector Groups data calculates the initial value of hypercomplex number from MEMS inertia device via the three-dimensional inertia Vector Groups data of SPI communication interface modules (1) input carrier for buffer memory; Described high speed registration module (3) carries out high-speed cache for the three-dimensional inertia vector after the normalization that inputs hypercomplex number initialization module (2) and initialized quaternionic vector; Described hypercomplex number update module (4), for carrying out attitude fusion to the inertia vector sum initialization hypercomplex number inputted from high speed registration module (3), upgrades the solution of hypercomplex number and the solution of hypercomplex number is sent to quaternion feedback and output module (5); Described quaternion feedback and output module (5) are for refilling dress and exporting to the renewal quaternionic vector data inputted from described hypercomplex number update module (4).
2. according to claim 1ly merge the intelligent chip accelerated for inertial navigation attitude, it is characterized in that, described in be solidified into software described in hardware-accelerated logical and and resolve and to exist in same system and the attitude algorithm that combined.
3. the intelligent chip merging acceleration for inertial navigation attitude according to claim 1, it is characterized in that, the front-end interface of described SPI communication interface modules (1) is connected with spi bus slot, and external signal is by the form turnover chip of SPI serial data packet; The SPI serial port of described intelligent chip is for receiving the inertia Vector Groups data gathered with the MEMS sensor of the SPI slot of High Speed Serial transmission mode on embedded microprocessor unit; The back end interface of described SPI communication interface modules (1) is connected with hypercomplex number initialization module (2).
4. the intelligent chip merging acceleration for inertial navigation attitude according to claim 3, it is characterized in that, described SPI communication interface modules (1) comprises SPI communication core module and SPI application module, and wherein SPI communicates core module for performing Physical layer, the data link layer of exchanges data; SPI application module is for managing described hypercomplex number initialization module (2), described quaternion feedback and output module (5) and outside host computer or the exchanges data between outside spi bus, inertia vector location and MEMS inertia device.
5. the intelligent chip merging acceleration for inertial navigation attitude according to claim 1, it is characterized in that, described three-dimensional inertia vector comprises carrier acceleration, angular velocity and magnetic field intensity.
6. the intelligent chip merging acceleration for inertial navigation attitude according to claim 5, it is characterized in that, described hypercomplex number initialization module (2) comprises FIFO stack module (21), normalization engine modules (22), Eulerian angle initialization module (23) and Eulerian angle turn hypercomplex number module (24), the three-dimensional inertia Vector Groups data that described FIFO stack module (21) obtains for buffer memory from SPI communication interface modules (1) are also transferred to described normalization engine modules (22) and described Eulerian angle initialization module (23), described three-dimensional inertia Vector Groups data comprise carrier acceleration, angular velocity and magnetic field intensity, the three-dimensional inertia vector data being transferred to described Eulerian angle initialization module (23) comprises carrier acceleration and magnetic field intensity information,
Described normalization engine modules (22), for the three-dimensional inertia Vector Groups obtained from FIFO stack module (21) being carried out the normalization computing of floating point vector, and result is transferred to described Eulerian angle and turns hypercomplex number module (24) and described high speed registration module (3); Be transferred to data that described Eulerian angle turn hypercomplex number module (24) comprise normalization after vector acceleration, the data being transferred to described high speed registration module (3) comprise vector acceleration, angular velocity vector and the magnetic field intensity vector after normalization;
Described Eulerian angle initialization module (23) is for the synthesis of the Eulerian angle initial value of carrier, reference frame project is carried out by the vector acceleration of coming from described FIFO stack module (21) acceptance and magnetic field intensity vector, obtain the Eulerian angle initial value rotated, and initialized Eulerian angle array is passed to Eulerian angle turn hypercomplex number module, this Eulerian angle array comprises course angle, the angle of pitch and roll angle;
Described Eulerian angle turn hypercomplex number module (24) for this Eulerian angle array being converted to corresponding quaternionic vector, and initialized quaternionic vector is transferred to high speed registration module (3).
7. the intelligent chip merging acceleration for inertial navigation attitude according to claim 6, it is characterized in that, described normalization engine modules (22) comprises acceleration normalization tube bank, angular velocity normalization tube bank and magnetic field intensity normalization tube bank, and they process three-dimensional floating add velocity vector normalization computing, three-dimensional floating-point angular velocity vector normalization computing and three-dimensional floating-point magnetic field intensity vector normalization computing respectively.
8. the intelligent chip merging acceleration for inertial navigation attitude according to claim 1, it is characterized in that, described high speed registration module (3) comprises 4 independently cache memories, and they work alone with the same area side by side, wherein:
Acceleration buffer for the vector acceleration after the normalization that stores hypercomplex number initialization module (2) and input, and sends to hypercomplex number update module (4) according to demand;
Angular velocity buffer for the angular velocity vector after the normalization that stores hypercomplex number initialization module (2) and input, and sends to hypercomplex number update module (4) according to demand;
Magnetic field intensity buffer for the magnetic field intensity vector after the normalization that stores hypercomplex number initialization module (2) and input, and sends to hypercomplex number update module (4) according to demand;
Hypercomplex number buffer for the quaternionic vector after the initialization that stores hypercomplex number initialization module (2) and input, and sends to hypercomplex number update module (4) according to demand.
9. the intelligent chip merging acceleration for inertial navigation attitude according to claim 1, it is characterized in that, described hypercomplex number update module (4) comprises renewal state machine module (41), angular velocity differential module (42), Jacobean matrix array module (43) and Gradient Descent blending algorithm module (44)
Described renewal state machine module (41) is for angular velocity differential module (42) described in control & monitor, order of operation between described Jacobean matrix array module (43) and described Gradient Descent blending algorithm module (44) and exchanges data;
Described angular velocity differential module (42) is differentiated for the angular velocity vector that transmits described high speed registration module (3) and initialization quaternionic vector, and under the control of described renewal state machine module (41), result is passed to described Gradient Descent blending algorithm module (44);
Described Jacobean matrix array module (43) is combined the computing solving Jacobi equation for vector acceleration, angular velocity vector, the magnetic field intensity vector sum initialization quaternionic vector transmitted described high speed registration module (3), and under the control of described renewal state machine module (41), result is passed to described Gradient Descent blending algorithm module (44);
Described Gradient Descent blending algorithm module (44) carries out fusion computing according to the gradient-pole value-based algorithm of multi-C vector function to described angular velocity differential module (42) and described Jacobean matrix array module (43) result out, obtain upgrading hypercomplex number, and under described renewal state machine module (41) controls, result is passed to quaternion feedback and output module (5).
10. the intelligent chip merging acceleration for inertial navigation attitude according to claim 1, it is characterized in that, described quaternion feedback and output module (5) comprise feedback states machine, load module and output module again, wherein:
Feedback states machine module is for controlling operation and the exchanges data of loading module and output module again;
The quaternionic vector data loaded again after the renewal that described hypercomplex number update module (4) inputs by module in charge write to the hypercomplex number buffer in high speed registration module (3) again, and cover original initialization quaternionic vector data and produce the quaternion algebra certificate upgraded;
Output module is responsible for the quaternion algebra of described renewal according to exporting outside host computer to.
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