CN104407617B - Aircraft manufacturing technology IP kernel able to programme - Google Patents

Abstract

The invention discloses a kind of aircraft manufacturing technology IP kernel able to programme, described IP kernel includes: the first On-Chip peripheral；First DMA channel；For 3-axis acceleration, three axis angular rates and three-axle magnetic field data being filtered respectively the filtering operation device processed；Connect filtering operation device, for carrying out the attitude fusion calculation bunch of the Eulerian angles of attitude fusion calculation output aircraft according to filtered 3-axis acceleration, three axis angular rates and three-axle magnetic field data；Connect the PID arithmetic bunch of attitude fusion calculation bunch；Second DMA channel；Second On-Chip peripheral；The Eulerian angles that second DMA channel is transmitted by described second On-Chip peripheral are transmitted to aircraft；Present invention employs hardware mode and the attitude of aircraft has been carried out corresponding control, the use of special circuit makes the response delay of control system compare single-chip microcomputer or CPU controls to be greatly reduced, and the single-chip microcomputer or CPU that were originally in gesture stability is freed from algorithm.

Description

Aircraft manufacturing technology IP kernel able to programme

Technical field

The present invention relates to aircraft manufacturing technology field, a kind of aircraft manufacturing technology IP kernel able to programme.

Background technology

Airborne vehicle according to track flight and spacecraft when track runs, in order to complete undertaken task, it is necessary to tool There is certain attitude, during such as four rotor hovering flights, need the state keeping with datum level attitude parallel.For aircraft Speech, when it is in state of flight, attitude control system needs to obtain each axial deflection angle of aircraft, then by filter Ripple algorithm, by each sensing data Filtering Processing, obtains the stable data of each sensor, and attitude to be used merges Algorithm carries out drift correction and fusion to each sensor, and integration goes out quaternary number and the Eulerian angles of aircraft, calculates finally by PID Aircraft propulsion is revised by method；Aforementioned each sensor generally comprises acceleration transducer, angular-rate sensor and magnetic Field sensor.

Attitude control system of the prior art, typically uses the frame of universal cpu+general A/D sampling+general D/A output Structure, this architecture design is simple, and universal cpu is identical with existing programming model.Adopt and mean universal cpu needs in this way Moment carries out the acquisition of A/D sampling, the filtering of sensing data, the fusion of attitude, the calculating of pid control parameter and D/A's Output, for being usually embedded formula processor, this operand is the hugest, and processor often cannot be reallocated in it Among its application so that some designs and framework have to use plural universal cpu, and one of them is used for attitude control System, another is used for realizing airborne application；Simultaneously for gesture stability process, its sensing data has obvious Producer-disappear The data characteristic of the person of expense, existing universal cpu is for controlling intensive applications, it is impossible to accomplish these data streams of parallel processing, because of And the treatment effeciency of whole system is substantially reduced；Attitude control system of the prior art, some employing universal cpu+ The design of hardware PID, this design is only capable of the computing pressure alleviating PID part, for improving whole attitude control system Act on little.

Summary of the invention

The present invention is directed to the proposition of problem above, and develop a kind of aircraft manufacturing technology IP kernel able to programme.

The technological means of the present invention is as follows:

A kind of aircraft manufacturing technology IP kernel able to programme, described IP kernel includes:

First On-Chip peripheral；Described first On-Chip peripheral for receive the 3-axis acceleration of aircraft, three axis angular rates and Three-axle magnetic field data；

Connect the first On-Chip peripheral and filtering operation device, for by 3-axis acceleration, three axis angular rates and three-axle magnetic field number The first DMA channel according to transmission to filtering operation device；

For 3-axis acceleration, three axis angular rates and three-axle magnetic field data being filtered respectively the filtering operation processed Device；Described filtering operation device includes 9 filtering operation unit；Each filtering operation unit the most corresponding 3-axis acceleration, three axles A kind of data in angular velocity and three-axle magnetic field data；Each filtering operation unit all includes FIR filter, iir digital filter With at least one in sliding-window filtering device；

Connect filtering operation device, for entering according to filtered 3-axis acceleration, three axis angular rates and three-axle magnetic field data The attitude fusion calculation bunch of the Eulerian angles of row attitude fusion calculation output aircraft；

Connect attitude fusion calculation bunch, for the Eulerian angles of attitude fusion calculation bunch output being carried out the PID fortune of PID correction Calculation bunch；

Connect PID arithmetic bunch, for by revised for PID Eulerian angles by the second On-Chip peripheral transmission to the of aircraft Two DMA channel；

Second On-Chip peripheral；The Eulerian angles transmission that second DMA channel is transmitted by described second On-Chip peripheral is to flight Device；

Described attitude fusion calculation bunch includes:

Connection filtering operation device, 3-axis acceleration, three axis angular rates and the three-axle magnetic field data after input filter, and 3-axis acceleration therein and three-axle magnetic field data are carried out unitization input data process bunch；

Connect quaternion product sub-clustering, for quaternary number q0, q1, q2, q3 for quaternion product sub-clustering output, obtain quaternary The intermediate flow of number intermediate flow q0*q0, q0*q1, q0*q2, q0*q3, q1*q1, q1*q2, q1*q3, q2*q2, q2*q3 and q3*q3 Calculating bunch；

Connect input data process bunch and intermediate flow calculating bunch, for three axle magnetic to input data process bunch output Field data is converted to earth axes by body axis system, and processes three axles acceleration of bunch output according to input data Degree, three axis angular rates and three-axle magnetic field data, calculate a bunch quaternary number intermediate flow for output in conjunction with intermediate flow and draw quaternary The Coordinate Conversion calculating bunch of the number margin of error；The calculating bunch of described Coordinate Conversion utilizes formula $\left\{\begin{array}{c}{b}_x=\sqrt{[\left({h_x}^2\right)+\left({h_y}^2\right)]}\\ b_y=0\\ b_z=h_z\\ \end{array}\right.$ Calculate the three-axle magnetic field data (b being converted to earth axes by body axis system_x,b_y,b_z), wherein $\left\{\begin{array}{c}{h}_x=2*m_x*(0.5-q2*q2-q3*q3)+2*m_y*(q1*q2-q0*q3)+2*m_z*(q1*q3+q0*q2)\\ h_y=2*m_x*(q1*q2+q0*q3)+2*m_y*(0.5-q1*q1-q3*q3)+2*m_z*(q2*q3-q0*q1)\\ h_z=2*m_x*(q1*q3-q0*q2)+2*m_y*(q2*q3+q0*q1)+2*m_z*(0.5-q1*q1-q2*q2)\end{array}\right.$ 、 (m_x,m_y,m_z) process bunch 3-axis acceleration data for output for input data；The calculating bunch of described Coordinate Conversion utilizes formula $\left\{\begin{array}{c}{e}_x=(a_y*v_z-a_z*v_y)+(m_y*w_z-m_z*w_y)\\ e_y=(a_z*v_x-a_x*v_z)+(m_z*w_x-m_x*w_z)\\ e_z=(a_x*v_y-a_y*v_x)+(m_x*w_y-m_y*w_x)\end{array}\right.$ Calculate the quaternary number margin of error (e_x,e_y,e_z), wherein (a_x,a_y, a_z) for input data process bunch output 3-axis acceleration data, $\left\{\begin{array}{c}{v}_x=2*(q1*q3-q0*q2)\\ v_y=2*(q0*q1+q2*q3)\\ v_z=q0*q0-q1*q1-q2*q2-q3*q3\end{array}\right.,$ $\left\{\begin{array}{c}{w}_x=2*b_x*(0.5-q2*q2-q3*q3)+2*b_z*(q1*q3-q0*q2)\\ w_y=2*b_x*(q1*q2-q0*q3)+2*b_z*(q0*q1+q2*q3)\\ w_z=2*b_x*(q0*q2+q1*q3)+2*b_z*(0.5-q1*q1-q2*q2)\end{array}\right.;$

Connection coordinate conversion Calculation bunch, is used for utilizing the quaternary number margin of error that three axis angular rate data are performed proportional integral and repaiies Positive PI correction bunch；Described PI correction bunch utilizes formula $\left\{\begin{array}{c}{u}_x=g_x+K_p*e_x+{e_x}^{\′}\mathrm{Int}\\ u_y=g_y+K_p*e_y+{e_y}^{\′}\mathrm{Int}\\ u_z=g_z+K_p*e_z+{e_z}^{\′}\mathrm{Int}\end{array}\right.$ Obtain revised three axles of PI Angular velocity data (u_x,u_y,u_z), wherein (g_x,g_y,g_z) input three axis angular rate data of data process bunch output, a K_pFor setting Proportionality coefficient, (e_x,e_y,e_z) be the quaternary number margin of error, $\left\{\begin{array}{c}{e_x}^{\′}\mathrm{Int}=e_x\mathrm{Int}+e_x*K_i\\ {e_y}^{\′}\mathrm{Int}=e_y\mathrm{Int}+e_y*K_i\\ {e_z}^{\′}\mathrm{Int}=e_z\mathrm{Int}+e_z*K_i\end{array}\right.,$ (e_xInt,e_yInt,e_zInt) For to (the e in a upper integration period_x,e_y,e_z) respective integration, K_pFor the integral coefficient set；

Connect PI correction bunch, generate for the quaternary number according to revised three axis angular rate data and a upper integration period The quaternion product of current integration cycle quaternary number divides calculating bunch；Described quaternion product divides calculating bunch to utilize formula $\left\{\begin{array}{c}{q0}^{\′}={q0}_b+(-{q1}_b*u_x-{q2}_b*u_y-{q3}_b*u_z)*\mathrm{halfT}\\ {q1}^{\′}={q1}_b+({q0}_b*u_x+{q2}_b*u_z-{q3}_b*u_y)*\mathrm{halfT}\\ {q2}^{\′}={q2}_b+({q0}_b*u_y-{q1}_b*u_z+{q3}_b*u_x)*\mathrm{halfT}\\ {q3}^{\′}={q3}_b+({q0}_b*u_z-{q1}_b*u_y-{q2}_b*u_x)*\mathrm{halfT}\end{array}\right.$ Draw the quaternary number q0 ' in current integration cycle, Q1 ', q2 ', q3 ', wherein q0_b,q1_b,q2_b,q3_bQuaternary number, (u for a upper integration period_x,u_y,u_z) it is PI revised three Axis angular rate data, halfT are setup parameter；Generating current integration cycle quaternary number q0 ', q1 ', q2 ', q3 ' rear described four Unit's number integral and calculating bunch is additionally operable to carry out unitization to q0 ', q1 ', q2 ', q3 ' and obtain q0, and q1, q2, q3 export to intermediate flow Calculating bunch and rapid translating bunch；

Connecting quaternion product sub-clustering, for the q0 according to quaternion product sub-clustering output, q1, q2, q3 obtain the fast of Eulerian angles Speed conversion bunch；Described rapid translating bunch utilizes formula $\left\{\begin{array}{c}\tan \left(\mathrm{Roll}\right)=\frac{(q1*q2+q3*q0)}{(q3*q3-q0*q0-q1*q1+q2*q2)}\\ \sin \left(\mathrm{Pitch}\right)=-2*(q0*q2-q3*q1)\\ \tan \left(\mathrm{Yaw}\right)=\frac{2*(q0*q1+q3*q2)}{(q3*q3+q0*q0-q1*q1-q2*q2)}\end{array}\right.$ Calculate Go out tangent trigonometric function value tan (Roll) of roll angle Roll, sine trigonometric function value sin (Pitch) of angle of pitch Pitch, Tangent trigonometric function value tan (Yaw) of yaw angle Yaw；It is each with corresponding that described rapid translating bunch also includes prestoring each angle The tangent trigonometric function value of angle and the look-up table of sine trigonometric function value；Described rapid translating bunch is according to tangent trigonometric function value Tan (Roll), sine trigonometric function value sin (Pitch) and tangent trigonometric function value tan (Yaw), determine rolling in conjunction with look-up table Angle Roll, angle of pitch Pitch and yaw angle Yaw；

It addition, described IP kernel also includes quick interconnection；Described quick interconnection for connect the first DMA channel and Filtering operation device, and connect attitude fusion calculation bunch and PID arithmetic bunch；

Further, described sliding-window filtering device includes having the first FIFO memory of 8 memory element, adder Unit, addition selector and barrel shift depositor；Described adder unit is before calculating the first FIFO memory Data sum that the data sum that 2 memory element are deposited, front 4 memory element are deposited and the number that 8 memory element are deposited According to sum；Described addition selector is for selecting above three data sum and exporting to barrel shift depositor；

Further, described first DMA channel and the second DMA channel are respectively provided with 9 input channels, input connects 9 The input selector of input channel, connect the second FIFO memory of input selector outfan, connect the second FIFO memory Outlet selector and connect outlet selector output channel；

Further, described quick interconnection includes multiple input bus and multiple output bus；Each defeated by controlling The break-make entering bus and output bus realizes selection input or the output of data；

It addition, IP kernel also includes connecting the first DMA channel, quick interconnection, attitude fusion calculation bunch, PID arithmetic bunch Control Parasites Fauna；Described control Parasites Fauna, for controlling the selection operation of described input selector, controls each input total Line and the break-make of output bus, set proportionality coefficient and the integral coefficient of PI correction bunch, and set the ratio system of PID arithmetic bunch Number, integral coefficient and differential coefficient；

It addition, described IP kernel also includes general quick calculating bunch, this general quick calculating bunch includes connecting each output bus Bus monitor and connect bus monitor microprocessor；

Described bus monitor includes connecting the Ll data caches depositor of output bus, connection Ll data caches is posted The secondary data buffer register of storage, connection Ll data caches depositor and the first comparing unit of reception reference limit value, Connect Ll data caches depositor and the second comparing unit of secondary data buffer register and connect the first comparing unit The first result selector with the second comparing unit；Described first comparing unit is for depositing in Ll data caches depositor Current data with compare with reference to limit value, and the output abnormality signal when current data exceedes with reference to limit value；Described second Comparing unit is for depositing upper data of the current data deposited in secondary data buffer register with Ll data caches The current data deposited in device compares, and when current data exceeds certain limit with the difference of data on it, second compares Unit output abnormality signal；Above-mentioned two abnormal signal is selected and is sent to interrupt event by described first result selector Maker；Described bus monitor also includes depositing the supervision depositor of preliminary data, connecting output bus and monitor depositor The second result selector；Described microprocessor disconnecting event generating and described second result selector, for when connecing When receiving the interrupt signal that interrupt event maker sends, control second result selector output monitor depositor deposit standby Data are on result bus；

Further, described microprocessor uses VLIW collection framework, and Deep integrating is inside IP kernel.

Owing to have employed technique scheme, the aircraft manufacturing technology IP kernel able to programme that the present invention provides, have employed hard Part mode has carried out corresponding control to the attitude of aircraft, and the use of special circuit makes the response delay of control system compare Single-chip microcomputer or CPU control to be greatly reduced, and the single-chip microcomputer or CPU that were originally in gesture stability are freed from algorithm.

Accompanying drawing explanation

Fig. 1 is the structural representation of IP kernel of the present invention；

Fig. 2 is the first DMA channel of the present invention and the structural representation of the second DMA channel；

Fig. 3 is the structural representation of filtering operation device of the present invention；

Fig. 4 is the structural representation of filtering operation unit of the present invention；

Fig. 5 is the structural representation of sliding-window filtering device of the present invention；

Fig. 6 is the structural representation of attitude fusion calculation bunch of the present invention；

Fig. 7 is that the present invention inputs data and processes and bunch carry out unitization schematic diagram；

Fig. 8 is the structural representation of PID arithmetic bunch of the present invention；

Fig. 9 is the schematic diagram that PID arithmetic unit of the present invention carries out PID arithmetic；

Figure 10 is the structural representation of the quick interconnection of the present invention；

Figure 11 is the structural representation of bus monitor of the present invention

Figure 12 is the structural representation of microprocessor of the present invention.

Detailed description of the invention

As shown in Figures 1 to 12, a kind of aircraft manufacturing technology IP kernel able to programme, described IP kernel includes: the first On-Chip peripheral； Described first On-Chip peripheral is for receiving the 3-axis acceleration of aircraft, three axis angular rates and three-axle magnetic field data；Connect first Upper peripheral hardware and filtering operation device, for transmitting 3-axis acceleration, three axis angular rates and three-axle magnetic field data to filtering operation device First DMA channel；For 3-axis acceleration, three axis angular rates and three-axle magnetic field data being filtered respectively the filtering operation processed Device；Described filtering operation device includes 9 filtering operation unit；Each filtering operation unit the most corresponding 3-axis acceleration, three shaft angles A kind of data in speed and three-axle magnetic field data；Each filtering operation unit all includes FIR filter, iir digital filter and cunning At least one in dynamic window filter；Connect filtering operation device, for according to filtered 3-axis acceleration, three axis angular rates and Three-axle magnetic field data carry out the attitude fusion calculation bunch of the Eulerian angles of attitude fusion calculation output aircraft；Connect attitude fusion calculation Bunch, for the Eulerian angles of attitude fusion calculation bunch output being carried out the PID arithmetic bunch of PID correction；Connecting PID arithmetic bunch, being used for will The revised Eulerian angles of PID are by the second DMA channel of the second On-Chip peripheral transmission to aircraft；Second On-Chip peripheral；Described The Eulerian angles that second DMA channel is transmitted by two On-Chip peripherals are transmitted to aircraft；Described attitude fusion calculation bunch includes: even Connect filtering operation device, 3-axis acceleration, three axis angular rates and the three-axle magnetic field data after input filter, and to therein three Axle acceleration and three-axle magnetic field data carry out unitization input data process bunch；Connect quaternion product sub-clustering, for for four Quaternary number q0, q1, q2, the q3 of unit's scalar product sub-clustering output, obtains quaternary number intermediate flow q0*q0, q0*q1, q0*q2, q0*q3, q1* The intermediate flow calculating bunch of q1, q1*q2, q1*q3, q2*q2, q2*q3 and q3*q3；Connect input data process bunch and middle flowmeter Calculation bunch, is converted to earth axes for input data are processed bunch three-axle magnetic field data for output by body axis system, and Bunch 3-axis acceleration, three axis angular rates and three-axle magnetic field data for output are processed, in conjunction with intermediate flow calculating bunch according to input data The quaternary number intermediate flow of output draws the Coordinate Conversion calculating bunch of the quaternary number margin of error；The calculating bunch of described Coordinate Conversion utilizes formula $\left\{\begin{array}{c}{b}_x=\sqrt{[\left({h_x}^2\right)+\left({h_y}^2\right)]}\\ b_y=0\\ b_z=h_z\\ \end{array}\right.$ Calculate the three-axle magnetic field data (b being converted to earth axes by body axis system_x,b_y,b_z), Wherein $\left\{\begin{array}{c}{h}_x=2*m_x*(0.5-q2*q2-q3*q3)+2*m_y*(q1*q2-q0*q3)+2*m_z*(q1*q3+q0*q2)\\ h_y=2*m_x*(q1*q2+q0*q3)+2*m_y*(0.5-q1*q1-q3*q3)+2*m_z*(q2*q3-q0*q1)\\ h_z=2*m_x*(q1*q3-q0*q2)+2*m_y*(q2*q3+q0*q1)+2*m_z*(0.5-q1*q1-q2*q2)\end{array}\right.$ 、 (m_x,m_y,m_z) process bunch 3-axis acceleration data for output for input data；The calculating bunch of described Coordinate Conversion utilizes formula $\left\{\begin{array}{c}{e}_x=(a_y*v_z-a_z*v_y)+(m_y*w_z-m_z*w_y)\\ e_y=(a_z*v_x-a_x*v_z)+(m_z*w_x-m_x*w_z)\\ e_z=(a_x*v_y-a_y*v_x)+(m_x*w_y-m_y*w_x)\end{array}\right.$ Calculate the quaternary number margin of error (e_x,e_y,e_z), wherein (a_x, a_y,a_z) for input data process bunch output 3-axis acceleration data, $\left\{\begin{array}{c}{v}_x=2*(q1*q3-q0*q2)\\ v_y=2*(q0*q1+q2*q3)\\ v_z=q0*q0-q1*q1-q2*q2-q3*q3\end{array}\right.,$ $\left\{\begin{array}{c}{w}_x=2*b_x*(0.5-q2*q2-q3*q3)+2*b_z*(q1*q3-q0*q2)\\ w_y=2*b_x*(q1*q2-q0*q3)+2*b_z*(q0*q1+q2*q3)\\ w_z=2*b_x*(q0*q2+q1*q3)+2*b_z*(0.5-q1*q1-q2*q2)\end{array}\right.;$ Connection coordinate conversion Calculation bunch, is used for Utilize the quaternary number margin of error that three axis angular rate data perform the PI correction bunch of proportional integral correction；Described PI correction bunch utilizes formula $\left\{\begin{array}{c}{u}_x=g_x+K_p*e_x+{e_x}^{\′}\mathrm{Int}\\ u_y=g_y+K_p*e_y+{e_y}^{\′}\mathrm{Int}\\ u_z=g_z+K_p*e_z+{e_z}^{\′}\mathrm{Int}\end{array}\right.$ Obtain the revised three axis angular rate data (u of PI_x,u_y,u_z), wherein (g_x,g_y,g_z) input Data process bunch three axis angular rate data of output, a K_pFor the proportionality coefficient set, (e_x,e_y,e_z) be the quaternary number margin of error, $\left\{\begin{array}{c}{e_x}^{\′}\mathrm{Int}=e_x\mathrm{Int}+e_x*K_i\\ {e_y}^{\′}\mathrm{Int}=e_y\mathrm{Int}+e_y*K_i\\ {e_z}^{\′}\mathrm{Int}=e_z\mathrm{Int}+e_z*K_i\end{array}\right.,$ (e_xInt,e_yInt,e_zInt) it is to (the e in a upper integration period_x,e_y,e_z) each long-pending Point, K_pFor the integral coefficient set；Connected PI correction bunch, for according to revised three axis angular rate data and a upper integration week The quaternary number of phase generates the quaternion product of current integration cycle quaternary number and divides calculating bunch；Described quaternion product divides calculating bunch to utilize formula $\left\{\begin{array}{c}{q0}^{\′}={q0}_b+(-{q1}_b*u_x-{q2}_b*u_y-{q3}_b*u_z)*\mathrm{halfT}\\ {q1}^{\′}={q1}_b+({q0}_b*u_x+{q2}_b*u_z-{q3}_b*u_y)*\mathrm{halfT}\\ {q2}^{\′}={q2}_b+({q0}_b*u_y-{q1}_b*u_z+{q3}_b*u_x)*\mathrm{halfT}\\ {q3}^{\′}={q3}_b+({q0}_b*u_z-{q1}_b*u_y-{q2}_b*u_x)*\mathrm{halfT}\end{array}\right.$ Draw quaternary number q0 ', the q1 ' in current integration cycle, Q2 ', q3 ', wherein q0_b,q1_b,q2_b,q3_bQuaternary number, (u for a upper integration period_x,u_y,u_z) it is revised three shaft angles of PI Speed data, halfT are setup parameter；Generating the rear described quaternary number of current integration cycle quaternary number q0 ', q1 ', q2 ', q3 ' Integral and calculating bunch is additionally operable to carry out unitization to q0 ', q1 ', q2 ', q3 ' and obtain q0, and q1, q2, q3 export and calculate to intermediate flow Bunch and rapid translating bunch；Connecting quaternion product sub-clustering, for the q0 according to quaternion product sub-clustering output, q1, q2, q3 obtain Euler The rapid translating bunch at angle；Described rapid translating bunch utilizes formula $\left\{\begin{array}{c}\tan \left(\mathrm{Roll}\right)=\frac{(q1*q2+q3*q0)}{(q3*q3-q0*q0-q1*q1+q2*q2)}\\ \sin \left(\mathrm{Pitch}\right)=-2*(q0*q2-q3*q1)\\ \tan \left(\mathrm{Yaw}\right)=\frac{2*(q0*q1+q3*q2)}{(q3*q3+q0*q0-q1*q1-q2*q2)}\end{array}\right.$ Calculate tangent trigonometric function value tan (Roll) of roll angle Roll, sine trigonometric function value sin of angle of pitch Pitch (Pitch), tangent trigonometric function value tan (Yaw) of yaw angle Yaw；Described rapid translating bunch also includes prestoring each angle Tangent trigonometric function value and the look-up table of sine trigonometric function value with corresponding each angle；Described rapid translating bunch is according to tangent three Angle function value tan (Roll), sine trigonometric function value sin (Pitch) and tangent trigonometric function value tan (Yaw), in conjunction with look-up table Determine roll angle Roll, angle of pitch Pitch and yaw angle Yaw；It addition, described IP kernel also includes quick interconnection；Described soon Speed interconnection is for connecting the first DMA channel and filtering operation device, and connects attitude fusion calculation bunch and PID arithmetic bunch； Further, described sliding-window filtering device includes having the first FIFO memory of 8 memory element, adder unit, add Method selector and barrel shift depositor；Described adder unit is for calculating front 2 storages of the first FIFO memory Data sum that the data sum that unit is deposited, front 4 memory element are deposited and the data sum that 8 memory element are deposited； Described addition selector is for selecting above three data sum and exporting to barrel shift depositor；Further, Described first DMA channel and the second DMA channel are respectively provided with 9 input channels, the input of input 9 input channels of connection selects Device, connect input selector outfan the second FIFO memory, connect the outlet selector of the second FIFO memory, Yi Jilian Connect the output channel of outlet selector；Further, described quick interconnection includes that multiple input bus and multiple output are total Line；The selection being realized data by the break-make controlling each input bus and output bus is inputted or output；It addition, IP kernel also includes Connect the control Parasites Fauna of the first DMA channel, quick interconnection, attitude fusion calculation bunch, PID arithmetic bunch；Described control Parasites Fauna, for controlling the selection operation of described input selector, controls the break-make of each input bus and output bus, sets The proportionality coefficient of PI correction bunch and integral coefficient, and set the proportionality coefficient of PID arithmetic bunch, integral coefficient and differential coefficient； It addition, described IP kernel also includes general quick calculating bunch, this general quick calculating bunch includes the bus prison connecting each output bus Visual organ and the microprocessor of connection bus monitor；Described bus monitor includes that the Ll data caches connecting output bus is posted Storage, the secondary data buffer register of connection Ll data caches depositor, connection Ll data caches depositor and reception The second of first comparing unit of reference limit value, connection Ll data caches depositor and secondary data buffer register is the most single Unit and connect the first comparing unit and the first result selector of the second comparing unit；Described first comparing unit is used for will The current data deposited in Ll data caches depositor compares with reference to limit value, and exceedes with reference to limit value in current data Time output abnormality signal；Described second comparing unit is used for upper the one of the current data will deposited in secondary data buffer register The current data deposited in data and Ll data caches depositor compares, current data with it on the difference of data Beyond the second comparing unit output abnormality signal during certain limit；Above-mentioned two abnormal signal is entered by described first result selector Row selects and is sent to interrupt event maker；Described bus monitor also includes depositing the supervision depositor of preliminary data, company Connect output bus and monitor the second result selector of depositor；Described microprocessor disconnecting event generating and described Two result selectores, for when receiving the interrupt signal that interrupt event maker sends, control the second result selector defeated Go out to monitor that preliminary data that depositor deposits is to result bus；Further, described microprocessor uses VLIW collection frame Structure, and Deep integrating is inside IP kernel；General quick calculating bunch including bus monitor and microprocessor can perform user Self-defining assist control program or auxiliary monitoring programme.

The present invention the first On-Chip peripheral and the second On-Chip peripheral be respectively provided with connection the A/D interface of aircraft, SPI interface, UART interface, I²The general-purpose interfaces such as C interface, the first On-Chip peripheral and the second On-Chip peripheral can connect acceleration by these interfaces Sensor, angular-rate sensor and magnetic field sensor；First On-Chip peripheral and the second On-Chip peripheral also have and the first DMA channel Or second DMA channel connect DMA Fabric Interface；Fig. 2 shows the first DMA channel of the present invention and the second DMA channel Structural representation, leads to as in figure 2 it is shown, the first DMA channel selects 9 significance bit and data are transported to input from multiple peripheral hardware On road, wherein significance bit is arranged by controlling Parasites Fauna, and input selector selects one group of significance bit and data, when significance bit has During effect, trigger the second FIFO memory and read in data；Similarly, for output channel, the marker of output channel (whether Busy) give the second FIFO memory through outlet selector, when busy bit is in non-effective, data by the second FIFO memory via Output channel exports to each peripheral hardware.

Fig. 3 shows the structural representation of filtering operation device of the present invention, and Fig. 4 shows the knot of filtering operation unit of the present invention Structure schematic diagram, described filtering operation device includes 9 filtering operation unit；Each filtering operation unit all includes FIR filter, IIR At least one in digital filter and sliding-window filtering device；As shown in Figure 3 and Figure 4, it is internally integrated three when filtering operation device When planting different hardware filter, connected by cross interconnected bus between each wave filter.

Fig. 7 shows that the present invention inputs data process bunch and carries out unitization schematic diagram, as it is shown in fig. 7, three number of axle are according to x, Y, z make to carry out SRT rapid division with the initial data having made two-stage vacancy reason from multiply-add after calculating respectively, it is achieved original Data unitization；Specifically, input data process and bunch realize 3-axis acceleration and three-axle magnetic field data by following process Unitization: to set 3-axis acceleration data as (a_x,a_y,a_z), three-axle magnetic field data are (m_x,m_y,m_z), the most unitization after three axles Acceleration information is $(\frac{a_x}{\sqrt{{a_x}^2+{a_y}^2+{a_z}^2}},\frac{a_y}{\sqrt{{a_x}^2+{a_y}^2+{a_z}^2}},\frac{a_z}{\sqrt{{a_x}^2+{a_y}^2+{a_z}^2}}),$ After unitization Three-axle magnetic field data be $(\frac{m_x}{\sqrt{{m_x}^2+{m_y}^2+{m_z}^2}},\frac{m_y}{\sqrt{{m_x}^2+{m_y}^2+{m_z}^2}},\frac{m_z}{\sqrt{{m_x}^2+{m_y}^2+{m_z}^2}}).$

Fig. 8 shows the structural representation of PID arithmetic bunch of the present invention, and Fig. 9 shows that PID arithmetic unit of the present invention is carried out The schematic diagram of PID arithmetic, as shown in Figure 8 and Figure 9, PID arithmetic bunch of the present invention each PID arithmetic unit and bunch in interconnection structure Becoming, wherein PID arithmetic unit uses incremental digital pid algorithm.

Figure 10 shows that the structural representation of the quick interconnection of the present invention, quick interconnection are each ingredients of IP kernel Link bridge, it is possible to the parallel connection of equipment choice in sheet being connected in series together, the unit of each operation independent also can be by successively Head and the tail connect and form a huge super arithmetic pipelining, and input bus and output bus all draw a holding wire to controlling Parasites Fauna, by break-make control (control of metal-oxide-semiconductor), can quickly select an input as data from all buses Bus, and output result selectivity is exported on output bus, the parallel/serial spirit between each ingredient can be realized Live and configure.

Figure 11 shows the structural representation of bus monitor of the present invention, and Figure 12 shows microprocessor of the present invention Structural representation, as shown in figure 11, bus monitor output bus all with on sheet is connected, it is possible to monitor each ingredient Such as the data of quick interconnection on sheet between calculating bunch, by Ll data caches depositor, secondary data buffer register, First comparing unit, the second comparing unit, can compare some specific events, as exceptional value or front occurs in a certain supervision signal Greatly, when this takes place, interrupt event maker produces interrupt level to rear two secondary data differences, according to interrupt mask, Corresponding interrupt signal is input to microprocessor；Microprocessor is by controlling the selection position of the second result selector so that input Data on result bus are the data on output bus or monitor the preliminary data deposited in depositor；As shown in figure 12, Described microprocessor is based on VLIW (VLIW collection) architecture design, and it has the characteristic of change length instruction, in instruction system Contain dormancy instruction, dormancy can be entered not using when, and microprocessor of the present invention is integrated in inside IP kernel, Only having ALU and calculate core and control core, do not have other peripheral hardware, wherein ALU calculates core and have employed the design of VLIW and (exceed standard Amount core), so can reduce other unnecessary design and make speed reach the most efficient simultaneously.

Intermediate flow of the present invention calculates a bunch employing hardware ALU and calculates quaternary number intermediate flow q0*q0, q0*q1, q0*q2, q0* Q3, q1*q1, q1*q2, q1*q3, q2*q2, q2*q3 and q3*q3, these intermediate variables are for other calculating bunch；Coordinate Conversion Calculating bunch specifically can calculate the quaternary number margin of error in inside by cascade ALU, and PI correction bunch utilizes this quaternary number margin of error Make PI correction angle velocity sensor zero inclined.The setup parameter halfT that quaternion product sub-clustering generates in quaternary number comes from user Depositor, is that user can be with the parameter of self-defining；Described quaternion product divides the initial quaternary number (first integral that calculating bunch generates Cycle) q0, q1, q2, q3 are (0,0,0,0)；Between a good appetite suddenly appearing in a serious disease, stream calculation bunch is general by all computings bunch, and other calculating bunch all meets life Product-Consumer relationships, i.e. one data are computed, and have one group to calculate a bunch reception at once.Attitude fusion calculation bunch uses hard Part mode performs AHRS (attitude heading reference system) algorithm.Look-up table in rapid translating bunch is stored in ROM.

The present invention overcomes attitude control system master cpu resources occupation rate in prior art too high, and it is excessive to control delay Problem；3-axis acceleration, three axis angular rates and the three-axle magnetic field data that each sensor obtains via the first On-Chip peripheral and First DMA channel reads in, and is then sent to filtering operation device on quick interconnection and attitude fusion calculation bunch is filtered Merge with attitude and obtain Eulerian angles attitude data, then utilize PID arithmetic bunch that attitude data is corrected accordingly, finally lead to Cross the second DMA channel output data and reach to control the purpose of attitude.Present invention employs hardware mode the attitude of aircraft is entered Having gone corresponding control, the use of special circuit makes the response delay of control system compare single-chip microcomputer or CPU controls significantly to drop Low, the single-chip microcomputer or CPU that were originally in gesture stability are freed from algorithm.The present invention uses multi input+multiagent to hand over The hardware systems framework of fork interconnection+superpipeline+multiple target, wherein multi input refers to that multiaxis can be sensed by the input of IP kernel The data input of device output, multiagent is cross interconnected and superpipeline refers to that the calculating bunch of inside and hardware PID are total in interconnection On line by according to preprogramming composition one googol according to circulation flow path, multiple target refer to DMA under programmed control by data by Export according to the path specified.

The above, the only present invention preferably detailed description of the invention, but protection scope of the present invention is not limited thereto, Any those familiar with the art in the technical scope that the invention discloses, according to technical scheme and Inventive concept equivalent or change in addition, all should contain within protection scope of the present invention.

Claims (8)

1. an aircraft manufacturing technology IP kernel able to programme, it is characterised in that described IP kernel includes:

First On-Chip peripheral；Described first On-Chip peripheral is for receiving the 3-axis acceleration of aircraft, three axis angular rates and three axles Magnetic field data；

Connect the first On-Chip peripheral and filtering operation device, for 3-axis acceleration, three axis angular rates and three-axle magnetic field data being passed Transport to the first DMA channel of filtering operation device；

For 3-axis acceleration, three axis angular rates and three-axle magnetic field data being filtered respectively the filtering operation device processed；Institute State filtering operation device and include 9 filtering operation unit；Each filtering operation unit the most corresponding 3-axis acceleration, three axis angular rates With a kind of data in three-axle magnetic field data；Each filtering operation unit all includes FIR filter, iir digital filter and slip At least one in window filter；

Connect filtering operation device, for carrying out appearance according to filtered 3-axis acceleration, three axis angular rates and three-axle magnetic field data The attitude fusion calculation bunch of the Eulerian angles of state fusion calculation output aircraft；

Connect attitude fusion calculation bunch, for the Eulerian angles of attitude fusion calculation bunch output being carried out the PID arithmetic of PID correction Bunch；

Connect PID arithmetic bunch, for revised for PID Eulerian angles being transmitted to the second of aircraft by the second On-Chip peripheral DMA channel；

Second On-Chip peripheral；The Eulerian angles that second DMA channel is transmitted by described second On-Chip peripheral are transmitted to aircraft；

Described attitude fusion calculation bunch includes:

Connection filtering operation device, 3-axis acceleration, three axis angular rates and the three-axle magnetic field data after input filter, and to it In 3-axis acceleration and three-axle magnetic field data carry out unitization input data and process bunch；

Connect quaternion product sub-clustering, for quaternary number q0, q1, q2, q3 for quaternion product sub-clustering output, obtain in quaternary number Between flow q0*q0, q0*q1, q0*q2, q0*q3, q1*q1, q1*q2, q1*q3, q2*q2, q2*q3, q3*q3 intermediate flow calculate Bunch；

Connect and input data process bunch and intermediate flow calculating bunch, for inputting the three-axle magnetic field data of data process bunch output by body coordinate System is converted to earth axes, and processes bunch 3-axis acceleration, three axis angular rates and a three-axle magnetic field number for output according to input data According to, calculate bunch quaternary number intermediate flow of output in conjunction with intermediate flow and draw the Coordinate Conversion calculating bunch of the quaternary number margin of error；Described Coordinate Conversion Calculating bunch utilizes formulaCalculate the three-axle magnetic field data (b being converted to earth axes by body axis system_x, b_y,b_z), wherein (m_x,m_y,m_z) process bunch 3-axis acceleration data for output for input data；The calculating bunch of described Coordinate Conversion utilizes formulaCalculate the quaternary number margin of error (e_x,e_y,e_z), wherein (a_x,a_y, a_z) for input data process bunch output 3-axis acceleration data,

Connection coordinate conversion Calculation bunch, for utilizing the quaternary number margin of error that three axis angular rate data are performed proportional integral correction PI correction bunch；Described PI correction bunch utilizes formulaObtain revised three axis angular rates of PI Data (u_x,u_y,u_z), wherein (g_x,g_y,g_z) process bunch three axis angular rate data of output, a K for input data_pFor the ratio set Example coefficient, (e_x,e_y,e_z) be the quaternary number margin of error,(e_xInt,e_yInt,e_zInt) it is right (e in a upper integration period_x,e_y,e_z) respective integration, K_iFor the integral coefficient set；

Connect PI correction bunch, generate for the quaternary number according to revised three axis angular rate data and a upper integration period current The quaternion product of integration period quaternary number divides calculating bunch；Described quaternion product divides calculating bunch to utilize formulaDraw the quaternary number q0 ' in current integration cycle, Q1 ', q2 ', q3 ', wherein q0_b,q1_b,q2_b,q3_bQuaternary number, (u for a upper integration period_x,u_y,u_z) it is PI revised three Axis angular rate data, halfT are setup parameter；Generating current integration cycle quaternary number q0 ', q1 ', q2 ', q3 ' rear described four Unit's number integral and calculating bunch is additionally operable to carry out unitization to q0 ', q1 ', q2 ', q3 ' and obtain q0, and q1, q2, q3 export to intermediate flow Calculating bunch and rapid translating bunch；

Connecting quaternion product sub-clustering, for the q0 according to quaternion product sub-clustering output, q1, q2, q3 obtain quickly turning of Eulerian angles Change bunch；Described rapid translating bunch utilizes formulaCalculate rolling Tangent trigonometric function value tan (Roll) of corner R oll, sine trigonometric function value sin (Pitch) of angle of pitch Pitch, driftage Tangent trigonometric function value tan (Yaw) of angle Yaw；Described rapid translating bunch also includes prestoring each angle and corresponding each angle Tangent trigonometric function value and the look-up table of sine trigonometric function value；Described rapid translating bunch is according to tangent trigonometric function value tan (Roll), sine trigonometric function value sin (Pitch) and tangent trigonometric function value tan (Yaw), determine roll angle in conjunction with look-up table Roll, angle of pitch Pitch and yaw angle Yaw.

One the most according to claim 1 aircraft manufacturing technology able to programme IP kernel, it is characterised in that described IP kernel also wraps Include quick interconnection；Described quick interconnection is for connecting the first DMA channel and filtering operation device, and connection attitude is melted Add up to calculation bunch and PID arithmetic bunch.

One the most according to claim 1 aircraft manufacturing technology able to programme IP kernel, it is characterised in that described sliding window Wave filter includes having the first FIFO memory of 8 memory element, adder unit, addition selector and barrel shift Depositor；Described adder unit is for calculating data sum that front 2 memory element of the first FIFO memory deposit, front Data sum that 4 memory element are deposited and the data sum that 8 memory element are deposited；Described addition selector is for right Above three data sum carries out selecting and exporting to barrel shift depositor.

One the most according to claim 3 aircraft manufacturing technology able to programme IP kernel, it is characterised in that a described DMA leads to Road and the second DMA channel are respectively provided with 9 input channels, input connects the input selector of 9 input channels, connect input choosing The second FIFO memory selecting device outfan, the outlet selector connecting the second FIFO memory and connection outlet selector Output channel.

One the most according to claim 4 aircraft manufacturing technology able to programme IP kernel, it is characterised in that described quick interconnection Bus includes multiple input bus and multiple output bus；Data are realized by the break-make controlling each input bus and output bus Selection input or output.

One the most according to claim 5 aircraft manufacturing technology able to programme IP kernel, it is characterised in that IP kernel also includes even Connect the control Parasites Fauna of the first DMA channel, quick interconnection, attitude fusion calculation bunch, PID arithmetic bunch；Described control is posted Storage group, for controlling the selection operation of described input selector, controls the break-make of each input bus and output bus, sets PI The proportionality coefficient of correction bunch and integral coefficient, and set the proportionality coefficient of PID arithmetic bunch, integral coefficient and differential coefficient.

One the most according to claim 5 aircraft manufacturing technology able to programme IP kernel, it is characterised in that described IP kernel also wraps Including general quick calculating bunch, this general quick calculating bunch includes the bus monitor connecting each output bus and connects bus monitoring The microprocessor of device；

Described bus monitor includes connecting the Ll data caches depositor of output bus, connecting Ll data caches depositor Secondary data buffer register, connect Ll data caches depositor and receive with reference to the first comparing unit of limit value, connection Ll data caches depositor and the second comparing unit of secondary data buffer register and connect the first comparing unit and the First result selector of two comparing units；Described first comparing unit is for by working as of depositing in Ll data caches depositor Front data compare with reference to limit value, and the output abnormality signal when current data exceedes with reference to limit value；Described second compares Unit for the upper data of current data that will deposit in secondary data buffer register with in Ll data caches depositor The current data deposited compares, the second comparing unit when the difference of data is beyond certain limit on current data is with it Output abnormality signal；Above-mentioned two abnormal signal is selected and is sent to interrupt event to generate by described first result selector Device；Described bus monitor also includes depositing monitoring depositor, connecting output bus and monitor the of depositor of preliminary data Two result selectores；Described microprocessor disconnecting event generating and described second result selector, for when receiving During the interrupt signal that interrupt event maker sends, control the second result selector output and monitor the preliminary data that depositor is deposited To result bus.

One the most according to claim 7 aircraft manufacturing technology able to programme IP kernel, it is characterised in that described microprocessor Use VLIW collection framework, and Deep integrating is inside IP kernel.