CN104880190B - A kind of intelligent chip accelerated for the fusion of inertial navigation posture - Google Patents
A kind of intelligent chip accelerated for the fusion of inertial navigation posture Download PDFInfo
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- CN104880190B CN104880190B CN201510294532.5A CN201510294532A CN104880190B CN 104880190 B CN104880190 B CN 104880190B CN 201510294532 A CN201510294532 A CN 201510294532A CN 104880190 B CN104880190 B CN 104880190B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/10—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration
- G01C21/12—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning
- G01C21/16—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning by integrating acceleration or speed, i.e. inertial navigation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/20—Instruments for performing navigational calculations
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Abstract
The invention discloses a kind of intelligent chips accelerated for the fusion of inertial navigation posture, the gradient-pole value-based algorithm of attitude algorithm is solidified into hardware-accelerated logic by the intelligent chip, software is resolved and is combined together with hardware-accelerated, the intelligent chip includes successively according to the order of data flow from output is input to：SPI communication interface module（1）, quaternary number initialization module（2）, high speed registration module（3）, quaternary number update module（4）With quaternion feedback and output module（5）, to promote the speed and precision of the fusion of inertial navigation system posture.
Description
Technical field
The present invention relates to technical field of inertial more particularly to a kind of intelligent cores accelerated for the fusion of inertial navigation posture
Piece.
Background technology
Course attitude reference system（Attitude Heading Reference System）Solving technique, abbreviation appearance
State integration technology is a mostly important and basic technology of field of navigating now, particularly with inertial navigation field.This
The highest demand of technology is exactly that the inertia device carried by carrier is capable of the completion carrier of high precision in real time in terrestrial coordinates
Attitude orientation under system.Towards this direction, the realization of the posture integration technology based on MEMS inertia devices has 3 kinds of sides so far
Formula：Based on MCU（Micro Control Unit）Embedded system inertial navigation posture integration technology；Based on MCU and DSP
（Digital Signal Processor）Cascade inertial navigation posture integration technology；Based on application-specific integrated circuit（Application
Specific Integrated Circuit）The inertial navigation posture integration technology of chip fixed logic.
In most of posture fusion application, the work for correcting often most time-consuming effort of error, these errors
Include evaluated error when parasitic error and the calculating between inertia device Acquisition Error in itself, inertia vector, these
The computing of elimination error has tended to take up the computing resource in entire posture calculating process more than 80 percent, therefore, in reality
In the posture fusion application on border, accuracy and speed needs to find an equalization point that can be compromised.
Kalman filtering method mathematically has unique advantage, French scholar Jose- for the calculating of error concealment
The MCU of Fermi Guerrero-Castellanos constructions is played with the cascade Kalman Filter Technologies of DSP on posture merges
Preferable error concealment effect, but renewal speed is slower, and requirement in real time completely is not achieved.This is largely due to its calculating
Complexity, in fact, Kalman filtering method is in actual posture fusion application, due to the mutation of its characteristic parameter, often
It is difficult to grasp, and Kalman filtering method is usually associated with extremely huge calculation amount, it is necessary to pay high calculating cost, makes
Use narrow range.
British scholar Sebastian O.H. Madgwick propose using gradient-pole value-based algorithm be then another compared with
ERROR ALGORITHM is merged for general posture, it is a kind of error function matrix for being to construct inertia vector system, utilizes error
The gradient of matrix is constantly approached, the method for last convergence error.This method is proved in low frequency system greatly to carry
At high speed, in the posture integration technology based on MCU of Madgwick, this method be demonstrated by better than Kalman filtering the characteristics of.
But the solving technique of this MCU platforms based on single CPU, apparent inferior position can be shown in frequency applications, not only such as
This, also due to computing capability is limited, the embedded inertial navigation posture integration technology based on MCU still reaches in accuracy and speed
Less than preferable requirement.
Two kinds of posture integration technologies of summary accelerate cascade system, more using pure software system and software with DSP
It is more good and bad in new speed, precision and cost：Pure software system accuracy is general, response speed at low frequency can be with high frequency misses
The lower distortion of difference, cost are relatively low；Software and DSP cascade system precision are pretty good, response speed is undesirable, and cost is costly.It is overall
For, two methods respectively have quality, but all not ideal enough, and basic reason is still that the computing capability of two kinds of technologies is limited.
The starting point of the present invention is the advantage for drawing above two posture integration technology, and avoids their inferior position.
Specifically, the present invention algorithmically inherit gradient extreme value integration technology it is flexible the advantages of, meanwhile, in order to make up
Computing capability takes the IC chip scheme of design specialized, designs special cured hardware logic and melts to resolve posture
Collaboration is united, and avoids the solution process that the lower rule sequential instructions collection of software way takes time and effort.For dedicated integrated circuit
For chip, since the reaction time of hardware gate circuit logic is in the unit of picosecond（10-12 seconds）And microprocessor instruction
The reaction time of collecting system is in the unit of Microsecond grade（10-6 seconds）, have nearly millionfold ability in speed and calculating capacity
It is promoted, the raising of speed also implies that the quickening of renewal frequency simultaneously, and so, the convergence of error can become rapider, be
The precision of system can also obtain proportional raising.The emphasis of the present invention is that be made up using the advantage of dedicated IC chip
The defects of in computing capability, while original gradient extreme value blending algorithm flexibly accurate advantage is played, both is allowed to be organized in
It performs and staggeredly exists in the time and space design of posture fusion application, work in perfect harmony, reach most efficient attitude algorithm effect.
Therefore it provides a kind of intelligent chip accelerated for the fusion of inertial navigation system posture, is melted with promoting inertial navigation system posture
The speed and precision of conjunction.
The content of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of intelligent chip accelerated for the fusion of inertial navigation system posture,
To promote the speed and precision of the fusion of inertial navigation system posture.
A kind of intelligent chip accelerated for the fusion of inertial navigation posture, the intelligent chip calculate the gradient extreme value of attitude algorithm
Method is solidified into hardware-accelerated logic, and software is resolved and is combined together with hardware-accelerated, the intelligent chip is according to data flow
Order includes successively from output is input to：SPI communication interface module, quaternary number initialization module, high speed registration module, quaternary number
Update module and quaternion feedback and output module；
The SPI communication interface module is for the data transmission of the intelligent chip and external spi bus, the quaternary
Number initialization module is vectorial via SPI communication interface module input carrier three-dimensional inertia from MEMS inertia devices for caching
Group data and the initial value that quaternary number is calculated according to the three-dimensional inertia Vector Groups data;The high speed registration module for pair
The quaternionic vector of three-dimensional inertia vector and initialization after the normalization of quaternary number initialization module input carries out slow at a high speed
It deposits;The quaternary number update module is used to carry out appearance to the inertia vector sum initialization quaternary number inputted from high speed registration module
State merges, and updates the solution of quaternary number and the solution of quaternary number is sent to quaternion feedback and output module；The quaternion feedback
And output module is used to that the update quaternionic vector data inputted from the quaternary number update module to be carried out refilling dress and output.
Preferably, it is described be solidified into hardware-accelerated logical AND described in software resolve and there are in same system and be incorporated in one
It rises and completes attitude algorithm.
Preferably, the front end interface of the SPI communication interface module is connected with spi bus slot, and external signal passes through SPI
The form disengaging chip of serial data packet；The SPI serial ports of the intelligent chip are for reception with High Speed Serial transmission mode
The inertia Vector Groups data that MEMS sensor through the SPI slots on embedded microprocessor unit is gathered；The SPI communication interface
The back end interface of module is connected with quaternary number initialization module.
Preferably, the SPI communication interface module includes SPI communication core module and SPI application modules, wherein SPI communication
Core module is used to perform physical layer, the data link layer of data exchange；SPI application modules initialize for managing the quaternary number
Module, the quaternion feedback and output module and external host computer or external spi bus, inertia vector location and
Data exchange between MEMS inertia devices.
Preferably, the three-dimensional inertia vector includes carrier acceleration, angular speed and magnetic field intensity.
Preferably, it is initial to include FIFO stack modules, normalization engine modules, Eulerian angles for the quaternary number initialization module
Change module and Eulerian angles turn quaternary digital-to-analogue block, the FIFO stack modules obtain for caching from SPI communication interface module
Three-dimensional inertia Vector Groups data are simultaneously transferred to the normalization engine modules and the Eulerian angles initialization module, described three-dimensional used
Property Vector Groups data include carrier acceleration, angular speed and magnetic field intensity, be transferred to the three-dimensional of the Eulerian angles initialization module
Inertia vector data includes carrier acceleration and magnetic field intensity information；
The normalization engine modules, for the three-dimensional inertia Vector Groups that will be obtained from FIFO stack modules carry out floating-point to
The normalization computing of amount, and result is transferred to the Eulerian angles and turns quaternary digital-to-analogue block and the high speed registration module；It is transferred to
The data that the Eulerian angles turn quaternary digital-to-analogue block include the vector acceleration after normalization, are transferred to the high speed registration module
Data include the vector acceleration after normalization, angular velocity vector and magnetic field intensity vector；
The Eulerian angles initialization module is used for the Eulerian angles initial value of synthetic vectors, by being connect from the FIFO stack modules
Vector acceleration and magnetic field intensity the vector progress referential project to be come over, the Eulerian angles initial value rotated, and will
The Eulerian angles array of initialization passes to Eulerian angles and turns quaternary digital-to-analogue block, which includes course angle, pitch angle and rolling
Corner；
The Eulerian angles turn quaternary digital-to-analogue block for the Eulerian angles array to be converted into corresponding quaternionic vector, and will just
The quaternionic vector of beginningization is transferred to high speed registration module.
Preferably, the normalization engine modules include acceleration normalization tube bank, angular speed normalization tube bank and magnetic field
Intensity normalization tube bank, they handle three-dimensional floating-point vector acceleration normalization computing respectively, three-dimensional floating-point angular velocity vector is returned
One changes computing and three-dimensional floating-point magnetic field intensity vector normalization computing.
Preferably, the high speed registration module include 4 independent cache memories, they side by side work independently with
In the same area, wherein：
Acceleration buffer be used for store quaternary number initialization module input normalization after vector acceleration, and according to
Demand is sent to quaternary number update module；
Angular speed buffer be used for store quaternary number initialization module input normalization after angular velocity vector, and according to
Demand is sent to quaternary number update module；
Magnetic field intensity buffer is used to store the magnetic field intensity vector after the normalization of quaternary number initialization module input, and
Quaternary number update module is sent to according to demand；
Quaternary number buffer be used for store quaternary number initialization module input initialization after quaternionic vector, and according to
Demand is sent to quaternary number update module.
Preferably, the quaternary number update module includes update state machine module, angular speed derivative module, Jacobian matrix
Module and gradient decline blending algorithm module,
The update state machine module is used to controlling and monitoring the angular speed derivative module, the Jacobean matrix array module
And the gradient declines the order of operation and data exchange between blending algorithm module；
The angular speed derivative module is used for the angular velocity vector of high speed registration module transmission and initialization quaternary
Number vector is differentiated, and is passed the result to the gradient under the control of the update state machine module and declined fusion
Algoritic module；
The Jacobean matrix array module be used for the high speed registration module transmission vector acceleration, angular velocity vector,
Magnetic field intensity vector sum initialization quaternionic vector carries out the computing that joint solves Jacobi equation, and in the update state machine
The gradient is passed the result under the control of module and declines blending algorithm module；
It is micro- to the angular speed according to the gradient-pole value-based algorithm of multi-C vector function that the gradient declines blending algorithm module
The result that sub-module and the Jacobean matrix array module come out carries out fusion operation, obtains update quaternary number, and in the update
Quaternion feedback and output module are passed the result under state machine module control.
Preferably, the quaternion feedback and output module include feedback states machine, refill module and output module,
In：
Feedback states machine module refills operation and the data exchange of module and output module for controlling；
Module is refilled to be responsible for again writing the updated quaternionic vector data of quaternary number update module input
Enter to the quaternary number buffer in high speed registration module, and cover original initialization quaternionic vector data and generate newer four
First number data；
Output module is responsible for the newer quaternion algebra according to output to external host computer.
Technical scheme has the advantages that：
1. provided by the present invention for the intelligent chip that the fusion of inertial navigation posture accelerates, MCU or DSP is utilized with popular
The instruction set service speed of posture integration technology compare, chip gate leve calculating speed has the promotion of 103 times of grades.Meanwhile it updates
The raising of speed accelerates the speed of error convergence, there is at least 102 times of promotion in precision.On the other hand, the present invention is in number
According to the structure that the mounting hardware logic used in the processing of stream accelerates, with real-time gate leve picosecond（10-12 seconds）The sound of grade delay
Frequency is answered to surmount MCU or DSP instruction set microseconds（10-6 seconds）The service speed of delay.
2. provided by the present invention for the intelligent chip that the fusion of inertial navigation posture accelerates, with general posture integration technology phase
Than employing more flexible modified gradient extreme value blending algorithm, not only convergence rate and precision are satisfactory, but also will calculate
Method makes appropriate reconstruction, to coordinate the accelerating structure of hardware logic, by the flexible advantage of algorithm and the advantage of the speed of hardware
It is combined together, the effect of algorithm in itself is made to perform to maximum efficiency.
Description of the drawings
Below by drawings and examples, technical scheme is described in further detail.
Fig. 1 is that the inertial navigation system posture fusion of the present invention accelerates the structure diagram of intelligent chip；
Fig. 2 is the structure diagram of quaternary number initialization module in Fig. 1；
Fig. 3 is the structure diagram of quaternary number update module in Fig. 1；
Fig. 4 is the structure diagram of quaternion feedback and output module in Fig. 1.
Specific embodiment
In order to have a clear understanding of technical scheme, its detailed structure will be set forth in the description that follows.Obviously, originally
The specific simultaneously deficiency of implementing of inventive embodiments is limited to the specific details that those skilled in the art is familiar with.The preferred reality of the present invention
It applies example to be described in detail as follows, in addition to these embodiments of detailed description, can also have other embodiment.
The fusion of inertial navigation system posture accelerates the special integrated electricity that the structure of intelligent chip is a high-speed digital video camera
Road intelligent chip is integrated with follow-on gradient-pole value-based algorithm and is cured in the form of hardware logic, dedicated for accelerating
With course therein and attitude algorithm part, according to the three-dimensional inertial sensor being connected on carrier system, real-time resolving represents
Carrier course and the required Eulerian angles of posture and quaternary number.
With reference to Fig. 1, the overall architecture realized described in figure and for the present invention.MCU system and inertial navigation system posture in Fig. 1
Fusion intelligent chip is directly connected to via chip pin, and the bus marco end of association system is used as by the spi bus of MCU, this
It is that a kind of MCU system merges the tandem type design structure that intelligent chip shares same system plate with inertial navigation system posture.It is external
MEMS three-dimensionals Inertial Sensor System it is then direct-connected by the communication pin and MCU system of SPI, under the control of MCU system, be used to
Property the inertia Vector Groups data that are gathered of sensor be endlessly transported on inertial navigation system posture fusion intelligent chip.
The gradient-pole value-based algorithm of attitude algorithm is solidified into hardware-accelerated logic by intelligent chip in figure, by software resolving and firmly
Part acceleration is combined together, it is described be solidified into hardware-accelerated logical AND described in software resolve and there are in same system and be incorporated in
Complete attitude algorithm together, each inertial navigation system posture fusion intelligent chip is made of 5 modules, according to the order of data flow from
Be input to output includes successively：SPI communication interface module 1, quaternary number initialization module 2, high speed registration module 3, quaternary number are more
New module 4, quaternion feedback and output module 5.
Wherein, SPI communication interface module 1 is used to implement the data transmission of the attitude algorithm chip and external spi bus, preceding
End interface is connected with spi bus slot, and external signal passes in and out chip by the form of SPI serial data packets；MEMS sensor institute
The inertia Vector Groups data of acquisition are transferred into this appearance with High Speed Serial transmission mode through the SPI slots on embedded microprocessor unit
State resolves the serial port for the SPI for accelerating chip；The back end interface of SPI communication interface module connects with quaternary number initialization module 2
It connects.
The SPI communication interface module 1 includes SPI communication core module and SPI application modules, wherein SPI communication core module
For performing the physical layer of data exchange, data link layer；SPI application modules for manage the quaternary number initialization module 2,
The quaternion feedback and output module 5 are used to external host computer or external spi bus, inertia vector location and MEMS
Data exchange between property device.
Wherein, the quaternary number initialization module 2 is cached from MEMS inertia devices via SPI communication interface mould
1 input carrier three-dimensional inertia Vector Groups data of block and the initial value that quaternary number is calculated according to the three-dimensional inertia Vector Groups data,
The inertia Vector Groups data that MEMS sensor is gathered include at least：Carrier three-dimensional angular velocity Vector Groups, carrier three-dimensional acceleration
Vector Groups and carrier three-dimensional magnetic field intensity vector group.
Quaternary number initialization module 2 is responsible for these inertia vectors for collecting of processing and calculates initial quaternary numerical value,
It is divided according to functional structure, quaternary number initialization module 2 includes：FIFO stack modules 21, normalization engine modules 22, Eulerian angles
Initialization module 23 and Eulerian angles turn quaternary digital-to-analogue block 24.
Refer to the attached drawing 2, we explain in detail the structure of quaternary number initialization module 2：
First, angular speed, acceleration and magnetic field strength date can be cached by the asynchronous FIFO of a high speed, it is therefore an objective to
Handle the cross clock domain problem between SPI communication interface module and quaternary number initialization module（Cross clock domain：In digit chip by
Differ in clock rate to caused metastable state and data exception problem）, another is exactly the spilling of data in order to prevent, this
A module is known as FIFO stack modules 21；
Normalization engine modules 22 can be sent to after inertia vector data is by FIFO shapings, including angular speed acceleration
And magnetic field intensity, which part vector data is also sent to Eulerian angles initialization module 23, including acceleration and magnetic field intensity；
When inertia vector data comes normalization engine, it can be arranged in three parallel bundle-shaped pipeline organizations,
It is angular speed normalizing beam, acceleration normalizing beam and magnetic field intensity normalizing beam respectively, independent parallel carries out vectorial normalizing mathematically
Change computing, after the completion of normalization, whole data can send quaternary number initialization module 2, be sent to high speed registration module 3, part
The Eulerian angles that data can be sent to simultaneously inside quaternary number initialization module 2 turn quaternary digital-to-analogue block 24；
As it was noted above, at the beginning of the acceleration information and magnetic field strength date after FIFO arrangements are sent to Eulerian angles simultaneously
Beginningization module 23 herein, adds according to relatively-stationary gravitational acceleration vector and absolute force vector with the carrier measured
The angled relationships of velocity vector and magnetic field intensity vector, it is preliminary to resolve the Eulerian angles of carrier, and the data obtained is transmitted to Eulerian angles
Turn quaternary digital-to-analogue block 24；
Eulerian angles turn the quaternary number that quaternary digital-to-analogue block 24 is responsible for the Eulerian angles of initialization being converted into initialization, here quaternary
The synthesis of number initial vector is in addition to the Eulerian angles for needing to initialize, it is also necessary to which the acceleration value after normalizing participates in, most
Eventually, obtained initialization quaternary number is exported to next module high speed registration module 3.
Refer to the attached drawing 1, high speed registration module 3 are actually to be made of 4 independent high-speed memories, are each responsible for caching
Angular velocity data, acceleration information, magnetic field strength date and quaternionic vector data, entire high speed registration module, which plays, holds
Effect under opening, is responsible for shaping and the flow of data flow, and the data of these cachings are issued next modular unit four on demand
First number update module 4.Wherein, the input terminal of quaternionic vector buffer its actually by two sources, one come from just
The quaternion algebra of beginningization quaternary digital-to-analogue block 2 according to vector, another from the quaternion algebra evidence conveyed with quaternion feedback module 5,
Quaternion algebra evidence is write by quaternary number initialization module when the buffer is except system initialization, other renewal times are then
It is constantly covered by feedback module write-in, it is therefore an objective to constantly update quaternary number to achieve the purpose that convergence error.
Quaternary number update module 4 is used to carry out the inertia vector sum initialization quaternary number inputted from high speed registration module 3
Posture merges, and the solution of quaternary number is simultaneously sent to quaternion feedback and output module 5 by the solution for updating quaternary number, according to its function,
We are divided into the basic structure of four pieces of two-stage.
Refer to the attached drawing 3, as described in Figure, quaternary number update module 4 include update state machine module 41, angular speed derivative module
42nd, Jacobean matrix array module 43 and gradient decline blending algorithm module 44；
Update state machine module 41 is used to controlling and monitoring angular speed derivative module 42, Jacobean matrix array module 43 and ladder
Degree declines the order of operation and data exchange between blending algorithm module 44；
42 pieces of angular velocity vectors being used for being transmitted from high speed registration module 3 of angular speed module of differentials and initialization quaternary
Number vector is differentiated, and is passed the result to gradient in the case where update state machine module 41 controls and declined blending algorithm module
44；
Jacobean matrix array module 43 be used for transmitted from high speed registration module 3 vector acceleration, angular velocity vector,
Magnetic field intensity vector sum initialization quaternionic vector carries out the computing that joint solves Jacobi equation, and in update state machine module
Gradient, which is passed the result to, under 41 controls declines blending algorithm module 44；
Gradient declines blending algorithm module 44 according to the gradient-pole value-based algorithm of multi-C vector function to from angular speed module of differentials
The result that block 42 and Jacobean matrix array module 43 come out carries out fusion operation, obtains newer quaternary number, and in update state machine
Quaternion feedback and output module 5 are passed the result under module control 41.
After the solution of newer quaternary number is sent to quaternion feedback and output module 5, quaternion feedback and output mould
Block 5 is used to that the update quaternionic vector data inputted from the quaternary number update module 4 to be carried out refilling dress and output, specific next
It says, quaternion feedback and output module 5 are responsible for refilling newer quaternionic vector data to four in high speed registration module 3
First number buffer, while the data of the quaternionic vector are sent to by the control of SPI communication interface module 1 external upper
Machine.Therefore, it can be there are two mission：First, output is declared that this is resolved and is completed to the host computer outside chip；On the other hand, originally
Secondary solution will be also filled into rapidly in quaternary number buffer, can only be in this way, quaternary number as the starting point for updating computing next time
The error of update ability constantly convergence solution obtains the solution of high-precision attitude of carrier fusion.
Accordingly, refer to the attached drawing 4, quaternion feedback and output module 5 are so carried out and organize：
Quaternion feedback and output module 5 by feedback states machine, refill three modules of module and output module and form；
Feedback states machine module refills operation and the data exchange of module and output module for controlling；
Refill the updated quaternionic vector data that module is responsible for inputting quaternary number update module 4 write again to
Quaternary number buffer in high speed registration module 3, and cover original initialization quaternionic vector data；
Output module is responsible for the newer quaternion algebra according to output to external host computer, and completes entire inertial navigation posture and melt
The resolving task of conjunction.
Provided by the present invention for the intelligent chip that the fusion of inertial navigation posture accelerates, utilize MCU's or DSP with popular
The instruction set service speed of posture integration technology is compared, and chip gate leve calculating speed has the promotion of 103 times of grades.Meanwhile update speed
The raising of degree accelerates the speed of error convergence, there is at least 102 times of promotion in precision.On the other hand, the present invention is in data
The structure that the mounting hardware logic used in the processing of stream accelerates, with real-time gate leve picosecond（10-12 seconds）The response of grade delay
Frequency surmounts MCU or DSP instruction set microseconds（10-6 seconds）The service speed of delay；Compared with general posture integration technology, adopt
With more flexible modified gradient extreme value blending algorithm, not only convergence rate and precision are satisfactory, but also algorithm is done
Go out appropriate reconstruction, to coordinate the accelerating structure of hardware logic, the advantage of the flexible advantage of algorithm and the speed of hardware is combined
Together, the effect of algorithm in itself is made to perform to maximum efficiency.
Finally it should be noted that：The above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, to the greatest extent
Pipe is described in detail the present invention with reference to above-described embodiment, and those of ordinary skill in the art still can be to this hair
Bright specific embodiment is modified or replaced equivalently, these without departing from spirit and scope of the invention any modification or
Equivalent substitution is being applied within pending claims.
Claims (10)
1. a kind of intelligent chip accelerated for the fusion of inertial navigation posture, which is characterized in that the intelligent chip is by attitude algorithm
Gradient-pole value-based algorithm is solidified into hardware-accelerated logic, and software is resolved and is combined together with hardware-accelerated, and software resolves part and wraps
It includes：Quaternary number initialization module (2) and quaternary number update module (4)；Hardware-accelerated part includes：SPI communication interface module
(1), high speed registration module (3) and quaternion feedback and output module (5)；
The intelligent chip includes successively according to the order of data flow from output is input to：SPI communication interface module (1), quaternary
Number initialization module (2), high speed registration module (3), quaternary number update module (4) and quaternion feedback and output module (5)；
The SPI communication interface module (1) is for the data transmission of the intelligent chip and external spi bus, the quaternary number
Initialization module (2) is for caching from MEMS inertia devices via SPI communication interface module (1) input carrier three-dimensional inertia
Vector Groups data and the initial value that quaternary number is calculated according to the three-dimensional inertia Vector Groups data；The high speed registration module (3)
For the three-dimensional inertia vector after the normalization that is inputted to quaternary number initialization module (2) and the quaternionic vector of initialization into
Row cache；The quaternary number update module (4) is used to initialize the inertia vector sum inputted from high speed registration module (3)
Quaternary number carries out posture fusion, updates the solution of quaternary number and the solution of quaternary number is sent to quaternion feedback and output module (5)；
The quaternion feedback and output module (5) are used for the update quaternionic vector to being inputted from the quaternary number update module (4)
Data carry out refilling dress and output.
2. the intelligent chip according to claim 1 accelerated for the fusion of inertial navigation posture, which is characterized in that described to be solidified into
Software described in hardware-accelerated logical AND resolves and there are in same system and be combined together and complete attitude algorithm.
3. the intelligent chip according to claim 1 accelerated for the fusion of inertial navigation posture, which is characterized in that the SPI leads to
The front end interface of letter interface module (1) is connected with spi bus slot, and external signal is passed in and out by the form of SPI serial data packets
Chip；The SPI serial ports of the intelligent chip are for reception with High Speed Serial transmission mode through on embedded microprocessor unit
The inertia Vector Groups data that the MEMS sensor of SPI slots is gathered；The back end interface of the SPI communication interface module (1) with
Quaternary number initialization module (2) connects.
4. the intelligent chip according to claim 3 accelerated for the fusion of inertial navigation posture, which is characterized in that the SPI leads to
Believe that interface module (1) includes SPI communication core module and SPI application modules, wherein SPI communication core module is used to perform data exchange
Physical layer, data link layer；SPI application modules are used to manage the quaternary number initialization module (2), the quaternion feedback
And between output module (5) and external host computer or external spi bus, inertia vector location and MEMS inertia devices
Data exchange.
5. the intelligent chip according to claim 1 accelerated for the fusion of inertial navigation posture, which is characterized in that described three-dimensional used
Property vector include carrier acceleration, angular speed and magnetic field intensity.
6. the intelligent chip according to claim 5 accelerated for the fusion of inertial navigation posture, which is characterized in that the quaternary number
Initialization module (2) includes FIFO stack modules (21), normalization engine modules (22), Eulerian angles initialization module (23) and Europe
Angle is drawn to turn quaternary digital-to-analogue block (24), the FIFO stack modules (21) obtain for caching from SPI communication interface module (1)
Three-dimensional inertia Vector Groups data are simultaneously transferred to the normalization engine modules (22) and the Eulerian angles initialization module (23), institute
Stating three-dimensional inertia Vector Groups data includes carrier acceleration, angular speed and magnetic field intensity, is transferred to the Eulerian angles initialization mould
The three-dimensional inertia vector data of block (23) includes carrier acceleration and magnetic field intensity information；
The normalization engine modules (22), for the three-dimensional inertia Vector Groups obtained from FIFO stack modules (21) to be floated
The normalization computing of point vector, and result is transferred to the Eulerian angles and turns quaternary digital-to-analogue block (24) and the high speed registration module
(3)；Being transferred to the Eulerian angles and turning the data of quaternary digital-to-analogue block (24) includes the vector acceleration after normalization, is transferred to described
The data of high speed registration module (3) include the vector acceleration after normalization, angular velocity vector and magnetic field intensity vector；
The Eulerian angles initialization module (23) is used for the Eulerian angles initial value of synthetic vectors, by from the FIFO stack modules
(21) receive the vector acceleration that comes and magnetic field intensity vector carries out referential project, at the beginning of the Eulerian angles rotated
Value, and the Eulerian angles array of initialization is passed into Eulerian angles and turns quaternary digital-to-analogue block, which includes course angle, pitching
Angle and roll angle；
The Eulerian angles turn quaternary digital-to-analogue block (24) for the Eulerian angles array to be converted into corresponding quaternionic vector, and will just
The quaternionic vector of beginningization is transferred to high speed registration module (3).
7. the intelligent chip according to claim 6 accelerated for the fusion of inertial navigation posture, which is characterized in that the normalization
Engine modules (22) are restrained including acceleration normalization, angular speed normalization tube bank and magnetic field intensity normalize tube bank, they divide
The three-dimensional floating-point vector acceleration normalization computing of other places reason, three-dimensional floating-point angular velocity vector normalization computing and three-dimensional floating-point magnetic field
Intensity vector normalizes computing.
8. the intelligent chip according to claim 1 accelerated for the fusion of inertial navigation posture, which is characterized in that the high speed is posted
Storing module (3) includes 4 independent cache memories, in their autonomous workings arranged side by side and the same area, wherein：
Acceleration buffer be used for store quaternary number initialization module (2) input normalization after vector acceleration, and according to
Demand is sent to quaternary number update module (4)；
Angular speed buffer be used for store quaternary number initialization module (2) input normalization after angular velocity vector, and according to
Demand is sent to quaternary number update module (4)；
Magnetic field intensity buffer is used to store the magnetic field intensity vector after the normalization of quaternary number initialization module (2) input, and
Quaternary number update module (4) is sent to according to demand；
Quaternary number buffer be used for store quaternary number initialization module (2) input initialization after quaternionic vector, and according to
Demand is sent to quaternary number update module (4).
9. the intelligent chip according to claim 1 accelerated for the fusion of inertial navigation posture, which is characterized in that the quaternary number
Update module (4) includes update state machine module (41), angular speed derivative module (42), Jacobean matrix array module (43) and gradient
Decline blending algorithm module (44), the update state machine module (41) is used to controlling and monitoring the angular speed derivative module
(42), the Jacobean matrix array module (43) and the gradient decline the order of operation and data between blending algorithm module (44)
It exchanges；
The angular speed derivative module (42) is used for the angular velocity vector of the high speed registration module (3) transmission and initialization four
First number vector is differentiated, and is passed the result under the control of the update state machine module (41) under the gradient
Blending algorithm module (44) drops；
The Jacobean matrix array module (43) be used for the high speed registration module (3) transmission vector acceleration, angular speed to
Amount, magnetic field intensity vector sum initialization quaternionic vector carry out the computing that joint solves Jacobi equation, and in the update shape
The gradient is passed the result under the control of state machine module (41) and declines blending algorithm module (44)；
It is micro- to the angular speed according to the gradient-pole value-based algorithm of multi-C vector function that the gradient declines blending algorithm module (44)
The result that sub-module (42) and the Jacobean matrix array module (43) come out carries out fusion operation, obtains update quaternary number, and
The update state machine module (41) passes the result to quaternion feedback and output module (5) under controlling.
10. the intelligent chip according to claim 1 accelerated for the fusion of inertial navigation posture, which is characterized in that the quaternary
Number feedback and output module (5) include feedback states machine, refill module and output module, wherein：
Feedback states machine module refills operation and the data exchange of module and output module for controlling；
Module is refilled to be responsible for again writing the updated quaternionic vector data of the quaternary number update module (4) input
Quaternary number buffer into high speed registration module (3), and it is newer to cover original initialization quaternionic vector data generation
Quaternion algebra evidence；
Output module is responsible for the newer quaternion algebra according to output to external host computer.
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| CN109001787B (en) * | 2018-05-25 | 2022-10-21 | 北京大学深圳研究生院 | Attitude angle resolving and positioning method and fusion sensor thereof |
| CN110887480B (en) * | 2019-12-11 | 2020-06-30 | 中国空气动力研究与发展中心低速空气动力研究所 | Flight attitude estimation method and system based on MEMS sensor |
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