CN104407183B - Test the forming method of syringe needle and semiconductor test jig - Google Patents
Test the forming method of syringe needle and semiconductor test jig Download PDFInfo
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- CN104407183B CN104407183B CN201410606939.2A CN201410606939A CN104407183B CN 104407183 B CN104407183 B CN 104407183B CN 201410606939 A CN201410606939 A CN 201410606939A CN 104407183 B CN104407183 B CN 104407183B
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Abstract
A kind of forming method of test syringe needle and semiconductor test jig, wherein the testing needle head forming method, including：Substrate is provided；The first testing needle is formed on the substrate；Insulating layer is formed on the side wall of the first testing needle；The second testing needle is formed on the surface of insulating layer, second testing needle is around first testing needle.The mechanical strength enhancing for the test syringe needle that the method for the present invention is formed, when carrying out electrical performance testing, improves the precision of test.
Description
Technical field
The present invention relates to semiconductor test technical field, more particularly to a kind of shape of test syringe needle and semiconductor test jig
At method.
Background technology
Test processing procedure is the electrical functionality for the product that test encapsulation is completed after IC package, to ensure IC functions of dispatching from the factory
On integrality, and the product to having tested according to its electrical functionality work classify, as the Appreciation gist of IC different brackets products, most
Make appearance test operation afterwards and to product.
Electrical functionality test is being tested for the various electrical parameters of product to determine product energy normal operation.
Test of two-point contact such as Kelvin's test etc. on traditional same tested terminal mostly uses Double ejection pin or double golden hands
The mode for referring to parallel side-by-side distribution, is primarily present following deficiency：
1, the accuracy of manufacture is relatively low：With the continuous diminution of semiconductor product size, it is tested the size of terminal and different quilts
The spacing surveyed between terminal is also constantly reducing, in order to comply with this trend, Conventional parallel and the Double ejection pin of column distribution or double golden hands
Refer to test mode its close spacing the problem of on bottleneck become increasingly conspicuous, required precision is higher and higher, some even cannot achieve
.
2, structural strength is weaker：In order to which two-point contact test, thimble or gold are realized in limited space on tested terminal
Finger is accordingly increasingly thinner, and Mechanical Structure Strength is also more and more weaker.
3, service life is shorter：The test contact head of traditional thimble or golden finger is easier to frayed, is especially carried in precision
Go out requirements at the higher level, mechanical strength it is relatively low when, degree of wear bigger thereby reduces the service life of measurement jig.
4, measuring accuracy is relatively low：To comply with the light and short growth requirement of semiconductor, increasingly thinner thimble or golden finger
Generated resistance value constantly increases, while when carrying out high-current test, will produce larger pressure drop and influencing test number
Judgement；On the other hand, the Double ejection pin of parallel side-by-side distribution or the also easy of double golden fingers produce because of offset deviation between the two
The deviation of raw test number；In addition, tradition and the Double ejection pin of column distribution in order to reduce the distance between two needles and use two back to
The way of contact on inclined-plane, contact head be easy because in its overall structure the torsion of telescopic spring due to rotate out of tested terminal so that influence
Measuring accuracy.
Invention content
Problems solved by the invention is precision and stability when how to improve existing electrical performance testing.
To solve the above problems, the present invention provides a kind of forming method of test syringe needle, including：Substrate is provided；Described
The first testing needle is formed in substrate；Insulating layer is formed on the side wall of the first testing needle；Second is formed on the surface of insulating layer to survey
Test point, second testing needle is around first testing needle.
Optionally, the forming process of first testing needle is：The first metal layer is formed on the substrate；Described in etching
The first metal layer forms the first testing needle.
Optionally, the forming process of first testing needle is：Sacrificial layer is formed on the substrate, in the sacrificial layer
With the through-hole for exposing substrate surface；Full the first metal layer is filled in the through-hole, forms the first testing needle；Described in removal
Sacrificial layer.
Optionally, the forming process of the insulating layer and the second testing needle is：It is formed and covers the first testing needle side wall
With the insulating thin layer of top surface；No mask etching technique etches the insulating thin layer and is formed in the side wall of the first testing needle
Insulating layer；Form the second metal layer for covering the insulating layer and the first testing needle top surface；Without described in mask etching second
Metal layer forms the second testing needle in surface of insulating layer.
Optionally, the forming process of the first detection needle, the second detection needle and insulating layer is：It is formed on the substrate
Dielectric layer is formed with first through hole and the annular through-hole around the first through hole, first through hole and annular in the dielectric layer
It is isolated by certain media layer between through-hole；Metal is filled in first through hole and forms the first testing needle, is filled out in annular through-hole
It fills the second metal and forms the second testing needle；Remove the dielectric layer on the outside of the second testing needle, the first testing needle and the second testing needle it
Between dielectric layer as insulating layer.
The present invention also provides a kind of forming methods of semiconductor test jig, which is characterized in that including：Substrate is provided；
Several first testing needles are formed on the substrate；Insulating layer is formed on the side wall of each first testing needle；In insulating layer
Surface forms the second testing needle, and second testing needle is around corresponding first testing needle.
Optionally, signal circuit is formed in the substrate, the signal circuit includes first input end,
One output end, the second input terminal and second output terminal, first output end are electrically connected with the first connecting pin of the first testing needle,
The second output terminal is electrically connected with the second connection end of the second testing needle, the first input end and the second input terminal respectively with
External test circuit electrical connection.
Optionally, first testing needle, insulating layer and the second testing needle forming process are：Is formed on the substrate
One metal layer；It etches the first metal layer and forms several first testing needles；It is formed and covers each first testing needle side wall and top
The insulating thin layer on portion surface；No mask etching technique etches the insulating thin layer and forms insulation in the side wall of the first testing needle
Layer；Form the second metal layer for covering the insulating layer and the first testing needle top surface；Without the second metal described in mask etching
Layer forms the second testing needle in surface of insulating layer.
Optionally, the forming process of first testing needle, insulating layer and the second testing needle is：It is formed on the substrate
Sacrificial layer has several through-holes for exposing substrate surface in the sacrificial layer；Full metal is filled in the through-hole, if being formed
Dry first testing needle；Remove the sacrificial layer；Form the insulating thin layer for covering each first testing needle side wall and top surface；
No mask etching technique etches the insulating thin layer and forms insulating layer in the side wall of the first testing needle；It is formed and covers the insulation
The second metal layer of layer and the first testing needle top surface；Without second metal layer described in mask etching, formed in surface of insulating layer
Second testing needle.
Optionally, the forming process of the first detection needle, the second detection needle and insulating layer is：It is formed on the substrate
Dielectric layer, is formed with several first through hole and the annular through-hole around each first through hole in the dielectric layer, first through hole and
It is isolated by certain media layer between annular through-hole；Metal is filled in first through hole and forms the first testing needle, in annular through-hole
Middle filling metal forms the second testing needle；Remove the dielectric layer on the outside of the second testing needle, the first testing needle and the second testing needle it
Between remaining dielectric layer as insulating layer.
Compared with prior art, technical scheme of the present invention has the following advantages：
The test syringe needle that the method for the present invention is formed, including the first testing needle, first testing needle include the first noumenon, position
The first test lead in the first noumenon one end and the first connecting pin positioned at the first noumenon other end；Cover first test
The insulating layer of the body surface of needle；Positioned at surface of insulating layer around the second testing needle of first testing needle, the second testing needle
With first test coaxial needle, the second testing needle include the second ontology, positioned at second ontology one end the second test lead and be located at
The second connection end of the second ontology other end, the second test end surfaces are flushed with the first test end surfaces.The survey of the present invention
First testing needle and the second testing needle are integrated on a test syringe needle by test point head, and the second testing needle is tested around described first
Needle uses insulator separation between the second testing needle and the first testing needle, to while ensureing that the size of testing needle is smaller, carry
Rise the mechanical strength of testing needle；On the other hand, the first testing needle and the second testing needle are coaxially to be distributed so that the first testing needle and
The precision of spacing is higher between second testing needle, improves the precision of test；In another aspect, needing compared with the prior art multiple
Testing needle (such as Double ejection pin or golden finger) could carry out electrical performance testing, and of the invention test syringe needle can carry out electricity
Learn the test of performance.
Semiconductor test jig is made by the advanced semiconductor integration making technology of technique so that each test of substrate
The size of several test syringe needles formed on region is identical with surface topography, and the spacing between adjacent test syringe needle is identical,
When the semiconductor test jig that the method for the present invention is formed is used for electrical performance testing, the precision of test is improved.
Further, be formed with signal circuit in the substrate, convenient for test signal in test process transmission and obtain
, and improve semiconductor test jig integrated level.
Description of the drawings
Fig. 1~Fig. 2 is the structural schematic diagram that the embodiment of the present invention tests syringe needle；
Fig. 3~Fig. 4 is the structural schematic diagram of semiconductor test jig of the embodiment of the present invention；
Fig. 5~Fig. 9 is the structural schematic diagram of one embodiment of the invention semiconductor test jig forming process；
Figure 10~Figure 13 is the structural schematic diagram of another embodiment of the present invention semiconductor test jig forming process.
Specific implementation mode
As described in the background art, the performance of existing thimble or golden finger is still to be improved.
For this purpose, the present invention provides a kind of coaxial test syringe needle, including the first testing needle, first testing needle includes the
One ontology, the first test lead positioned at the first noumenon one end and the first connecting pin positioned at the first noumenon other end；Covering institute
State the insulating layer of the body surface of the first testing needle；The second testing needle of first testing needle is surround positioned at surface of insulating layer,
Second testing needle and the first test coaxial needle, the second testing needle include the second ontology, the second test positioned at second ontology one end
End and positioned at the second ontology other end second connection end, it is described second test end surfaces with first test end surfaces flushes.
First testing needle and the second testing needle are integrated on a test syringe needle by the test syringe needle of the present invention, and the second testing needle is around institute
State the first testing needle, between the second testing needle and the first testing needle use insulator separation, to ensure testing needle size compared with
While small, the mechanical strength of testing needle is promoted；On the other hand, the first testing needle and the second testing needle are coaxially to be distributed so that
The precision of spacing is higher between first testing needle and the second testing needle, improves the precision of test；In another aspect, compared to existing
Technology needs multiple testing needles (such as Double ejection pin or golden finger) that could carry out electrical performance testing, of the invention testing needle
Head can carry out the test of electric property.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
In making should include length, width and depth three-dimensional space.
Fig. 1~Fig. 2 is the structural schematic diagram that the embodiment of the present invention tests syringe needle；Fig. 3~Fig. 4 is that the embodiment of the present invention is partly led
The structural schematic diagram of body measurement jig；Fig. 5~Fig. 9 is that the structure of one embodiment of the invention semiconductor test jig forming process is shown
It is intended to；Figure 10~Figure 13 is the structural schematic diagram of another embodiment of the present invention semiconductor test jig forming process.
Referring to FIG. 1, test syringe needle 20 is provided in one embodiment of the invention, including：
First testing needle 201, first testing needle 201 include the first noumenon, are surveyed positioned at the first of the first noumenon one end
Try end 21 and the first connecting pin 22 positioned at the first noumenon other end；
Cover the insulating layer 202 on the first noumenon surface of first testing needle 201；
Positioned at 202 surface loop of insulating layer around the second testing needle 203 of first testing needle 201, the second testing needle 203 with
First testing needle 201 is coaxial, the second testing needle 203 include the second ontology, positioned at second ontology one end the second test lead 23 with
And the second connection end 24 positioned at the second ontology other end, 23 surface of the second test lead and 31 surface of the first test lead are neat
It is flat.
Incorporated by reference to being cross-sectional views of the Fig. 1 along the directions hatching AB with reference to figure 1 and Fig. 2, Fig. 2, described first surveys
The shape of test point 201 is cylinder, and the section shape of corresponding first testing needle 201 is circle, the section of the insulating layer 202
Shape is circular ring shape, and the section shape of second testing needle 203 is circular ring shape.It should be noted that first testing needle
Section shape can be other shapes, for example the section shape of first testing needle can be regular polygon, such as just
Triangle, square.
The test syringe needle of the present invention is formed by semiconductor integration making technology, thus the first testing needle 201 formed
Diameter can be smaller, and in one embodiment, a diameter of 100 nanometers~500 microns of first testing needle 201, can be 200
Nanometer~50 microns.
The width of the corresponding insulating layer 202 and the width of the second testing needle 203 can also very little, in an embodiment
In, the width of the insulating layer 202 is 80 nanometers~400 microns, can be 100 nanometers~10 microns, second testing needle
203 width is 60 nanometers~300 microns, can be 90 nanometers~25 microns.
It should be noted that in other embodiments of the invention, diameter, the insulating layer 202 of first testing needle 201
Thickness and the thickness of third testing needle 203 can be other numerical value.
The material of first testing needle, 201 and second testing needle 203 be copper, gold, tungsten or alloy material or other
Suitable metal material or metal compound material.
The insulating layer 202 is for the electric isolation between the first testing needle 201 and the second testing needle 203, the present embodiment
In, the top surface (the first test lead 21) of the top surface of the insulating layer 202 and the first testing needle 201 and the second testing needle
203 top surface (the second test lead 23) flushes, i.e., so that the first test lead 21 and the second testing needle of the first testing needle 201
There is no gap between 203 the second test lead 23, in test, prevents the first test lead 21 or the of the first testing needle 201
Second test lead 23 of two testing needles 203 thus between there are gaps to deform under external stress, and make the
The second test lead 23 electrical contact of the first test lead 21 and the second testing needle 203 of one testing needle 201, to influence the essence of test
Degree.
The insulating layer 202 can be single-layer or multi-layer (>=2 layers) stacked structure.
The material of the insulating layer 202 can be insulating dielectric materials, such as silica, silicon nitride, silicon oxynitride, nitrogen carbon
One or more of SiClx, fire sand, the material of the insulating layer can also be resin material, for example, epoxy resin, poly-
Imide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
In one embodiment, from the direction for being directed toward the second test lead 23 far from the second test lead 23, second testing needle
The width of 203 part body is gradually reduced.It is specific referring to FIG. 1, the part body of second testing needle 203 width,
It is smaller closer to second test lead 23 its width, will be mostly with testing needle 20 for when testing so that adjacent test syringe needle 20
The distance between test lead increases.
First testing needle 201 and the second testing needle 203 are integrated in a test by the test syringe needle 20 of the embodiment of the present invention
On syringe needle, the second testing needle 203 is used around first testing needle 201 between second testing needle 203 and the first testing needle 201
Insulating layer 202 is isolated, to while ensureing that the size of testing needle is smaller, promote the mechanical strength of testing needle；On the other hand,
First testing needle 201 and the second testing needle 203 are coaxially to be distributed so that between the first testing needle 201 and the second testing needle 203
Away from precision it is higher, and the spacing between the first testing needle 201 and the second testing needle 203 will not change during the test
Become, improves the precision of test；In another aspect, needing multiple testing needles (such as Double ejection pin or golden finger) compared with the prior art
Electrical performance testing could be carried out, the embodiment of the present invention is integrated in a survey due to the first testing needle 201 and the second testing needle 203
On test point head, using because one test syringe needle of the embodiment of the present invention can carry out the test of electric property.
When the test syringe needle 20 that will apply the present invention carries out electrical performance testing, in one embodiment, this can be sent out
Bright test syringe needle is applied to resistance test or high-current test, and the one end for testing syringe needle 20 and tested termination contact make
The table of first test lead 21 of the first testing needle 201 and the second test lead 23 surface and tested terminal of the second testing needle 203
Face contacts, and applies test voltage between the first testing needle 201 and the second testing needle 202, measures and passes through the first testing needle
201, the electric current on the second testing needle 203 and tested terminal, and pass through test voltage divided by electric current obtains test electricity
Resistance.
When carrying out the test of resistance using the test syringe needle 20 of the present invention, due to the first testing needle 201 and the second testing needle
203 be coaxial, thus tests electric current and uniformly spread around by the first testing needle 201, flows to the second testing needle 203,
I.e. so that the annular region of the terminal to be tested between the first testing needle 201 and the second testing needle 203 (is contacted with insulating layer 202
Part) on the electric current that flows through of different directions be average, improve the precision of test.
In other embodiments of the invention, the test syringe needle of the present invention can be applied to the electric property of other forms
Test, for example the test of multiple test syringe needle progress electric properties can be applied, for example test electric current can be from a testing needle
The first testing needle or the second testing needle of head flow to the first testing needle or the second testing needle of another test syringe needle, or test
The second testing needle and the second testing needle that circuit can test syringe needle from one flow to the first testing needle of another test syringe needle
With the second testing needle.
A kind of semiconductor test jig is additionally provided in the embodiment of the present invention, referring to FIG. 3, the measurement jig includes：
Substrate 200；Several test syringe needles 20 in substrate 200.
The restriction or description of the test syringe needle 20 please refer to restriction or description previously with regard to test syringe needle 20, herein not
It repeats again.
The quantity of the test syringe needle 20 is more than or equal to two, and in a specific embodiment, the test syringe needle 20 exists
It arranges in ranks in substrate 200.
It is formed with signal circuit in the substrate 200, the signal circuit includes first input end, first defeated
Outlet, the second input terminal and second output terminal, first output end are electrically connected with the first connecting pin of the first testing needle 201,
The second output terminal is electrically connected with the second connection end of the second testing needle 203, the first input end and the second input terminal point
It is not electrically connected with external test circuit.For the test circuit for providing test signal, the signal circuit is used for will
The test signal that test circuit generates is transmitted to the first testing needle 201 and the second testing needle 203, and will be obtained in test process
Electric signal transmission to test circuit, test circuit handles the electric signal of reception, obtains test parameter.
Material PCB resins of the substrate 200 etc., the first input end and the first output end are intrabasement by being located at
First metal wire is electrically connected, and second input terminal and second output terminal are electrically connected by being located at intrabasement second metal wire.
In one embodiment, the substrate 200 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, several first output ends and second output terminal are located at the front of substrate 200, with the first testing needle and the second testing needle
Position correspond to, several first input ends and the second input terminal can concentrate on the interface area at 200 back side of substrate so that several
First input end and the second input terminal can be connected by one or more interfaces with external test circuit, and semiconductor is simplified
Interface circuit between measurement jig and the test circuit of outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes several interconnection structures, and each interconnection structure includes
It is connected with through-hole interconnection structure through the through-hole interconnection structure of the PCB resin substrates and on PCB resin substrates surface
Metal layer, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And several first input ends and the second input terminal is allow to concentrate on the interface area at 200 back side of substrate.
In another embodiment, the substrate 200 includes front and the back side opposite with front, the back side packet of the substrate
Include interface area, several first output ends and second output terminal are located at the front of substrate 200, several first input ends and second defeated
First through hole interconnection structure and the through substrate 200 can be formed positioned at the back side of substrate 200, in the substrate 200 by entering end
Two through-hole interconnection structures, the first input end and the first output end pass through the first through hole interconnection structure in substrate 200
Electrical connection, second input terminal and second output terminal are electrically connected by the second through-hole interconnection structure in substrate 200；Institute
Stating on the back side of substrate 200 also has the several first interconnection metal layer and the second interconnection metal layers again again, and described first connects up again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces with it is external
Test circuit is connected.
In other embodiments, test circuit (not shown), the test electricity are could be formed in the substrate 200
Road includes the first signal end and second signal end, and the first signal end is electrically connected with the first connecting pin of the first testing needle 201, and second
Signal end is electrically connected with the second connection end of the second testing needle 203.The test circuit is when being tested, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).In one embodiment, the substrate 200 includes
Semiconductor substrate (such as silicon substrate or substrate etc.) and the dielectric layer in semiconductor substrate are formed in the semiconductor substrate
There is a semiconductor devices (such as transistor etc.), forms metal interconnecting wires and passive device (such as resistance, capacitance in the dielectric layer
Deng), semiconductor devices and passive device are connected and composed test circuit, the first signal end and second signal by the metal interconnecting wires
End can be drawn by the first metal wire being electrically connected with test circuit in dielectric layer and the second metal wire.
With reference to figure 4, Fig. 4 is structural schematic diagram when semiconductor test jig of the invention is used for electrical performance testing, first
First semiconductor test jig is placed in tester table；Then encapsulating structure 300 to be tested is placed on semiconductor test jig,
There are several tested terminals 31, the tested terminal 31 can be pin or weldering on the encapsulating structure to be tested 300
Disk etc., (test lead is the first testing needle to the part surface of the tested terminal 31 with the test lead of corresponding test syringe needle 20
Second test lead of 201 the first test lead and the second testing needle 203) electrical connection；Then it is surveyed in the first testing needle 201 and second
Apply test signal between test point 203, carries out the test of electric property.
Semiconductor test jig through the invention can be carried out at the same time electricity to multiple tested terminals of encapsulating structure 300
Performance test is learned, the efficiency of test and the accuracy of test are improved.
It should be noted that the semiconductor test jig of the present invention can be applied to manual test and (manually load to be tested
Encapsulating structure) automatic test can also be applied to (mechanical hand loads encapsulating structure to be tested automatically).
The embodiment of the present invention additionally provide it is a kind of formed aforesaid semiconductor measurement jig method, specifically please refer to Fig. 5~
Fig. 9.
Referring to FIG. 5, providing substrate 200；Several first testing needles 201 are formed in the substrate 200.
It is formed with signal circuit in the substrate 200, the signal circuit includes first input end, first defeated
Outlet, the second input terminal and second output terminal, first output end are electrically connected with the first connecting pin of the first testing needle 201,
The second output terminal is electrically connected with the second connection end of the second testing needle 203, the first input end and the second input terminal point
It is not electrically connected with external test circuit.For the test circuit for providing test signal, the signal circuit is used for will
The test signal that test circuit generates is transmitted to the first testing needle 201 and the second testing needle 203, and will be obtained in test process
Electric signal transmission to test circuit, test circuit handles the electric signal of reception, obtains test parameter.
Material PCB resins of the substrate 200 etc., the first input end and the first output end are intrabasement by being located at
First metal wire is electrically connected, and second input terminal and second output terminal are electrically connected by being located at intrabasement second metal wire.
In one embodiment, the substrate 200 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, several first output ends and second output terminal are located at the front of substrate 200, with the first testing needle and the second testing needle
Position correspond to, several first input ends and the second input terminal can concentrate on the interface area at 200 back side of substrate so that several
First input end and the second input terminal can be connected by one or more interfaces with external test circuit, and semiconductor is simplified
Interface circuit between measurement jig and the test circuit of outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes several interconnection structures, and each interconnection structure includes
It is connected with through-hole interconnection structure through the through-hole interconnection structure of the PCB resin substrates and on PCB resin substrates surface
Metal layer, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And several first input ends and the second input terminal is allow to concentrate on the interface area at 200 back side of substrate.
In another embodiment, the substrate 200 includes front and the back side opposite with front, the back side packet of the substrate
Include interface area, several first output ends and second output terminal are located at the front of substrate 200, several first input ends and second defeated
First through hole interconnection structure and the through substrate 200 can be formed positioned at the back side of substrate 200, in the substrate 200 by entering end
Two through-hole interconnection structures, the first input end and the first output end pass through the first through hole interconnection structure in substrate 200
Electrical connection, second input terminal and second output terminal are electrically connected by the second through-hole interconnection structure in substrate 200；Institute
Stating on the back side of substrate 200 also has the several first interconnection metal layer and the second interconnection metal layers again again, and described first connects up again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces with it is external
Test circuit is connected.
In other embodiments, test circuit (not shown), the test electricity are could be formed in the substrate 200
Road includes the first signal end and second signal end, and the first signal end is electrically connected with the first connecting pin of the first testing needle 201, and second
Signal end is electrically connected with the second connection end of the second testing needle 203.The test circuit is when being tested, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).
First testing needle 201 is cylinder, and the first testing needle 201 is obtained along the direction for being parallel to 200 surface of substrate
Section shape be circle, a diameter of 500 nanometers~500 microns of first testing needle 201, formed in the substrate 200
The first testing needle 201 quantity be more than or equal to 2, in the present embodiment, to form 3 the first testing needles 201 on a substrate 200
As example.
It should be noted that the section shape of first testing needle can be other shapes, for example described first surveys
The shape of test point is regular polygon, such as equilateral triangle, square.
In one embodiment, the forming process of first testing needle 201 is：The first gold medal is formed in the substrate 200
Belong to layer (not shown)；Patterned mask layer is formed on the first metal layer；Using the patterned mask layer as mask,
It etches the first metal layer and forms several first testing needles 201；Remove the patterned mask layer.
In another embodiment, the forming process of first testing needle 201 is：It is formed and is sacrificed in the substrate 200
Layer (not shown), has several through-holes for exposing 200 surface of substrate in the sacrificial layer；It is filled in the through-hole full
The first metal layer forms several first testing needles；Remove the sacrificial layer.
In the through-hole fill the first metal layer technique be electroplating technology, in through-holes fill the first metal layer it
Before, further include：Conductive layer is formed in the side wall of the through-hole and bottom and the surface of sacrificial layer, the conductive layer is as plating
Cathode when technique.
The material of the conductive layer is one or more of Ti, Ta, TiN, TaN etc., and conductive layer can be single layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer packet of the double stacked structure
Ti layers and the TiN layer on Ti layers are included, or the TaN layers being located on Ta layers including Ta layers.
The thickness of the conductive layer is less than the radius of through-hole, and in one embodiment, the thickness of the conductive layer is 50~200
The formation process of nanometer, conductive layer is sputtering.
After forming conductive layer, electroplating technology is carried out, forms the first metal layer layer, the first metal layer is located at conductive layer
Through-hole is gone up and filled, after carrying out electroplating technology, further includes：Chemical mechanical milling tech is carried out, the of sacrificial layer surface is removed
One metal layer and conductive layer, form the first testing needle 201, and the first testing needle 201 includes the first metal layer and encirclement described first
The non-proliferation barrier layer of metal layer, the non-proliferation barrier layer is made of remaining conductive layer after chemical mechanical grinding, for preventing
Only the metal in metal layer is spread into the insulating layer being subsequently formed.
The material of the first metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
The surface (bottom surface) that first testing needle 201 is contacted with 200 surface of substrate is the first connecting pin, and first surveys
The surface (top surface) opposite with the first connecting pin of test point 201 is the first test lead.
In conjunction with reference to figure 6 and Fig. 7, insulating layer 202 is formed on the side wall of each first testing needle 201.
The forming process of the insulating layer 202 is：It is formed and covers the exhausted of each first testing needle, 201 side wall and top surface
Edge film layer 204；No mask etching technique etches the insulating thin layer 204 and forms insulation in the side wall of the first testing needle 201
Layer 202.
The thickness of the insulating layer 202 is 80 nanometers~400 microns, and the material of the insulating layer 202 can be that insulation is situated between
One or more of material, such as silica, silicon nitride, silicon oxynitride, fire sand, fire sand.
The insulating layer 202 can be single-layer or multi-layer (>=2 layers) stacked structure.
The no mask etching technique is anisotropic plasma etching industrial, in one embodiment, the plasma
The etching gas that etching technics uses is specifically as follows CF for fluorine-containing and carbon gas4、C2F6、C4F8、CHF3、CH2F2In one
Kind is several, and source power is 500~1000W, and bias power is 0~100W, and etching cavity pressure is 2~500mtorr.
In the present embodiment, the insulating layer 202 is the silicon oxide layer of single layer,
In other embodiments of the invention, the material of the insulating layer 202 can also be resin material, the resinous wood
Material can be epoxy resin, polyimide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
The formation process of the insulating layer 202 is screen printing technique etc..
In conjunction with reference to figure 8 and Fig. 9, the second testing needle 203, second testing needle 203 are formed on the surface of insulating layer 202
Around corresponding first testing needle 201.
The forming process of second testing needle 203 is：It is formed and covers 202 and first testing needle 201 of the insulating layer top
The second metal layer 205 on portion surface；Without second metal layer 205 described in mask etching, the second test is formed on 202 surface of insulating layer
Needle 203.
The formation process of the second metal layer 205 is sputtering, and 205 material of second metal layer is copper, gold, tungsten or alloy
The thickness of material or other suitable metal materials, second metal layer 205 is 60 nanometers~300 microns.
The technique of second metal layer 205 described in no mask etching is anisotropic plasma etching industrial, is implemented one
In example, the etching gas that the plasma etching industrial uses is SF6、NF3、Cl2, one or more of HBr, source power is
500~1500W, bias power are 0~100W, and etching cavity pressure is 10~500mtorr.
Each first testing needle 201 constitutes a test syringe needle with corresponding insulating layer 202 and the second testing needle 203.
Another embodiment of the present invention additionally provides a kind of method forming aforesaid semiconductor measurement jig, specifically please refers to figure
10~Figure 13.
Referring to FIG. 10, providing substrate 200；Dielectric layer 207 is formed in the substrate 200, is stated and is formed in dielectric layer 207
There are several first through hole 208 and the annular through-hole 209 around each first through hole 208, first through hole 208 and annular through-hole 209
Between be isolated by certain media layer.
The first through hole 208 and annular through-hole 209 expose the surface of substrate 200, follow-up in the first through hole 208
It fills metal and forms the first testing needle, metal is subsequently filled in second through-hole and forms the second testing needle.
Signal circuit or test circuit are formed in the substrate 200, about signal circuit or test circuit
Description please refers to previous embodiment, and details are not described herein.
With reference to figure 11, Figure 11 is the overlooking structure diagram of part-structure in Figure 10, and the first through hole 208 is circle,
Annular through-hole 209 is circular ring shape, annular through-hole 209 around the first through hole 208, first through hole 208 and annular through-hole 209 it
Between be isolated by certain media layer material.
In other embodiments of the invention, the shape of the first through hole can be other shapes, for example can be
Regular polygon is specifically as follows equilateral triangle, square etc..
In one embodiment, the material of the dielectric layer 207 is insulating dielectric materials, such as silica, silicon nitride, nitrogen oxygen
One or more of SiClx, fire sand, fire sand form medium on a substrate 200 by chemical gaseous phase deposition technique
Layer 207, then forms patterned photoresist layer on the dielectric layer 207, using the patterned photoresist layer as mask,
The dielectric layer 207 is etched, forms several first through hole 208 and the annular around each first through hole 208 in dielectric layer 207
Through-hole 209；After forming the annular through-hole 209 of first through hole 208, the patterned photoresist layer is removed.
In another embodiment, the material of the dielectric layer 207 is resin glue, and the resin glue is epoxide-resin glue, gathers
Imide resin glue, polyvinyl adhesive, benzocyclobutene resin glue or polybenzoxazoles resin glue, by dry film process, wet
Membrane process, printing technology or plastic roll technique form dielectric layer 207 in the substrate 200；Then pass through exposed and developed technique
Several first through hole 208 and the annular through-hole 209 around each first through hole 208 are formed in the dielectric layer, simplify work
Skill step, formation process are simple.
With reference to figure 12, filling metal forms the first testing needle 201 in first through hole 208 (with reference to figure 10), logical in annular
Filling metal forms the second testing needle 203 in hole 209 (with reference to figure 10).
First testing needle, 201 and second testing needle 203 is formed by same processing step.
The technique that metal is filled in first through hole 208 and annular through-hole 209 is electroplating technology, in 208 He of first through hole
Before filling metal in annular through-hole 209, further include：The first through hole 208 and annular through-hole 209 side wall and bottom with
And the surface of sacrificial layer forms conductive layer, the cathode when conductive layer is as electroplating technology.
The material of the conductive layer is one or more of Ti, Ta, TiN, TaN etc., and conductive layer can be single layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer packet of the double stacked structure
Ti layers and the TiN layer on Ti layers are included, or the TaN layers being located on Ta layers including Ta layers.
The thickness of the conductive layer is less than smaller in both the radius of first through hole 208 and the radius of annular through-hole 209
Radius value, the formation process of conductive layer is sputtering.
After forming conductive layer, electroplating technology is carried out, forms metal layer, the metal layer is located on conductive layer and fills the
One through-hole 208 and annular through-hole 209 further include after carrying out electroplating technology：Chemical mechanical milling tech is carried out, medium is removed
The metal layer and conductive layer on 207 surface of layer, form the first testing needle 201 and the second testing needle 203, the first testing needle 201 and the
Two testing needles 203 include metal layer and surround the non-proliferation barrier layer of the metal layer, and the non-proliferation barrier layer is chemistry
Remaining conductive layer is constituted after mechanical lapping, for preventing the metal in metal layer from being spread into the insulating layer being subsequently formed.
The material of the metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
The first testing needle 201 and the second testing needle 203, the first testing needle are formed simultaneously by electroplating technology in the present embodiment
201 and second testing needle 203 will not be by the damage etched so that the surface shape of the first testing needle 201 and the second testing needle 203
Looks are preferable.
With reference to figure 13, the dielectric layer 207 (with reference to figure 12) in 203 outside of the second testing needle of removal exposes the second testing needle
203 sidewall surfaces, remaining dielectric layer is as insulating layer 202 between the first testing needle 201 and the second testing needle 203.
Before the dielectric layer 207 for removing 203 outside of the second testing needle, tested in first testing needle 201 and second
Photoresist mask layer is formed on dielectric layer between needle 203 and the first testing needle 201 and the second testing needle 203；Then with institute
It is mask, the dielectric layer 207 in 203 outside of the second testing needle of etching removal to state photoresist.
207 technique of dielectric layer in 203 outside of the second testing needle of etching removal can be wet etching or dry etch process.
A kind of method forming aforementioned test syringe needle is additionally provided in another embodiment of the present invention, including：
Substrate is provided；
The first testing needle is formed on the substrate；
Insulating layer is formed on the side wall of the first testing needle；
The second testing needle is formed on the surface of insulating layer, second testing needle is around first testing needle.
In one embodiment, the forming process of first testing needle is：The first metal layer is formed on the substrate；It carves
It loses the first metal layer and forms the first testing needle.
In another embodiment, the forming process of first testing needle is：Sacrificial layer is formed on the substrate, it is described
There is the through-hole for exposing substrate surface in sacrificial layer；Full metal is filled in the through-hole, forms the first testing needle；Removal institute
State sacrificial layer.
In one embodiment, the forming process of the insulating layer and the second testing needle is：Form covering first test
The insulating thin layer of needle side wall and top surface；No mask etching technique etches the insulating thin layer in the side of the first testing needle
Wall forms insulating layer；Form the second metal layer for covering the insulating layer and the first testing needle top surface；Without mask etching institute
Second metal layer is stated, the second testing needle is formed in surface of insulating layer.
In another embodiment, the forming process of the first detection needle, the second detection needle and insulating layer is：In the base
Dielectric layer is formed on bottom, first through hole and the annular through-hole around the first through hole are formed in the dielectric layer, and first is logical
It is isolated by certain media layer between hole and annular through-hole；Metal is filled in first through hole and forms the first testing needle, in annular
The second metal is filled in through-hole forms the second testing needle；Remove the dielectric layer on the outside of the second testing needle, the first testing needle and second
Dielectric layer between testing needle is as insulating layer.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (3)
1. a kind of forming method of test syringe needle, which is characterized in that including：
Substrate is provided；
The first testing needle is formed on the substrate；
Insulating layer is formed on the side wall of the first testing needle；
The second testing needle is formed on the surface of insulating layer, second testing needle is around first testing needle；
Wherein, the test syringe needle is made by semiconductor integrated technique, including scheme a, scheme b and scheme c：
Scheme a, the process that test syringe needle is made by semiconductor integrated technique include：The first metal is formed on the substrate
Layer；It etches the first metal layer and forms the first testing needle；It is formed and covers the exhausted of the first testing needle side wall and top surface
Edge film layer；No mask etching technique etches the insulating thin layer and forms insulating layer in the side wall of the first testing needle；Formation is covered
Cover the second metal layer of the insulating layer and the first testing needle top surface；Without second metal layer described in mask etching, insulating
Layer surface forms the second testing needle；
Scheme b, the process that test syringe needle is made by semiconductor integrated technique include：Sacrificial layer is formed on the substrate, institute
State the through-hole for having in sacrificial layer and exposing substrate surface；Full the first metal layer is filled in the through-hole, forms the first test
Needle；Remove the sacrificial layer；Form the insulating thin layer for covering the first testing needle side wall and top surface；Without mask etching
Technique etches the insulating thin layer and forms insulating layer in the side wall of the first testing needle；It is formed and covers the insulating layer and the first survey
The second metal layer of test point top surface；Without second metal layer described in mask etching, the second testing needle is formed in surface of insulating layer；
Scheme c, the process that test syringe needle is made by semiconductor integrated technique include：Dielectric layer is formed on the substrate, institute
It states and is formed with first through hole and the annular through-hole around the first through hole in dielectric layer, lead between first through hole and annular through-hole
Cross the isolation of certain media layer；Metal is filled in first through hole and forms the first testing needle, and the second metal is filled in annular through-hole
Form the second testing needle；Remove the dielectric layer on the outside of the second testing needle, the dielectric layer between the first testing needle and the second testing needle
As insulating layer.
2. a kind of forming method of the semiconductor test jig with several test syringe needles, which is characterized in that including：
Substrate is provided；
Several first testing needles are formed on the substrate；
Insulating layer is formed on the side wall of each first testing needle；
The second testing needle is formed on the surface of insulating layer, second testing needle is around corresponding first testing needle；
Wherein, several test syringe needles are made by semiconductor integrated technique, including scheme a, scheme b and scheme c：
Scheme a, the process that several test syringe needles are made by semiconductor integrated technique include：The first gold medal is formed on the substrate
Belong to layer；It etches the first metal layer and forms several first testing needles；It is formed and covers each first testing needle side wall and top table
The insulating thin layer in face；No mask etching technique etches the insulating thin layer and forms insulating layer in the side wall of the first testing needle；
Form the second metal layer for covering the insulating layer and the first testing needle top surface；Without second metal layer described in mask etching,
The second testing needle is formed in surface of insulating layer；
Scheme b, the process that several test syringe needles are made by semiconductor integrated technique include：It is formed and is sacrificed on the substrate
Layer, there are several through-holes for exposing substrate surface in the sacrificial layer；Full metal is filled in the through-hole, forms several the
One testing needle；Remove the sacrificial layer；Form the insulating thin layer for covering each first testing needle side wall and top surface；Nothing is covered
Film etching technics etches the insulating thin layer and forms insulating layer in the side wall of the first testing needle；Formed cover the insulating layer and
The second metal layer of first testing needle top surface；Without second metal layer described in mask etching, second is formed in surface of insulating layer
Testing needle；
Scheme c, the process that several test syringe needles are made by semiconductor integrated technique include：Medium is formed on the substrate
Layer, several first through hole and the annular through-hole around each first through hole, first through hole and annular are formed in the dielectric layer
It is isolated by certain media layer between through-hole；Metal is filled in first through hole and forms the first testing needle, is filled out in annular through-hole
It fills metal and forms the second testing needle；The dielectric layer on the outside of the second testing needle is removed, is remained between the first testing needle and the second testing needle
Remaining dielectric layer is as insulating layer.
3. the forming method of semiconductor test jig as claimed in claim 2, which is characterized in that be formed with letter in the substrate
Number transmission circuit, the signal circuit include first input end, the first output end, the second input terminal and second output terminal,
First output end is electrically connected with the first connecting pin of the first testing needle, the second output terminal and the second of the second testing needle
Connecting pin is electrically connected, and the first input end and the second input terminal are electrically connected with external test circuit respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410606939.2A CN104407183B (en) | 2014-10-30 | 2014-10-30 | Test the forming method of syringe needle and semiconductor test jig |
| US14/927,642 US10067162B2 (en) | 2014-10-30 | 2015-10-30 | Testing probe, semiconductor testing fixture and fabrication method thereof |
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| CN201410606939.2A CN104407183B (en) | 2014-10-30 | 2014-10-30 | Test the forming method of syringe needle and semiconductor test jig |
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| CN104407183B true CN104407183B (en) | 2018-10-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1936595A (en) * | 2006-09-05 | 2007-03-28 | 杭州高特电子设备有限公司 | Coaxial multi-detection-point detecting rod |
| CN201654080U (en) * | 2010-01-05 | 2010-11-24 | 诺亚电子股份有限公司 | Improved detecting probe structure |
| CN101957389A (en) * | 2009-07-13 | 2011-01-26 | 巧橡科技有限公司 | Test device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008205042A (en) * | 2007-02-16 | 2008-09-04 | Renesas Technology Corp | Manufacturing method of semiconductor integrated circuit device |
| JP5386769B2 (en) * | 2008-09-29 | 2014-01-15 | 日本電産リード株式会社 | Inspection jig |
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2014
- 2014-10-30 CN CN201410606939.2A patent/CN104407183B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1936595A (en) * | 2006-09-05 | 2007-03-28 | 杭州高特电子设备有限公司 | Coaxial multi-detection-point detecting rod |
| CN101957389A (en) * | 2009-07-13 | 2011-01-26 | 巧橡科技有限公司 | Test device and manufacturing method thereof |
| CN201654080U (en) * | 2010-01-05 | 2010-11-24 | 诺亚电子股份有限公司 | Improved detecting probe structure |
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