CN104752405B - Test structure of semiconductor devices and forming method thereof - Google Patents
Test structure of semiconductor devices and forming method thereof Download PDFInfo
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- CN104752405B CN104752405B CN201310739680.4A CN201310739680A CN104752405B CN 104752405 B CN104752405 B CN 104752405B CN 201310739680 A CN201310739680 A CN 201310739680A CN 104752405 B CN104752405 B CN 104752405B
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Abstract
The present invention provides a kind of test structure of semiconductor devices and forming method thereof.The test structure includes：First semiconductor device structure, including：More metal layers spaced apart from each other in dielectric layer, there is the first connector between adjacent two metal layers；And test cell, in the dielectric layer of the first semiconductor device structure side, the test cell spaced a predetermined distance, the electrology characteristic of the dielectric layer of the multiple layer metal interlayer of first semiconductor device structure is corresponded to for acquisition with first semiconductor device structure.The fracture of low K dielectric layer or ultra-low K dielectric layer or lamination caused by the test structure of semiconductor devices provided by the invention can detect stress accumulation.
Description
Technical field
The present invention relates to semiconductor test technical field, the test structure of more particularly to a kind of semiconductor devices and its formation
Method.
Background technology
At present, in the chip of integrated circuit frequently with low-K material or ultra low-K material as interlayer dielectric, to reduce
Distribution capacity between interconnection line, signal cross-talk is reduced, shorten signal propagation delay, improve the overall performance of chip.It is however, low
K materials and ultra low-K material thermal characteristics and mechanical properties, it is weaker with the bonding force of metal level, and mechanical strength is weaker.When cutting
When cutting chip, the layering or stripping of serious metal level and interlayer dielectric layer occurs in chip edge；The meeting in wire bonding process
There is disconnected weldering, weak weldering or the stripping of metal level and interlayer dielectric layer, so as to cause integrated circuit electrical property failure.Therefore, it is necessary to right
The manufacturing process of the semiconductor devices is monitored.
The content of the invention
The present invention program solves the problems, such as to be to provide a kind of test structure of semiconductor devices and forming method thereof, Neng Goujian
The fracture of low-K material or lamination caused by stress accumulation in semiconductor devices are controlled, can so as to improve semiconductor devices
By property.
To solve the above problems, technical solution of the present invention provides a kind of test structure of semiconductor devices, including：First
Semiconductor device structure, including：More metal layers spaced apart from each other in dielectric layer, have between adjacent two metal layers
There is the first connector；And test cell, in the dielectric layer of the side of first semiconductor device structure, the survey
Try unit and first semiconductor device structure spaced a predetermined distance, the test cell, which is used to obtain, corresponds to described first
The electrology characteristic of the dielectric layer of the multiple layer metal interlayer of semiconductor device structure.
Alternatively, the test cell includes multi-layer testing layer, the multi-layer testing layer and first semiconductor devices
Some or all of metal level is corresponding in structure, and the multi-layer testing interlayer is formed with the second connector.
Alternatively, the opposite side of the test cell has the second semiconductor device structure, second semiconductor devices
Structure and the first semiconductor device structure are identical in structure.
Alternatively, first semiconductor devices is symmetrically distributed in the test list with second semiconductor device structure
First both sides.
Alternatively, at least two layers one layer of gold with first semiconductor device structure respectively in the multi-layer testing layer
Category layer is electrically connected, electrically connected with the layer of metal layer of second semiconductor device structure.
Alternatively, the test cell also includes the first test lead and the second test lead, and first test lead is used to connect
Power end is connect, second test lead is used to be grounded, in first test lead and the second test lead and the multi-layer testing layer
Two layers respectively correspond to electrical connection.
Alternatively, the preset distance between the semiconductor device structure and the test cell is more than minimal design chi
It is very little.
Alternatively, the semiconductor device structure determines according to the semiconductor device structure of reality.
Alternatively, the material of the dielectric layer is low K or ultra low-K material.
Present invention also offers a kind of forming method of the test structure of semiconductor devices, including：
Form dielectric layer；More metal layers are formed in the dielectric layer；Formed between adjacent two metal layers more
Individual first connector, the more metal layers and the multiple first connector form the first semiconductor device structure；And described
In dielectric layer, the side of first semiconductor device structure form test cell, the test cell is led with described the first half
Body device architecture spaced a predetermined distance, Jie of the multiple layer metal interlayer of first semiconductor device structure is corresponded to for test
The electrology characteristic of matter layer.
Alternatively, the formation test cell, which is included in the dielectric layer, forms multi-layer testing layer and in the multilayer
Test interlayer and form the second connector, the multi-layer testing layer and some or all of metal in first semiconductor device structure
Layer is corresponding.
Alternatively, the forming method of the test structure of the semiconductor devices also includes：In the dielectric layer, the survey
The opposite side for trying unit forms the second semiconductor device structure, second semiconductor device structure and the first junction of semiconductor device
Structure is identical in structure.
Alternatively, first semiconductor devices is symmetrically distributed in the test list with second semiconductor device structure
First both sides.
Alternatively, at least two layers one layer of gold with first semiconductor device structure respectively in the multi-layer testing layer
Category layer is electrically connected, electrically connected with the layer of metal layer of second semiconductor device structure.
Alternatively, the forming method of the test structure of the semiconductor devices also includes：Formed and test cell electricity
The first test lead and the second test lead of connection, first test lead are used to connect power end, and second test lead is used for
Ground connection, first test lead and the second test lead and the corresponding electrical connection respectively of two layers in the multi-layer testing layer.
Alternatively, the preset distance between the semiconductor device structure and the test cell is more than minimal design chi
It is very little.
Alternatively, the semiconductor device structure determines according to the semiconductor device structure of reality.
Alternatively, the material of the dielectric layer is low K or ultra low-K material.
Technical scheme has advantages below：
The test structure of the semiconductor devices includes semiconductor device structure and test cell, and the test cell is located at
In the dielectric layer of the semiconductor device structure, by measuring the electrical parameter between two layers of test layer, it can be determined that around
In the case of semiconductor device structure being present, the two layer medium layer whether there is fracture or lamination, therefore in the survey
Semiconductor device structure is introduced in examination structure, the dielectric layer electricity measured by test cell in corresponding semiconductor device structure is special
Property, the characteristic of actual semiconductor device can be reflected.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the test structure for the semiconductor devices that one embodiment of the present of invention provides；
Fig. 2 is the top view of the test structure of the semiconductor devices shown in Fig. 1；
Fig. 3 is the cross-sectional view of the test structure for the semiconductor devices that one embodiment of the present of invention provides；
Fig. 4 is the cross-sectional view of the test structure for the semiconductor devices that one embodiment of the present of invention provides；With
And
Fig. 5 to Figure 10 is cuing open for the forming method of the test structure for the semiconductor devices that one embodiment of the present of invention provides
Face structural representation.
Embodiment
The embodiments of the invention provide a kind of test structure of semiconductor devices and forming method thereof, the test structure bag
Semiconductor device structure and test cell are included, the semiconductor device structure includes the multilayer spaced apart from each other being located in dielectric layer
Metal level, there is the first connector between adjacent two metal layers, the test cell is located at first junction of semiconductor device
In the dielectric layer of the side of structure, the test cell spaced a predetermined distance, is used for first semiconductor device structure
Obtain the electrology characteristic of the dielectric layer of the multiple layer metal interlayer corresponding to first semiconductor device structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, and it should not be limited the scope of the invention herein.In addition, in reality
The three-dimensional space of length, width and depth should be included in making.
Fig. 1 be one embodiment of the present of invention provide semiconductor devices test structure cross-sectional view, Fig. 2
It is the top view of the test structure of the semiconductor devices shown in Fig. 1.
In semiconductor processing, in order to improve the yield of semiconductor devices, before the actual semiconductor devices of manufacture, meeting
Some test structures are additionally manufactured to monitor semiconductor technology, the embodiment of the present invention is just related to such a test structure.
With reference to Fig. 1 and Fig. 2, the test structure of the semiconductor devices includes：Semiconductor device structure 11 and test cell
12.The semiconductor device structure 11 includes：Four layers of metal level 111 in dielectric layer 112, adjacent two metal layers
There are multiple first conductive plungers 113 between 111.The test cell 12 is located at the side of the semiconductor device structure 11.
The test layer of the test cell 12 is corresponding with all or part of metal level of the semiconductor device structure 11, i.e., described survey
The all or part of material for the metal level 111 for making the semiconductor device structure 11 can be used by trying the test layer of unit 12
Film layer makes.In the present embodiment, the first test layer 121 that the test cell 12 includes being located in the dielectric layer 112, the
Two conductive plungers 122 and the second test layer 123, first test layer 121 and second test layer 123 pass through described the
Two conductive plungers 122 electrically connect.The semiconductor device structure 11 is according to actual semiconductor device structure determination.In some implementations
In example, the semiconductor device structure 11 can be identical with actual semiconductor device structure.In the present embodiment, the semiconductor device
Part structure 11 is illustrated by taking four layers of metal level as an example, is illustrated herein, should not too be limited the scope of the invention.
First test layer 121 is located at same layer, second test with the first layer in four layers of metal level 111
Layer 123 is located at same layer with the second layer in four layers of metal level 111.In other embodiments, first test layer 121
It can be located at same layer with any two layers in four layers of metal level 111 respectively with the second test layer 123.
In practical application, the distance of the test cell 12 and the semiconductor device structure 11 is according to specific technique section
Point determines.In certain embodiments, the distance of the test cell 12 and the semiconductor device structure 11 is more than minimal design
Size.For example, in 28nm process node, the distance of the test cell 12 and the semiconductor device structure 11 is more than
50nm.In 40nm process node, the distance of the test cell 12 and the semiconductor device structure 11 is more than 70nm.
In other embodiment, the distance of the test cell 12 and the semiconductor device structure 11 can also be other values.
Specifically, the material of first test layer 121 and second test layer 123 is metal, such as copper or aluminium.Institute
State dielectric layer 112 to be made up of low-K material or ultra low-K material, such as carborundum, silicon oxide carbide, organic siloxane polymer, fluorine carbonization
Compound etc..The material of the conductive plunger 122 of first conductive plunger 113 and second is copper or aluminium etc..
On the dielectric layer 112, the first test lead 124, second test are led on first test layer 121
The second test lead 125 is led on layer 123.When being tested, first test lead 124 is used to apply supply voltage, the
Two test leads 125 are used to be grounded.By measuring the leakage current value between the test lead 125 of the first test lead 124 and second, if
When the leakage current value is more than reference current value, it can be determined that the portion between the test layer 123 of the first test layer 121 and second
Dielectric layer 112 is divided fracture or lamination to be present.
In other embodiments, the performance parameter of test can be the other specification beyond leakage current value, such as resistance value.
Specifically, by measuring the current value between the first test lead 124 and the second test lead 125, the first test layer 121 and the are obtained
Resistance value between two test layers 123, if the resistance value is outside with reference to Standard resistance range, it can be determined that the first test layer 121
Fracture or lamination be present in the certain media layer 112 between the second test layer 123.
In other embodiments, the test structure of the semiconductor devices can also include multiple semiconductor device structures,
The test cell can also include multilayer other test layers, the multiple conductive plungers for connecting these test layers and these tests
The multiple test leads drawn on layer.By measuring the performance parameter between any two layers of test layer, it can be determined that described any two
Dielectric layer between layer test layer is with the presence or absence of fracture or lamination.
Fig. 3 is the cross-sectional view of the test structure for the semiconductor devices that another embodiment of the present invention provides.
With reference to figure 3, the test structure of the semiconductor devices includes：Two semiconductor device structures 21a and 21b, and
Test cell 22, described two semiconductor device structure 21a and 21b are symmetrically dispersed in the both sides of the test cell 22.Often
Individual semiconductor device structure includes：Four layers of metal level 211 in dielectric layer 212, have between adjacent two metal layers 211
There are multiple first conductive plungers 213.The first test layer 221 that the test cell 22 includes being located in the dielectric layer 212, the
Two test layers 222, the 3rd test layer 223, the 4th test layer 224 and multiple second conductive plungers 225, wherein, adjacent two
Second conductive plunger 225 of the layer test layer between electrically connects.First test layer 221, the second test layer the 222, the 3rd
Four layer metal level 211 of the test layer 224 of test layer 223 and the 4th respectively with each semiconductor device structure are located at same layer.
Similar with previous embodiment, the distance of the test cell 22 and the semiconductor device structure is according to specific
Process node determines.First test layer 221, the second test layer 222, the 3rd test layer 223 and the 4th test layer 224
Material is metal, such as copper or aluminium.The dielectric layer 212 is made up of low-K material or ultra low-K material.First conductive plunger
213 and second conductive plunger 225 material for aluminium or copper etc..
The first test lead 221 ' is led on first test layer 221, second is led on second test layer 222
Test lead 222 ', lead on the 3rd test layer 223 and draw on the 3rd test lead 223 ', and the 4th test layer 224
Going out has the 4th test lead 224 '.
In the present embodiment, by measuring leakage current value or resistance value between any two test lead respectively, you can respectively
Dielectric layer 212 between two layers of test layer corresponding to judgement is with the presence or absence of fracture or lamination.
Fig. 4 is the cross-sectional view of the test structure for the semiconductor devices that another embodiment of the present invention provides.
With reference to figure 4, the test structure of the semiconductor devices includes：Two semiconductor device structures 31a and 31b, and
Test cell 32, described two semiconductor device structure 31a and 31b are symmetrically dispersed in the both sides of the test cell 32.Often
Individual semiconductor device structure includes：Four layers of metal level 311 in dielectric layer 312, have between adjacent two metal layers 311
There are multiple first conductive plungers 313.The first test layer 321 that the test cell 32 includes being located in the dielectric layer 312, the
Two test layers 322, the 3rd test layer 323, the 4th test layer 324 and multiple second conductive plungers 325, wherein, adjacent two
Second conductive plunger 325 of the layer test layer between electrically connects.First test layer 321, the second test layer the 322, the 3rd
Four layer metal level 311 of the test layer 324 of test layer 323 and the 4th respectively with each semiconductor device structure are located at same layer, its
In, the first test layer 321 is connected with the first metal layer in semiconductor device structure 31b, the second test layer 322 and semiconductor device
Second metal layer in part structure 31a is connected.
Similar with previous embodiment, the distance of the test cell 32 and the semiconductor device structure is according to specific
Process node determines.First test layer 321, the second test layer 322, the 3rd test layer 323 and the 4th test layer 324
Material is metal, such as copper or aluminium.The dielectric layer 312 is made up of low-K material or ultra low-K material.First conductive plunger
313 and second conductive plunger 325 material for aluminium or copper etc..
First test layer 321, second test layer 322, the 3rd test layer 323 and the 4th test
Corresponding test lead is led on layer 324（It is not shown）.By measuring leakage current value or electricity between any two test lead
Resistance, you can the dielectric layer 312 between two layers of test layer corresponding to judgement is with the presence or absence of fracture or lamination.
In other embodiments, multi-layer testing layer is connected with multiple metal levels of same semiconductor device structure, then,
When being tested using the test structure of the semiconductor devices, two test leads are respectively and a semiconductor device structure
In the connected test lead of layer of metal layer and the test lead being connected with the layer of metal layer in another semiconductor device structure.
Such as first test layer 321 be connected with semiconductor device structure 31b, the second test layer 322, the 3rd test layer 323 and the 4th
Test layer 324 is connected with semiconductor device structure 31a.So, surveyed using the test structure of the semiconductor devices
During examination, two test leads are respectively the test lead and the second test layer 322 or the 3rd test drawn on the first test layer 321
The test lead drawn on the test layer 324 of layer 323 or the 4th.
Because semiconductor device structure and actual semiconductor device are prepared using same process, and with mutual corresponding pass
System, therefore by detecting the electrology characteristic of the dielectric layer with semiconductor device structure, also it is obtained with practical semiconductor device
The electrology characteristic of dielectric layer in part.
One embodiment of the present of invention additionally provides a kind of forming method of the test structure of semiconductor devices.Fig. 5 extremely schemes
10 be the cross-sectional view of the forming method of the test structure of semiconductor devices in one embodiment of the present of invention.
First, it refer to Fig. 5, there is provided substrate 400, and form first medium layer 410 in the substrate 400.
In the present embodiment, the material of the substrate 400 can be on monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, insulator
Well known to a person skilled in the art other semi-conducting materials for silicon, iii-v element compound, monocrystalline silicon carbide etc..
In the present embodiment, the material of the first medium layer 410 can be low-K material or ultra low-K material, such as be carbonized
Silicon, silicon oxide carbide, organic siloxane polymer, fluorocarbons etc..The first medium layer 410 can use chemical vapor deposition
Product（Chemical Vapor Deposition, CVD）Technique or thermal oxide growth technique are formed.The first medium layer 410 is made
For intermetallic dielectric layer（Inter-Metal Dielectric, IMD）Use.
Fig. 6 is refer to, the first groove 411 of formation and the second groove 412 in the first medium layer 410, described first
The groove 412 of groove 411 and second exposes the substrate 400.
In a particular embodiment, forming the first groove 411 and the method for the second groove 412 includes：Use photoetching, etching work
Skill.Concrete technology is：Patterned photoresist layer, the patterned photoresist layer are formed on the first medium layer 410
Define the position of the first groove 411 and the second groove 412；Using patterned photoresist layer as mask etching first medium layer 410
Until the exposure Semiconductor substrate 400；Patterned photoresist layer is removed, forms the first groove 411 and the second groove 412.
In the present embodiment, the method for the etching first medium layer 410 includes dry etch process, such as plasma etch process
Deng.
First groove 411 be used in subsequent step formed semiconductor device structure in metal level, described second
Groove 412 is used for the test layer formed in subsequent step in test cell.In certain embodiments, in first medium layer 410
The second groove 412 can not also be formed.
Fig. 7 is refer to, metal is filled into the groove 412 of the first groove 411 and second, removes the first groove afterwards
411 and second metal unnecessary beyond groove 412, the test layer 414 of the first metal layer 413 and first is formed respectively so that described
The test layer 414 of the first metal layer 413 and first flushes with the surface of the first medium layer 410.The first groove 411 of the removal
Cmp can be used with metal unnecessary beyond the second groove 412（Chemical-Mechanical
Polishing, CMP）Technique.
In the present embodiment, the metal is copper.The method for forming the test layer 414 of the first metal layer 413 and first has thing
Physical vapor deposition（Physical vapor deposition, PVD）, chemical vapor deposition, ionization PVD, plating etc..
Fig. 8 is refer to, the is formed above the first medium layer 410, the test layer 414 of the first metal layer 413 and first
Second medium layer 420, and contact hole 421~424 is formed in the second dielectric layer 420.The contact hole 421~423 exposes
Go out the first metal layer 413 of lower floor, the contact hole 424 exposes the first test layer 414 of lower floor.The number of the contact hole
Determined according to the situation of actual semiconductor device.
The contact hole 421~423 is used for the conductive plunger formed in subsequent step in semiconductor device structure, described
Contact hole 424 is used for the conductive plunger formed in subsequent step in test cell.In certain embodiments, second dielectric layer
Contact hole 424 can not also be formed in 420.
Fig. 9 is refer to, deposited metal layer forms the first conductive plunger 425 and second and led in the contact hole 421~424
Electric plug 426.
The lower end of first conductive plunger 425 is connected with the first metal layer 413, second conductive plunger 426
Lower end be connected with first test layer 414.In the present embodiment, the conductive plunger of the first conductive plunger 425 and second
426 material is copper.
Then, then in the top of the second dielectric layer 420, the first conductive plunger 425 and the second conductive plunger 426 formed
3rd dielectric layer 430, the step in Fig. 6~Fig. 9 is repeated, until the test structure of semiconductor devices as shown in Figure 10 is formed,
It includes semiconductor device structure 41 and test cell 42.
In other embodiments, the first metal layer 413, the first test layer 414, the first conductive plunger 425 and second are conductive
The material of connector 426 can also be aluminium etc..
To sum up, test structure of semiconductor devices provided in an embodiment of the present invention and forming method thereof, can detect low K or
The dielectric layer of ultra low-K material can specifically judge that the dielectric layer of which part is present with the presence or absence of fracture or lamination
Fracture or lamination.
Although the present invention is disclosed as above with preferred embodiment, the present invention is not limited to this.Any art technology
Personnel, without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore protection scope of the present invention should
When limiting scope with claim.
Claims (14)
- A kind of 1. test structure of semiconductor devices, it is characterised in that including：First semiconductor device structure, including：More metal layers spaced apart from each other in dielectric layer, adjacent double layer of metal There is the first connector between layer；AndTest cell, in the dielectric layer of the side of first semiconductor device structure, the test cell and institute State the first semiconductor device structure spaced a predetermined distance, the test cell includes multi-layer testing layer, the multi-layer testing layer with Some or all of metal level is corresponding in first semiconductor device structure, and the multi-layer testing interlayer is inserted formed with second Plug, the test cell are used to judge described the first half based on the leakage current value between any two layers test layer or resistance value The dielectric layer of the multiple layer metal interlayer of conductor device structure is with the presence or absence of fracture or layering.
- 2. the test structure of semiconductor devices as claimed in claim 1, it is characterised in that the opposite side tool of the test cell There is the second semiconductor device structure, second semiconductor device structure and the first semiconductor device structure are identical in structure.
- 3. the test structure of semiconductor devices as claimed in claim 2, it is characterised in that first semiconductor device structure The test cell both sides are symmetrically distributed in second semiconductor device structure.
- 4. the test structure of semiconductor devices as claimed in claim 2, it is characterised in that in the multi-layer testing layer at least Electrically connected respectively with the layer of metal layer of first semiconductor device structure for two layers, with second semiconductor device structure Layer of metal layer electrically connects.
- 5. the test structure of semiconductor devices as claimed in claim 1, it is characterised in that the test cell also includes first Test lead and the second test lead, first test lead are used to connect power end, and second test lead is used to be grounded, and described the One test lead and the second test lead and the corresponding electrical connection respectively of two layers in the multi-layer testing layer.
- 6. the test structure of the semiconductor devices as any one of claim 1 to 5, it is characterised in that the semiconductor Preset distance between device architecture and the test cell is more than minimum design dimension.
- 7. the test structure of the semiconductor devices as any one of claim 1 to 5, it is characterised in that the dielectric layer Material be low K or ultra low-K material.
- A kind of 8. forming method of the test structure of semiconductor devices, it is characterised in that including：Form dielectric layer；More metal layers are formed in the dielectric layer；Multiple first connectors, the more metal layers and the multiple first connector structure are formed between adjacent two metal layers Into the first semiconductor device structure；AndIn the dielectric layer, the side formation test cell of first semiconductor device structure, the test cell and institute State the first semiconductor device structure spaced a predetermined distance, the formation test cell, which is included in the dielectric layer, forms multilayer survey Try layer and form the second connector, the multi-layer testing layer and first semiconductor device structure in the multi-layer testing interlayer In some or all of metal level it is corresponding, the test cell is used for based on the leakage current value between any two layers test layer Or resistance value judges the dielectric layer of the multiple layer metal interlayer of first semiconductor device structure with the presence or absence of fracture or layering.
- 9. the forming method of the test structure of semiconductor devices as claimed in claim 8, it is characterised in that be additionally included in described In dielectric layer, the opposite side of the test cell form the second semiconductor device structure, second semiconductor device structure with First semiconductor device structure is identical in structure.
- 10. the forming method of the test structure of semiconductor devices as claimed in claim 9, it is characterised in that described the first half Conductor device structure is symmetrically distributed in the test cell both sides with second semiconductor device structure.
- 11. the forming method of the test structure of semiconductor devices as claimed in claim 9, it is characterised in that the multilayer is surveyed Electrically connect with the layer of metal layer of first semiconductor device structure at least two layers in examination layer, led with described the second half respectively The layer of metal layer electrical connection of body device architecture.
- 12. the forming method of the test structure of semiconductor devices as claimed in claim 8, it is characterised in that also include being formed The first test lead and the second test lead electrically connected with the test cell, first test lead are used to connect power end, institute State the second test lead to be used to be grounded, first test lead and the second test lead and two layers in the multi-layer testing layer are right respectively It should electrically connect.
- 13. the forming method of the test structure of the semiconductor devices as any one of claim 8 to 12, its feature exists In the preset distance between the semiconductor device structure and the test cell is more than minimum design dimension.
- 14. the forming method of the test structure of the semiconductor devices as any one of claim 8 to 12, its feature exists In the material of the dielectric layer is low K or ultra low-K material.
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| CN106571311B (en) * | 2015-10-10 | 2019-04-26 | 中芯国际集成电路制造(上海)有限公司 | The test device and its test method of through silicon via |
| CN107578986B (en) * | 2016-07-04 | 2019-11-01 | 中芯国际集成电路制造(上海)有限公司 | The measurement method of semiconductor structure and forming method thereof and photoetching offset |
| CN109560099A (en) * | 2018-11-29 | 2019-04-02 | 德淮半导体有限公司 | For the semiconductor devices and its detection method of plasma damage detection, forming method |
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| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
| CN102456667A (en) * | 2010-10-19 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Pad structure having contact bars extending into substrate and wafer having the pad structure |
| CN103137607A (en) * | 2011-12-02 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Conductor failure detection structure, a forming method, and a method of detecting failure time |
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| US8125054B2 (en) * | 2008-09-23 | 2012-02-28 | Texas Instruments Incorporated | Semiconductor device having enhanced scribe and method for fabrication |
| US8039367B2 (en) * | 2009-05-13 | 2011-10-18 | United Microelectronics Corp. | Scribe line structure and method for dicing a wafer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
| CN102456667A (en) * | 2010-10-19 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Pad structure having contact bars extending into substrate and wafer having the pad structure |
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