CN103630825B - Chip test circuit and forming method thereof - Google Patents
Chip test circuit and forming method thereof Download PDFInfo
- Publication number
- CN103630825B CN103630825B CN201210313499.2A CN201210313499A CN103630825B CN 103630825 B CN103630825 B CN 103630825B CN 201210313499 A CN201210313499 A CN 201210313499A CN 103630825 B CN103630825 B CN 103630825B
- Authority
- CN
- China
- Prior art keywords
- test
- layer
- conducting block
- chip
- conductive plunger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention provides a kind of chip test circuit and forming method thereof and the method for testing using described test circuit, wherein said chip test circuit comprises: at least one deck test structure, every one deck test structure comprises: the first test layer, comprises multiple the first conducting block be electrically connected to each other; Second test layer, described second test layer is positioned at below or the top of described first test layer, and described second test layer comprises multiple ring texture, described ring texture and described first conducting block one_to_one corresponding, each described ring texture comprises the second conducting block at center and the 3rd conducting block at outer shroud, dielectric material between described second conducting block and the 3rd conducting block; And multiple first conductive plunger, for being electrically connected described first conducting block and second conducting block corresponding with it.Described chip test circuit can not only reflect the practical structures of chip, and can improve the precision of testing chip before package.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of chip test circuit and forming method thereof.
Background technology
In ic chip package, generally realize being communicated with of chip and outside port by bonding wire.Fig. 1 is the diagrammatic cross-section of a chip-packaging structure in prior art.As shown in Figure 1, one end of bonding wire 15 is beaten on wire pad 14 by throwing device, is connected with chip 13, and other one end of bonding wire 15 is connected to outside port 12, and therefore, described chip 13 can be electrically connected to outside port 12 by described bonding wire 15.After above-mentioned bonding process, to be describedly just placed in mold 11 by the chip 13 that bonding wire 15 is communicated with, and by injecting sealing resin 16, described chip 13 to be encapsulated.
But in above-mentioned bonding process, described throwing device institute applied pressure may make to occur in chip that dielectric layer crack and each metal level bond unstable problem.Fig. 2 is the partial enlarged drawing of part shown in Fig. 1 dotted line, throwing device by described bonding wire 15 dozens on wire pad 14 time, the chip structure that its applied pressure will affect below pad zone 10.On the other hand, along with the size of semiconductor devices reduces, low k dielectric materials is inevitably used in the manufacture process of chip, elasticity coefficient due to low k dielectric materials is less and adhesiveness is poor, and so just the chip structure increased below described pad zone 10 respectively occurs that when being under pressure dielectric layer crack and each metal level bond unstable possibility more.
If occur that dielectric layer crack and each metal level thereof bond unstable problem in the chips, just mean that this chip damages, can not be used.In order to not affect the yield rate of product, the chip of described damage needs to be detected before packaging.
Because crack appears in the dielectric layer in chip, just there will be short circuit phenomenon, thus produce leakage current, therefore by carrying out leakage current test to chip, we can judge whether chip internal damages.In prior art, be generally, by probe, front test is encapsulated to chip.Chinese patent literature as patent publication No. to be CN101622545A and publication date be on January 6th, 2010 discloses a kind of probe detection device.Before utilizing probe to carry out the encapsulation of chip, test generally comprises following steps: by the connection of probe and wire pad, test signal is introduced chip internal; Then, make test signal flow through the test circuit of chip internal, then flowed out by the test pin of chip, judge that whether chip is damaged by the test signal of this outflow.Fig. 3 is the cross-sectional view of the test circuit before the encapsulation of prior art chips, and with reference to figure 3, this test circuit is simple metal construction and dielectric material of simulating chip under test just, well can not react the chip under test of high integration high complexity.
Therefore, need to propose a kind of new chip test circuit and method of testing thereof, the practical structures of simulation chip under test that can be more true to nature, thus improve the precision of chip testing.
Summary of the invention
The problem that the present invention solves is to provide a kind of chip test circuit and method of testing thereof, can not only reflect the practical structures of chip under test, and can avoid because existing test circuit can not reflect the practical structures of chip preferably that the test that leads to errors judges.
For solving the problem, embodiments provide a kind of chip test circuit, comprise: at least one deck test structure, described at least one deck test structure is stacked arrangement, and be formed with interlayer dielectric layer between adjacent test structure, every one deck test structure comprises: the first test layer, and described first test layer comprises multiple the first conducting block be electrically connected to each other; Second test layer, described second test layer is positioned at below or the top of described first test layer, and described second test layer comprises multiple ring texture, described ring texture and described first conducting block one_to_one corresponding, each described ring texture comprises the second conducting block at center and the 3rd conducting block at outer shroud, dielectric material between described second conducting block and the 3rd conducting block, and is electrically connected to each other between multiple described 3rd conducting block; And multiple first conductive plunger, described first conductive plunger is between described first test layer and the second test layer, for being electrically connected described first conducting block and second conducting block corresponding with it, every one deck first test layer and every one deck second test layer all distinguish the layer of metal layer of corresponding chip under test.
Alternatively, the square or circular Zhou Chang great that the section girth specific area of described second conducting block is identical.
Alternatively, described chip test circuit also comprises: multiple second conductive plunger, between adjacent two test structures, for being electrically connected the second conducting block of adjacent test structure and corresponding first conducting block.
Alternatively, described chip test circuit also comprises: multiple 3rd conductive plunger, described 3rd conductive plunger weld pad and and the hithermost test layer of described weld pad between, for being electrically connected weld pad and the conducting block with the hithermost test layer of described weld pad.
Alternatively, the first conductive plunger be connected with each second conducting block is one or more.
Alternatively, the cross-sectional area of described first conductive plunger is 1/4 ~ 3/4 of described second conducting block.
The embodiment of the present invention additionally provides a kind of formation method of chip test circuit, comprising: form at least one deck test structure, and described at least one deck test structure is stacked arrangement; The formation method of every one deck test structure comprises: form the first conductive layer; Graphically described first conductive layer forms the first test layer, and described first test layer comprises multiple the first conducting block be electrically connected to each other; Described first test layer forms the first interlayer dielectric layer; Multiple first conductive plunger is formed, the position of described first conductive plunger and the position one_to_one corresponding of described first conducting block in described first interlayer dielectric layer; Form the second conductive layer, cover described first interlayer dielectric layer and described first conductive plugs; Graphically described second conductive layer forms the second test layer, described second test layer comprises multiple ring texture, the position one_to_one corresponding of described ring texture and described first conducting block, each described ring texture comprises the second conducting block being positioned at center and the 3rd conducting block being positioned at outer shroud, described second conducting block is positioned at accordingly on described first conductive plugs, is electrically connected to each other between described 3rd conducting block; And in described second conducting block and the 3rd conducting block filled media material, or, the formation method of every one deck test structure comprises: form the second conductive layer, graphically described second conductive layer is to form the second test layer, described second test layer comprises multiple ring texture, each described ring texture comprises the second conducting block being positioned at center and the 3rd conducting block being positioned at outer shroud, is electrically connected to each other between described 3rd conducting block; Filled media material in described second conducting block and the 3rd conducting block; Described second layer test layer forms the first interlayer dielectric layer; Multiple first conductive plunger is formed, the position of described first conductive plunger and the position one_to_one corresponding of described second conducting block in described first interlayer dielectric layer; And the first conductive layer is formed on described first interlayer dielectric layer; Graphically described first conductive layer forms the first test layer, and described first test layer comprises multiple the first conducting block be electrically connected to each other, and with the position one_to_one corresponding of described first conductive plunger; Wherein, every one deck first test layer and every one deck second test layer all distinguish the layer of metal layer of corresponding chip under test.
Alternatively, the square or circular Zhou Chang great that the section girth specific area of described second conducting block is identical.
Alternatively, after formation one deck test structure, formed and to be positioned on this layer of test structure and before another layer of test structure adjacent with this layer of test structure, the formation method of described chip test circuit also comprises: form the second interlayer dielectric layer, described second interlayer dielectric layer covers this layer of test structure, the second conductive plunger is formed in described second interlayer dielectric layer, described second conductive plunger between adjacent two layers test structure, for being electrically connected the second conducting block of adjacent test structure and corresponding first conducting block.
Alternatively, after forming the test structure being positioned at most top layer, before forming weld pad, the formation method of described chip test circuit also comprises: form dielectric layer between third layer, between described third layer dielectric layer cover described in most top layer test structure; Between described third layer, form multiple 3rd conductive plunger in dielectric layer, described 3rd conductive plunger is for being electrically connected described weld pad and the conducting block corresponding to described top layer test structure.
Alternatively, the first conductive plunger be connected with each second conducting block is one or more.
Alternatively, the cross-sectional area of described first conductive plunger is 1/4 ~ 3/4 of described second conducting block.
The embodiment of the present invention additionally provides a kind of method of testing utilizing said chip test circuit, comprising: provide test component, and described test component has the first test lead and the second test lead; Multiple first conducting block of the first test layer of one deck test structure is electrically connected with described first test lead; Multiple 3rd conducting blocks of the second test layer of this layer of test structure are electrically connected with described second test lead; Whether have electric current pass through, judge whether there is leakage current between the first test layer of described test structure and the second test layer if monitoring described test component; According to described leakage current test result, judge whether the dielectric material of the second test layer be connected with described second test lead occurs crack, thus infer whether the metal level of the chip under test corresponding with described second test layer occurs crack.
Alternatively, described method of testing also comprises: be electrically connected with described first test lead by multiple 3rd conducting blocks of described test by the second test layer of one deck test structure; Multiple first conducting block of the first test layer of the test structure adjacent with this layer of test structure is electrically connected with described second test lead; Whether have electric current pass through, judge whether there is leakage current between described test structure and adjacent test structure if monitoring described test component; According to described leakage current test result, judge whether the interlayer dielectric layer between described test structure and adjacent test structure occurs crack, thus infer whether the interlevel dielectric material of the chip under test corresponding with described interlayer dielectric layer occurs crack.
Compared with prior art, embodiments of the invention have the following advantages:
In an embodiment of the present invention, metal level in chip under test is simulated by forming the first test layer and the second test layer, and simulate conductive plunger in chip under test by forming the first conductive plunger, therefore the chip test circuit that the embodiment of the present invention provides can be more true to nature the structure of simulation chip under test, thus the actual inside situation of chip under test can be reacted more accurately.
Secondly, the layer of metal layer of the first test layer in described chip test circuit and the corresponding chip under test of the second test layer difference, by between described first test layer and the second test layer of same test structure and carry out leakage current test between adjacent test structure, then accurately can judge which layer metal level the damage of chip under test appears at according to its test result, thus improve the precision of chip testing.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art chips encapsulation;
Fig. 2 is the structural representation of the partial enlargement of Fig. 1;
Fig. 3 is the cross-sectional view of the test circuit before the encapsulation of prior art chips;
Fig. 4 is the cross-sectional view of the chip test circuit of one embodiment of the invention;
Fig. 5 is the cross sectional representation of Fig. 4 along AA ' direction;
Fig. 6 is the cross sectional representation of Fig. 4 along BB ' direction;
Fig. 7 is the cross-sectional structure schematic diagram of the ring texture of the second test layer of one embodiment of the invention;
Fig. 8 is the xsect contrast schematic diagram of two kinds of difform second conductive layers;
Fig. 9 is the schematic diagram of the chip test circuit of another embodiment of the present invention;
Figure 10 is the schematic diagram of the chip detecting method of one embodiment of the invention;
Figure 11 is the schematic diagram of the chip detecting method of another embodiment of the present invention; And
Figure 12 is the schematic diagram of the chip detecting method of another embodiment of the present invention.
Embodiment
From background technology, according to the test result of existing test circuit, the damaged condition of chip under test effectively can not be judged.Inventor finds after deliberation, and along with development and the improvement of integrated circuit, the metal connecting line of chip internal is more and more meticulousr, and chip test circuit of the prior art can not reflect the IC complexity after improvement.The structure of chip build-in test circuit plays key effect in test process, only when the structure of described test circuit can emulate the inner structure of chip under test preferably, situation about can damage according to described test circuit judges that whether the inner structure of chip under test is damaged.Furthermore, if make test circuit can not only emulate the actual internal structure of chip under test, and the damaged condition of amplification chip under test practical structures that can be suitable, the sensitivity of such test circuit is just relatively high.
For the problems referred to above, The embodiment provides a kind of chip test circuit, described chip test circuit formation method and utilize described test circuit to carry out the method for testing of testing.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Lower mask body composition graphs 4 ~ 8, is described in detail the chip test circuit that the embodiment of the present invention provides.
Fig. 4 is the cross-sectional view of the chip test circuit of one embodiment of the invention.Please refer to Fig. 4, described chip test circuit 200 comprises at least one deck test structure, every one deck test structure comprises the first test layer 210 and the second test layer 220, and described at least one deck test structure is stacked arrangement, and is formed with interlayer dielectric layer (figure does not show) between adjacent test structure.
In embodiments of the present invention, as shown in Figure 4, described chip test circuit 200 can be arranged on the side of chip under test 100, and described chip under test 100 is all positioned at below weld pad (not shown).And the number of plies of described test structure can be determined by the number of plies of the metal level 110 of chip under test 100, the first test layer 210 wherein in each test structure and the second test layer 220 distinguish the layer of metal layer 110 of corresponding chip under test 100.If the metal level of described chip under test is n layer, and n is even number, and so described test circuit comprises the described test structure of n/2 layer; If the metal level of described chip under test is n layer, and n is odd number, and so described test circuit comprises the described test structure of n-1/2 layer and independent one deck first test layer or the second test layer.In order to simplify, only comprise four layers of metal level for chip under test in the diagram and being described.
Please continue to refer to Fig. 4, described first test layer 210 comprises multiple first conducting block 211.Fig. 5 is the schematic cross-section of Fig. 4 along AA ' direction.As shown in Figure 5, be electrically connected to each other between described multiple first conducting block 211, so that the follow-up test lead described multiple first conducting block 211 being electrically connected to leakage current test component in test process.
In embodiments of the present invention, described second test layer 220 can be positioned at below or the top of described first test layer 210.For the purpose of simplifying the description, the below being only positioned at described first test layer for the second test layer 220 is below described.
Please continue to refer to Fig. 4, described second test layer 220 comprises multiple ring texture 230, described ring texture 230 and described first conducting block 211 one_to_one corresponding.
Fig. 6 is the cross sectional representation of Fig. 4 along BB ' direction.As shown in Figure 4 and Figure 6, each ring texture 230 comprises the second conducting block 231 being positioned at center and the 3rd conducting block 233 being positioned at outer shroud, and the dielectric material 232 between described second conducting block 231 and the 3rd conducting block 233.In addition, be electrically connected to each other between multiple described 3rd conducting block 233 in same second test layer 220, to facilitate another test port the 3rd conducting block 233 of the second test layer 220 being all electrically connected to leakage current test component in follow-up test process.
In an embodiment of the present invention, the material of the dielectric material 232 between described second conducting block 231 and the second conducting block 233 can be identical with the interlevel dielectric material of chip under test, also other dielectric materials more easily producing crack under stress can be adopted, to improve the sensitivity of described chip test circuit.
It should be noted that, in an embodiment of the present invention, shape is non-square or non-circular to the xsect (described cross-section normal is in the follow-up bearing of trend by the first conductive plunger of description) of the second conducting block 221, and the square or circular Zhou Chang great that the section girth specific area of described second conducting block 221 is identical.Can infer thus, described second conducting block is when keeping cross-sectional area constant, have larger girth, the pressure that so described first conducting block bears at the same pressure is constant, but larger with the contact area of described dielectric material 232 when described first conducting block same thickness.
Below using the xsect of described second conducting block for square frame-shaped is described in detail as comparison other.As shown in Figure 7, the cross sectional representation of the loop configuration 230 ' that the left side is the xsect of the second conducting block 231 ' when being square frame-shaped, the cross sectional representation of the loop configuration 230 that the right is the xsect of the second conducting block 231 when being irregularly shaped, wherein, the cross-sectional area of the second conducting block 231 ' is identical with the cross-sectional area of the second conducting block 231, that is the area equation that surrounds of the described irregular figure of girth to be the area of the square enclosure of X and described girth be Y, this just means that the pressure that described second conducting block 231 ' and the second conducting block 231 are at the same pressure subject to is equal, but, the girth Y of described irregular figure is larger than described square girth X, when described ring texture 230 ' is equal with ring texture 230 thickness, described in the contact area rate of described second conducting block 231 ' and dielectric material 232 ', the second conducting block 231 and dielectric material 232 contact area want large, therefore, when identical pressure, occur that the probability in crack is larger at the surface of contact of described second conducting block 231 and dielectric material 232, thus improve the sensitivity of described test circuit further.
Please continue to refer to Fig. 4, described test circuit 200 also comprises multiple first conductive plunger 240, described first conductive plunger 240 between described first test layer 210 and the second test layer 220, for being electrically connected described first conducting block 211 and second conducting block 231 corresponding with it.
It should be noted that, as shown in Figure 4, described first conductive plunger 240 can be used for simulating the conductive plunger 120 in described chip under test 100.In embodiments of the present invention, the sectional area of described first conductive plunger 240 is 1/4 ~ 3/4 of described first conducting block 231 area, the xsect of described first conductive plunger 240 can be any figure applicatory, is circular being described at this for the xsect of described first conductive plunger 240.
In addition, and each ring texture 230 second conducting block 231 be electrically connected the first conductive plunger 240 can be one or more.Such as, in fig. 8, the first conductive plunger 240 be communicated with the second conducting block 231 of described ring texture 230 is 8.It should be noted that, when described second conducting block 231 comprises multiple first conductive plunger 240, can when the first conductive plunger 240 for when one bear pressure and be applied to multiple regions inside the described dielectric material 232 by multiple first conductive plunger 240 dispersion, make the dielectric material in test circuit be more prone to occur crack, thus improve the sensitivity of chip test circuit further.
Please continue to refer to Fig. 4, described chip test circuit 200 can also comprise multiple second conductive plunger 250, between adjacent two test structures, for being electrically connected the second conducting block 231 of adjacent test structure and corresponding first conducting block 211.
In embodiments of the present invention, when in described test structure, the second test layer 220 is positioned at below the first test layer 210, described second conductive plunger 250 is for being electrically connected corresponding first conducting block 211 of test structure adjacent below the second conducting block 231 of one deck test structure and this layer of test structure, when in described test structure, the second test layer 220 is positioned at above the first test layer 210, described second conductive plunger 250 is for being electrically connected corresponding second conducting block 231 of test structure adjacent below the first conducting block 211 of one deck test structure and this layer of test structure.
Please continue to refer to Fig. 4, described chip test circuit 200 can also comprise multiple 3rd conductive plunger (figure does not show), described 3rd conductive plunger weld pad and and the hithermost test layer of described weld pad between, for being electrically connected weld pad and the conducting block with the hithermost test layer of described weld pad.
Concrete composition graphs 4 and Fig. 9 more below, is described in detail the formation method of the chip test circuit that the embodiment of the present invention provides.As mentioned above, described second test layer can be positioned at below or the top of described first test layer, will first describe the formation method of the described test circuit when above described second test layer is positioned at described first test layer below.
First, please refer to Fig. 9, form the first test layer 210.The formation method of described first test layer 210 comprises: form the first conductive layer (figure does not show); Graphically described first conductive layer is to form described first test layer 210, and described first test layer comprises multiple the first conducting block 211 be electrically connected to each other.
Then, please refer to Fig. 9, form the first conductive plunger 240.The formation method of described first conductive plunger 240 comprises: on described first test layer, form the first interlayer dielectric layer (figure does not show), described first interlayer dielectric layer covers described first test layer; Patterned photoresist is formed, with described patterned photoresist for the first interlayer dielectric layer described in mask etching is to form multiple first through hole in described first interlayer dielectric layer; Multiple first conductive plunger 240 is formed, the position of described first conductive plunger 240 and the position one_to_one corresponding of described first conducting block in described first through hole.Described first conductive plunger 240 can be used for simulating the conductive plunger 120 in described chip under test 100.
In addition, and each ring texture 230 second conducting block 231 be electrically connected the first conductive plunger 240 can be one or more.
Then, please refer to Fig. 9, form the second test layer 220.The formation method of described second test layer 220 comprises: form the second conductive layer (figure does not show), cover described first interlayer dielectric layer and described first conductive plunger; Graphically described second conductive layer forms the second test layer 220, described second test layer 220 comprises multiple ring texture 230, the position one_to_one corresponding of described ring texture 230 and described first conducting block 210, each described ring texture 220 comprises the second conducting block 231 being positioned at center and the 3rd conducting block 233 being positioned at outer shroud, described second conducting block 231 is positioned at accordingly on described first conductive plunger 221, is electrically connected to each other between described 3rd conducting block 233.In an embodiment of the present invention, the shape of cross section of described second conducting block 221 is non-square or non-circular, and the square or circular Zhou Chang great that the section girth specific area of described second conducting block 221 is identical.
Then, please refer to Fig. 9, filled media material 232 in described second conducting block 231 and the 3rd conducting block 233.
Adjacent described first test layer 210 and the second test layer 220 form a test structure, and test structure described at least one is that stacked arrangement forms described chip test circuit.As previously mentioned, in embodiments of the present invention, described chip test circuit 200 can be arranged on chip under test 100 side, and described chip under test is all positioned at below weld pad.And the number of plies of described test structure can be determined by the number of plies of the metal level of chip under test, the first test layer 210 wherein in each test structure and the second test layer 220 distinguish the layer of metal layer of corresponding chip under test.
Then, please continue to refer to Fig. 9, after formation one deck test structure, formed and be positioned on this layer of test structure and before another layer of test structure adjacent with this layer of test structure, the second conductive plunger 250 can also be formed.The method of described second conductive plunger 250 comprises: form the second interlayer dielectric layer (figure does not show), described second interlayer dielectric layer covers described test structure; Described second interlayer dielectric layer forms patterned photoresist; With described patterned photoresist for the second interlayer dielectric layer described in mask etching is to form multiple second through hole; In described second through hole, form described second conductive plunger 250, described second conductive plunger between adjacent two test structures, for being electrically connected the second conducting block of adjacent test structure and corresponding first conducting block.
Then, after forming the test structure being positioned at most top layer, before forming weld pad, the 3rd conductive plunger (figure does not show) can also be formed.The formation method of described 3rd conductive plunger comprises: form dielectric layer between third layer, between described third layer dielectric layer cover described in most top layer test structure; Between described third layer, dielectric layer forms patterned photoresist, with described patterned photoresist for dielectric layer between third layer described in mask etching is to form multiple third through-hole; In described third through-hole, form described 3rd conductive plunger, described 3rd conductive plunger is for being electrically connected described weld pad and the conducting block corresponding to described top layer test structure.
The formation method of the described test circuit the foregoing described when described second test layer is positioned at below described first test layer will be specifically described below.
First, please refer to Fig. 4, form the second test layer 220.The formation method of described second test layer comprises: form the second conductive layer (figure does not show), graphically described second conductive layer is to form the second test layer 220, described second test layer comprises multiple ring texture 230, each described ring texture comprises the second conducting block 231 being positioned at center and the 3rd conducting block 233 being positioned at outer shroud, is electrically connected to each other between described 3rd conducting block 233.The shape of cross section of described second conducting block 221 is non-square or non-circular, and the square or circular Zhou Chang great that the section girth specific area of described second conducting block 221 is identical.
Then, please refer to Fig. 4, filled media material 232 in described second conducting block 231 and the 3rd conducting block 233.
Then, please refer to Fig. 4, form the first conductive plunger 240.The formation method of described first conductive plunger comprises: on described second test layer, form the first interlayer dielectric layer (figure does not show), described first interlayer dielectric layer covers described second test layer; Patterned photoresist is formed, with described patterned photoresist for the first interlayer dielectric layer described in mask etching is to form multiple first through hole in described first interlayer dielectric layer; Multiple first conductive plunger 240 is formed, the position of described first conductive plunger 240 and the position one_to_one corresponding of described second conducting block in described first through hole.Described first conductive plunger 240 can be used for simulating the conductive plunger 120 in described chip under test 110.
In addition, and each ring texture 230 second conducting block 231 be electrically connected the first conductive plunger 240 can be one or more.Such as, in fig. 8, the first conductive plunger 240 be communicated with the second conducting block 231 of described ring texture 230 is 8.
Then, please refer to Fig. 4, form the first test layer 210.The formation method of described first test layer 210 comprises: on described first interlayer dielectric layer, form the first conductive layer (figure does not show); Graphically described first conductive layer forms the first test layer, and described first test layer comprises multiple the first conducting block be electrically connected to each other, and the position one_to_one corresponding of the position of described first conducting block and described first conductive plunger.
Adjacent described first test layer 210 and the second test layer 220 form a test structure, and described test structure is that stacked arrangement forms described chip test circuit.Described chip test circuit 200 can be arranged on the side of chip under test 100, and described chip under test 110 is all positioned at below weld pad (not shown).And the number of plies of described test structure can be determined by the number of plies of the metal level 110 of chip under test 100, the first test layer 210 wherein in each test structure and the second test layer 220 distinguish the layer of metal layer 110 of corresponding chip under test 100.
Then, please continue to refer to Fig. 4, after formation one deck test structure, formed and be positioned on this layer of test structure and before another layer of test structure adjacent with this layer of test structure, the second conductive plunger 250 can also be formed.The method of described second conductive plunger 250 comprises: form the second interlayer dielectric layer (figure does not show), described second interlayer dielectric layer covers described test structure; Described second interlayer dielectric layer forms patterned photoresist; With described patterned photoresist for the second interlayer dielectric layer described in mask etching forms multiple second through hole; In described second through hole, form described second conductive plunger 250, described second conductive plunger between adjacent two test structures, for being electrically connected the second conducting block of adjacent test structure and corresponding first conducting block.
Then, after forming the test structure being positioned at most top layer, before forming weld pad, the 3rd conductive plunger (figure does not show) can also be formed.The formation method of described 3rd conductive plunger comprises: form dielectric layer between third layer, between described third layer dielectric layer cover described in most top layer test structure; Between described third layer, dielectric layer forms patterned photoresist, with described patterned photoresist for dielectric layer between third layer described in mask etching is to form multiple third through-hole; In described third through-hole, form described 3rd conductive plunger, described 3rd conductive plunger is for being electrically connected described weld pad and the conducting block corresponding to described top layer test structure.
Below in conjunction with Figure 10 ~ 12, the chip detecting method utilizing said chip test circuit to test that the embodiment of the present invention provides is described in detail.
In an embodiment of the present invention, under the weld pad of chip under test side, the first chip test circuit and the second chip test circuit can be set.Described first chip test circuit can be the chip test circuit that aforementioned second test layer is positioned at above the first test layer, so, first test layer of described first chip test circuit is corresponding with the odd-level metal level of chip under test respectively, and namely the second test layer of described first chip test circuit is corresponding with the even level metal level of chip under test respectively.Described second chip test circuit can be the chip test circuit that aforementioned second test layer is positioned at below the first test layer, so, first test layer of described second chip test circuit is corresponding with the even level metal level of chip under test respectively, namely the second test layer of described first chip test circuit is corresponding with the odd-level metal level of chip under test respectively, finally comprehensively can analyze in conjunction with the inner case utilizing the test result of two chip test circuits to chip under test, draw further and judge more accurately.First be described for any one chip test circuit below.
First, provide test component, described test component has the first test lead A and the second test lead B.In embodiments of the present invention, described test component can be multimeter, but is not limited thereto.
Then, please refer to Figure 10, multiple first conducting block 211 of the first test layer 210 of one deck test structure in described test circuit 200 is electrically connected with described first test lead A, multiple 3rd conducting block 233 of the second test layer 220 of this layer of test structure is electrically connected with described second test lead B.
Then whether, monitoring described test component has electric current to pass through, and judges whether there is leakage current between the first test layer 210 of described test structure and the second test layer 220.
Then, according to described leakage current test result, judge whether the dielectric material of the second test layer be connected with described second test lead B occurs crack, namely, between first test layer and the second test layer of described test structure, there is leakage current, then there is crack in the dielectric material of the second test layer of described second test interface connection.
Because the layer of metal layer of described second test layer and chip under test is corresponding, for simulating corresponding metal level, and bear identical pressure with the metal level of described correspondence under being positioned at weld pad, therefore whether occur that crack can infer whether the metal level of described correspondence also occurs crack according to described second test layer medium material.
In addition, in embodiments of the present invention, due to the second metal level of described first chip test circuit and the even level metal level correspondence of chip under test, therefore, when above-mentioned test circuit is the first chip test circuit, can infer whether all even level metal levels occur crack according to above-mentioned test result.Due to the second metal level of described second chip test circuit and the odd-level metal level correspondence of chip under test, therefore, when described test circuit is the second chip test circuit, can infer whether all odd-level metal levels occur crack according to above-mentioned test result.
If use the first chip test circuit and the second chip test circuit to carry out testing all metal levels that just can test out chip under test whether occur crack simultaneously.
When described test circuit comprises multi-layer testing structure, can also test between adjacent test structure.
First, please refer to Figure 11, multiple 3rd conducting block 233 of the second test layer 220 of one deck test structure is electrically connected with described first test lead A, the first conducting block 211 of the first test layer 210 of the test structure adjacent with this layer of test structure is electrically connected with described second test lead B.
Then, whether have electric current pass through, thus judge whether there is leakage current between described test structure and adjacent test structure if monitoring described test component.
Then, according to described leakage current test result, judge whether the interlayer dielectric layer between described test structure and adjacent test structure occurs crack, namely, between described test structure and adjacent test structure, there is leakage current, then there is crack in the interlayer dielectric layer between described test structure and adjacent test structure.
Because described first test layer and the second test layer distinguish the layer of metal layer of corresponding chip under test, interlayer dielectric layer between so described adjacent test structure and the interlevel dielectric material between two metal levels in chip under test corresponding, therefore whether occur that crack can infer that the interlevel dielectric material of the chip under test corresponding with described interlayer dielectric layer also occurs crack according to the interlayer dielectric layer between described adjacent test structure.
In addition, please refer to Figure 12, when described chip test circuit comprises the second conductive plunger 250, the method utilizing described chip test circuit to carry out testing can comprise: be electrically connected with described first test lead A by multiple first conducting block 211 of the first test layer 210 of one deck test structure in described test circuit 200, is electrically connected by multiple first conducting block 211 of the first test layer 210 of the test structure adjacent with this layer of test structure with described second test lead B; Then, whether monitor described test component has leakage current to pass through.
Owing to being communicated with by the second conductive plunger 250 between the second test layer of this layer of test structure and the first test layer of test structure be adjacent, in fact so above-mentioned test process can test out between the first test layer of this layer of test structure and the second test layer whether occur leakage current, therefore according to above-mentioned leakage current test result, also can judge whether the dielectric material of the second test layer in this layer of test structure occurs crack.
In sum, embodiments of the invention have the following advantages:
In an embodiment of the present invention, metal level in chip under test is simulated by forming the first test layer and the second test layer, and simulate conductive plunger in chip under test by forming the first conductive plunger, therefore the structure of the more enough simulation chip under test more true to nature of chip test circuit that provides of the embodiment of the present invention, thus the actual inside situation of chip under test can be reacted more accurately.
Secondly, the shape of cross section of described second conducting block is non-square or non-circular, and the square or circular Zhou Chang great that the section girth specific area of described second conducting block is identical.That is, described second conducting block, when keeping cross-sectional area constant, has larger girth.So, the pressure that the first conducting block bears at the same pressure is constant, when same thickness and the contact area of the second and the 3rd described dielectric material between test structure larger.Therefore, when identical pressure, occur that the probability in crack is larger at the surface of contact of described second conducting block and dielectric material, thus improve the sensitivity of described test circuit further.
Again, and each ring texture second conducting block electrical connection the first conductive plunger can be one or more.When described second conducting block comprises multiple first conductive plunger, can when the first conductive plunger for when one bear pressure and be applied to multiple regions inside the described dielectric material by multiple first conductive plunger dispersion, make the dielectric material in test circuit be more prone to occur crack, thus improve the sensitivity of chip test circuit further.
Finally, the layer of metal layer of the first test layer in described chip test circuit and the corresponding chip under test of the second test layer difference, by between described first test layer and the second test layer of same test structure and test between adjacent test structure, then accurately can judge that the position damaged appears in chip under test according to its test result, thus improve the precision of chip testing.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. a formation method for chip test circuit, is characterized in that, comprising: form at least one deck test structure, and described at least one deck test structure is stacked arrangement;
The formation method of every one deck test structure comprises:
Form the first conductive layer;
Graphically described first conductive layer forms the first test layer, and described first test layer comprises multiple the first conducting block be electrically connected to each other;
Described first test layer forms the first interlayer dielectric layer;
Multiple first conductive plunger is formed, the position of described first conductive plunger and the position one_to_one corresponding of described first conducting block in described first interlayer dielectric layer;
Form the second conductive layer, cover described first interlayer dielectric layer and described first conductive plunger;
Graphically described second conductive layer forms the second test layer, described second test layer comprises multiple ring texture, the position one_to_one corresponding of described ring texture and described first conducting block, each described ring texture comprises the second conducting block being positioned at center and the 3rd conducting block being positioned at outer shroud, described second conducting block is positioned at accordingly on described first conductive plunger, is electrically connected to each other between described 3rd conducting block; And
Filled media material in described second conducting block and the 3rd conducting block,
Or the formation method of every one deck test structure comprises:
Form the second conductive layer, graphically described second conductive layer is to form the second test layer, described second test layer comprises multiple ring texture, and each described ring texture comprises the second conducting block being positioned at center and the 3rd conducting block being positioned at outer shroud, is electrically connected to each other between described 3rd conducting block;
Filled media material in described second conducting block and the 3rd conducting block;
Described second layer test layer forms the first interlayer dielectric layer;
Multiple first conductive plunger is formed, the position of described first conductive plunger and the position one_to_one corresponding of described second conducting block in described first interlayer dielectric layer;
And the first conductive layer is formed on described first interlayer dielectric layer;
Graphically described first conductive layer forms the first test layer, and described first test layer comprises multiple the first conducting block be electrically connected to each other, and with the position one_to_one corresponding of described first conductive plunger;
Wherein, every one deck first test layer and every one deck second test layer all distinguish the layer of metal layer of corresponding chip under test.
2. the formation method of chip test circuit as claimed in claim 1, is characterized in that, the square or circular Zhou Chang great that the section girth specific area of described second conducting block is identical.
3. the formation method of chip test circuit as claimed in claim 1, it is characterized in that, after formation one deck test structure, formed and to be positioned on this layer of test structure and before another layer of test structure adjacent with this layer of test structure, also comprise: form the second interlayer dielectric layer, described second interlayer dielectric layer covers this layer of test structure, the second conductive plunger is formed in described second interlayer dielectric layer, described second conductive plunger between adjacent two layers test structure, for being electrically connected the second conducting block of adjacent test structure and corresponding first conducting block.
4. the formation method of chip test circuit as claimed in claim 1, it is characterized in that, also comprise: after forming the test structure being positioned at most top layer, before forming weld pad, also comprise: form dielectric layer between third layer, between described third layer dielectric layer cover described in the test structure of most top layer; Between described third layer, form multiple 3rd conductive plunger in dielectric layer, described 3rd conductive plunger is for being electrically connected described weld pad and the conducting block corresponding to the test structure of described most top layer.
5. the formation method of chip test circuit as claimed in claim 1, it is characterized in that, the first conductive plunger be connected with each second conducting block is one or more.
6. the formation method of chip test circuit as claimed in claim 1, it is characterized in that, the cross-sectional area of described first conductive plunger is 1/4 ~ 3/4 of described second conducting block.
7. the method for testing of a chip test circuit, described chip test circuit comprises: at least one deck test structure, described at least one deck test structure is stacked arrangement, and be formed with interlayer dielectric layer between adjacent test structure, every one deck test structure comprises: the first test layer, and described first test layer comprises multiple the first conducting block be electrically connected to each other; Second test layer, described second test layer is positioned at below or the top of described first test layer, and described second test layer comprises multiple ring texture, described ring texture and described first conducting block one_to_one corresponding, each described ring texture comprises the second conducting block at center and the 3rd conducting block at outer shroud, dielectric material between described second conducting block and the 3rd conducting block, and is electrically connected to each other between multiple described 3rd conducting block; And multiple first conductive plunger, described first conductive plunger is between described first test layer and the second test layer, for being electrically connected described first conducting block and second conducting block corresponding with it, every one deck first test layer and every one deck second test layer all distinguish the layer of metal layer of corresponding chip under test, it is characterized in that, the method for testing of described chip test circuit comprises:
There is provided test component, described test component has the first test lead and the second test lead;
Multiple first conducting block of the first test layer of one deck test structure is electrically connected with described first test lead;
Multiple 3rd conducting blocks of the second test layer of this layer of test structure are electrically connected with described second test lead;
Whether have electric current pass through, judge whether there is leakage current between the first test layer of described test structure and the second test layer if monitoring described test component;
According to leakage current test result, judge whether the dielectric material of the second test layer be connected with described second test lead occurs crack, thus infer whether the metal level of the chip under test corresponding with described second test layer occurs crack.
8. method of testing as claimed in claim 7, is characterized in that, also comprise:
Multiple 3rd conducting blocks of the second test layer of one deck test structure are electrically connected with described first test lead;
Multiple first conducting block of the first test layer of the test structure adjacent with this layer of test structure is electrically connected with described second test lead;
Whether have electric current pass through, judge whether there is leakage current between described test structure and adjacent test structure if monitoring described test component;
According to described leakage current test result, judge whether the interlayer dielectric layer between described test structure and adjacent test structure occurs crack, thus infer whether the interlevel dielectric material of the chip under test corresponding with described interlayer dielectric layer occurs crack.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210313499.2A CN103630825B (en) | 2012-08-29 | 2012-08-29 | Chip test circuit and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210313499.2A CN103630825B (en) | 2012-08-29 | 2012-08-29 | Chip test circuit and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103630825A CN103630825A (en) | 2014-03-12 |
| CN103630825B true CN103630825B (en) | 2016-01-06 |
Family
ID=50212078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210313499.2A Active CN103630825B (en) | 2012-08-29 | 2012-08-29 | Chip test circuit and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103630825B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107037699B (en) * | 2016-02-03 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of mark structure |
| CN113823576B (en) * | 2020-06-18 | 2023-07-04 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor test structure and forming method thereof |
| CN112904180B (en) * | 2021-01-22 | 2022-04-19 | 长鑫存储技术有限公司 | Chip test board and chip test method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404122A (en) * | 2001-07-26 | 2003-03-19 | 联华电子股份有限公司 | Detection method of electric defect in inner conducting layer of tested area |
| CN101312181A (en) * | 2007-05-24 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semiconductor chip, integrated circuit structure and semi-conductor wafer |
| CN101615606A (en) * | 2008-06-26 | 2009-12-30 | 台湾积体电路制造股份有限公司 | Integrated circuit (IC) chip weld pad and manufacture method thereof and comprise the integrated circuit of this weld pad |
| CN101622545A (en) * | 2007-02-22 | 2010-01-06 | 泰拉丁公司 | Design-for-test micro probe |
| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100638042B1 (en) * | 2004-12-28 | 2006-10-23 | 동부일렉트로닉스 주식회사 | Test Pattern for Measuring Kelvin Resistance and Semiconductor device Including Such a Pattern |
| US7498680B2 (en) * | 2006-12-06 | 2009-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test structure |
| US7939348B2 (en) * | 2007-08-28 | 2011-05-10 | Chartered Semiconductor Manufacturing, Ltd. | E-beam inspection structure for leakage analysis |
-
2012
- 2012-08-29 CN CN201210313499.2A patent/CN103630825B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404122A (en) * | 2001-07-26 | 2003-03-19 | 联华电子股份有限公司 | Detection method of electric defect in inner conducting layer of tested area |
| CN101622545A (en) * | 2007-02-22 | 2010-01-06 | 泰拉丁公司 | Design-for-test micro probe |
| CN101312181A (en) * | 2007-05-24 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semiconductor chip, integrated circuit structure and semi-conductor wafer |
| CN101615606A (en) * | 2008-06-26 | 2009-12-30 | 台湾积体电路制造股份有限公司 | Integrated circuit (IC) chip weld pad and manufacture method thereof and comprise the integrated circuit of this weld pad |
| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103630825A (en) | 2014-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9287184B2 (en) | Apparatuses and methods for die seal crack detection | |
| CN102299139B (en) | Semiconductor integrated circuit | |
| KR101975541B1 (en) | TSV structure of semiconductor memory device and testing method thereof | |
| US20120018723A1 (en) | Structure and method for testing through-silicon via (tsv) | |
| CN103399225A (en) | Test structure containing transferring plate | |
| US9153507B2 (en) | Semiconductor package with improved testability | |
| CN103630825B (en) | Chip test circuit and forming method thereof | |
| CN103165577A (en) | Semiconductor detection structure and detection method | |
| US20160322265A1 (en) | Method and apparatus for detection of failures in under-fill layers in integrated circuit assemblies | |
| CN103346142A (en) | Test key structure and method for monitoring etching capacity of contact holes in etching process | |
| CN203377200U (en) | Chip package testing structure | |
| CN105489581B (en) | Semiconductor structure and preparation method thereof | |
| CN101750563B (en) | Structure for detecting short circuit of through holes or contact holes in semiconductor device | |
| KR20060058953A (en) | Packaged semiconductor die and manufacturing method thereof | |
| US9134366B2 (en) | Method for forming a packaged semiconductor device | |
| JP2008028274A (en) | Manufacturing method for semiconductor device | |
| JP2011039023A (en) | Test method of substrate | |
| CN203895444U (en) | Contact hole bridging test structure | |
| CN202957239U (en) | Structure for detecting electric leakage of packaged chip | |
| CN203038917U (en) | CPI test structure | |
| CN104282596B (en) | The forming method of semiconductor test tool | |
| TW201421038A (en) | Method for testing interposer | |
| CN103531443B (en) | Semiconductor devices and manufacture method thereof | |
| CN101819940B (en) | Method and structure for testing wafer | |
| US7517723B2 (en) | Method for fabricating a flip chip system in package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |