CN103630825A - Chip test circuit and formation method thereof - Google Patents
Chip test circuit and formation method thereof Download PDFInfo
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- CN103630825A CN103630825A CN201210313499.2A CN201210313499A CN103630825A CN 103630825 A CN103630825 A CN 103630825A CN 201210313499 A CN201210313499 A CN 201210313499A CN 103630825 A CN103630825 A CN 103630825A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The invention provides a chip test circuit and a formation method thereof and a test method using the test circuit. The chip test circuit comprises at least one layer of test structure. Each layer of test structure comprises a first test layer, a second test layer, and multiple first conductive plugs. The first test layer comprises multiple first conductive blocks which are electrically interconnected. The second test layer is arranged below or above the first test layer, and the second test layer comprises multiple ring-shaped structures which are corresponding to the first conductive blocks in a one-to-one way. Each ring-shaped structure comprises a second conductive block arranged in the center, a third conductive block arranged outside the ring, and a dielectric material arranged between the second conductive block and the third conductive block. The multiple first conductive plugs are used for being electrically connected with the first conductive blocks and the second conductive blocks which are corresponding to the first conductive blocks. According to the chip test circuit, the practical structure of a chip can be reflected and precision of a test before chip packaging can be enhanced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of chip test circuit and forming method thereof.
Background technology
In ic chip package, generally by bonding wire, realize the connection of chip and outside port.Fig. 1 is the diagrammatic cross-section of a chip-packaging structure in prior art.As shown in Figure 1, one end of bonding wire 15 is beaten on wire pad 14 by throwing device, is connected with chip 13, and other one end of bonding wire 15 is connected to outside port 12, and therefore, described bonding wire 15 can be electrically connected to outside port 12 by described chip 13.After the above-mentioned routing process of process, the described chip being communicated with by bonding wire 15 13 is just placed in mold 11, and by injecting sealing resin 16, by described chip 13 encapsulation.
Yet in above-mentioned routing process, described throwing device institute applied pressure may make to occur in chip dielectric layer crack and the bonding unstable problem of each metal level.Fig. 2 is the partial enlarged drawing of part shown in Fig. 1 dotted line, and throwing device is when 15 dozens of described bonding wires are on wire pad 14, and its applied pressure will affect the chip structure of 10 belows, pad zone.On the other hand, along with the size of semiconductor devices is dwindled, low k dielectric materials is inevitably used in the manufacture process of chip, because the elasticity coefficient of low k dielectric materials is less and adhesiveness is poor, respectively there is dielectric layer crack and the bonding unstable possibility of each metal level in the chip structure that has so just more increased 10 belows, described pad zone when being under pressure.
If there is the bonding unstable problem of dielectric layer crack and each metal level thereof in chip, just mean that this chip damages, and can not be used.In order not affect the yield rate of product, the chip of described damage need to be detected before encapsulation.
Because crack appears in the dielectric layer in chip, just there will be short circuit phenomenon, thereby produce leakage current, so we can judge whether chip internal damages by chip being carried out to leakage current test.In prior art, be generally, by probe, chip is encapsulated to front test.As patent publication No. is CN101622545A and within open day, is that the Chinese patent literature on January 6th, 2010 discloses a kind of probe detection device.Before utilizing probe to carry out the encapsulation of chip, test generally comprises following steps: by probe and being connected of wire pad test signal being introduced to chip internal; Then, make the flow through test circuit of chip internal of test signal, then the test pin by chip flows out, and the test signal by this outflow judges that whether chip is damaged.Fig. 3 is the cross-sectional view of the test circuit before the encapsulation of prior art chips, and with reference to figure 3, this test circuit is metal construction and the dielectric material of simple simulation chip under test just, can not well react the chip under test of the high complexity of high integration.
Therefore, a kind of new chip test circuit and method of testing thereof need to be proposed, the practical structures of simulation chip under test that can be more true to nature, thus improve the precision of chip testing.
Summary of the invention
The problem that the present invention solves is to provide a kind of chip test circuit and method of testing thereof, can not only reflect the practical structures of chip under test, and can avoid can not reflecting preferably because of existing test circuit the test judgement that the practical structures of chip leads to errors.
For addressing the above problem, the embodiment of the present invention provides a kind of chip test circuit, comprise: one deck test structure at least, described at least one deck test structure is stacked arrangement, and be formed with interlayer dielectric layer between adjacent test structure, every one deck test structure comprises: the first test layer, and described the first test layer comprises the first conducting block of a plurality of mutual electrical connections; The second test layer, described the second test layer is positioned at below or the top of described the first test layer, and described the second test layer comprises a plurality of ring texturees, described ring texture and described the first conducting block are corresponding one by one, described in each, ring texture comprises at second conducting block at center with at the 3rd conducting block of outer shroud, dielectric material between described the second conducting block and the 3rd conducting block, and is mutually electrically connected between a plurality of described the 3rd conducting block; And a plurality of the first conductive plungers, described the first conductive plunger is between described the first test layer and the second test layer, for being electrically connected to described the first conducting block and second conducting block corresponding with it, every one deck the first test layer and every one deck the second test layer are all distinguished the layer of metal layer of corresponding chip under test.
Alternatively, the identical square or circular Zhou Chang great of the section girth specific area of described the second conducting block.
Alternatively, described chip test circuit also comprises: a plurality of the second conductive plungers, and between adjacent two test structures, for being electrically connected to the second conducting block and corresponding first conducting block of adjacent test structure.
Alternatively, described chip test circuit also comprises: a plurality of the 3rd conductive plungers, described the 3rd conductive plunger weld pad and and the hithermost test layer of described weld pad between, for be electrically connected to weld pad and with the conducting block of the hithermost test layer of described weld pad.
Alternatively, the first conductive plunger being connected with each second conducting block is one or more.
Alternatively, the cross-sectional area of described the first conductive plunger is 1/4 ~ 3/4 of described the second conducting block.
The embodiment of the present invention also provides a kind of formation method of chip test circuit, comprising: form at least one deck test structure, described at least one deck test structure is stacked arrangement; The formation method of every one deck test structure comprises: form the first conductive layer; Graphical described the first conductive layer forms the first test layer, and described the first test layer comprises the first conducting block of a plurality of mutual electrical connections; On described the first test layer, form the first interlayer dielectric layer; In described the first interlayer dielectric layer, form a plurality of the first conductive plungers, the position of described the first conductive plunger is corresponding one by one with the position of described the first conducting block; Form the second conductive layer, cover described the first interlayer dielectric layer and described the first conduction plug; Graphical described the second conductive layer forms the second test layer, described the second test layer comprises a plurality of ring texturees, the position of described ring texture and described the first conducting block is corresponding one by one, described in each, ring texture comprises the second conducting block that is positioned at center and the 3rd conducting block that is positioned at outer shroud, described the second conducting block is positioned on corresponding described the first conduction plug, between described the 3rd conducting block, is mutually electrically connected to; And in described the second conducting block and the 3rd conducting block filled media material, or, the formation method of every one deck test structure comprises: form the second conductive layer, graphical described the second conductive layer is to form the second test layer, described the second test layer comprises a plurality of ring texturees, described in each, ring texture comprises the second conducting block that is positioned at center and the 3rd conducting block that is positioned at outer shroud, between described the 3rd conducting block, is mutually electrically connected to; Filled media material in described the second conducting block and the 3rd conducting block; On described second layer test layer, form the first interlayer dielectric layer; In described the first interlayer dielectric layer, form a plurality of the first conductive plungers, the position of described the first conductive plunger is corresponding one by one with the position of described the second conducting block; And form the first conductive layer on described the first interlayer dielectric layer; Graphical described the first conductive layer forms the first test layer, and described the first test layer comprises the first conducting block of a plurality of mutual electrical connections, and corresponding one by one with the position of described the first conductive plunger; Wherein, every one deck the first test layer and every one deck the second test layer are all distinguished the layer of metal layer of corresponding chip under test.
Alternatively, the identical square or circular Zhou Chang great of the section girth specific area of described the second conducting block.
Alternatively, after forming one deck test structure, formation be positioned on this layer of test structure and another layer test structure adjacent with this layer of test structure before, the formation method of described chip test circuit also comprises: form the second interlayer dielectric layer, described the second interlayer dielectric layer covers this layer of test structure, in described the second interlayer dielectric layer, form the second conductive plunger, described the second conductive plunger is between adjacent two layers test structure, for being electrically connected to the second conducting block and corresponding first conducting block of adjacent test structure.
Alternatively, form after the test structure be positioned at top layer, before forming weld pad, the formation method of described chip test circuit also comprises: form the 3rd interlayer dielectric layer, top layer test structure described in described the 3rd interlayer dielectric layer covers; In described the 3rd interlayer dielectric layer, form a plurality of the 3rd conductive plungers, described the 3rd conductive plunger be used for being electrically connected to described weld pad and with the corresponding conducting block of described top layer test structure.
Alternatively, the first conductive plunger being connected with each second conducting block is one or more.
Alternatively, the cross-sectional area of described the first conductive plunger is 1/4 ~ 3/4 of described the second conducting block.
The embodiment of the present invention also provides a kind of method of testing of utilizing said chip test circuit, comprising: test component is provided, and described test component has the first test lead and the second test lead; A plurality of first conducting blocks of the first test layer of one deck test structure are electrically connected to described the first test lead; A plurality of the 3rd conducting blocks of the second test layer of this layer of test structure are electrically connected to described the second test lead; Whether have electric current pass through, judge between the first test layer of described test structure and the second test layer whether have leakage current if monitoring described test component; According to described leakage current test result, whether the dielectric material of the second test layer that judgement is connected with described the second test lead there is crack, thereby infers whether the metal level of the chip under test corresponding with described the second test layer occurs crack.
Alternatively, described method of testing also comprises: described test is electrically connected to a plurality of the 3rd conducting blocks of the second test layer of one deck test structure with described the first test lead; A plurality of first conducting blocks of the first test layer of the test structure adjacent with this layer of test structure are electrically connected to described the second test lead; Whether have electric current pass through, judge between described test structure and adjacent test structure whether have leakage current if monitoring described test component; According to described leakage current test result, judge whether the interlayer dielectric layer between described test structure and adjacent test structure occurs crack, thereby infer whether the interlevel dielectric material of the chip under test corresponding with described interlayer dielectric layer occurs crack.
Compared with prior art, embodiments of the invention have the following advantages:
In an embodiment of the present invention, by forming the first test layer and the second test layer is simulated the metal level in chip under test, and simulate the conductive plunger in chip under test by forming the first conductive plunger, therefore the chip test circuit that the embodiment of the present invention provides can be more true to nature the structure of simulation chip under test, thereby can react more accurately the actual inside situation of chip under test.
Secondly, the first test layer in described chip test circuit and the second test layer be the layer of metal layer of corresponding chip under test respectively, by between described the first test layer at same test structure and the second test layer and carry out leakage current test between adjacent test structure, then which layer metal level the damage that can accurately judge chip under test according to its test result appears at, thereby has improved the precision of chip testing.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art chips encapsulation;
Fig. 2 is the structural representation that amplify the part of Fig. 1;
Fig. 3 is the cross-sectional view of the test circuit before the encapsulation of prior art chips;
Fig. 4 is the cross-sectional view of the chip test circuit of one embodiment of the invention;
Fig. 5 is that Fig. 4 is along the cross sectional representation of AA ' direction;
Fig. 6 is that Fig. 4 is along the cross sectional representation of BB ' direction;
Fig. 7 is the cross-sectional structure schematic diagram of ring texture of the second test layer of one embodiment of the invention;
Fig. 8 is the xsect contrast schematic diagram of two kinds of difform second conductive layers;
Fig. 9 is the schematic diagram of the chip test circuit of another embodiment of the present invention;
Figure 10 is the schematic diagram of the chip detecting method of one embodiment of the invention;
Figure 11 is the schematic diagram of the chip detecting method of another embodiment of the present invention; And
Figure 12 is the schematic diagram of the chip detecting method of another embodiment of the present invention.
Embodiment
From background technology, according to the test result of existing test circuit, can not effectively judge the damaged condition of chip under test.Inventor finds after deliberation, and along with development and the improvement of integrated circuit, the metal connecting line of chip internal is more and more meticulousr, and chip test circuit of the prior art can not reflect the integrated circuit complexity after improvement.The structure of chip build-in test circuit plays key effect in test process, only in the situation that the inner structure of the structure of described test circuit emulation preferably chip under test can judge that whether the inner structure of chip under test is damaged according to the situation of described test circuit damage.Furthermore, if make the actual internal structure that test circuit can not only emulation chip under test, and the damaged condition of amplification chip under test practical structures that can be suitable, the sensitivity of such test circuit is just relatively high.
For the problems referred to above, embodiments of the invention provide a kind of formation method of chip test circuit, described chip test circuit and the method for testing of utilizing described test circuit to test.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here, implement, so the present invention has not been subject to the restriction of following public specific embodiment.
Lower mask body is in conjunction with Fig. 4 ~ 8, and the chip test circuit that the embodiment of the present invention is provided is described in detail.
Fig. 4 is the cross-sectional view of the chip test circuit of one embodiment of the invention.Please refer to Fig. 4, described chip test circuit 200 comprises at least one deck test structure, every one deck test structure comprises the first test layer 210 and the second test layer 220, and described at least one deck test structure is stacked arrangement, and between adjacent test structure, is formed with interlayer dielectric layer (figure does not show).
In embodiments of the present invention, as shown in Figure 4, described chip test circuit 200 can be arranged on a side of chip under test 100, and described chip under test 100 is all positioned at weld pad (not shown) below.And the number of plies of described test structure can be determined by the number of plies of the metal level 110 of chip under test 100, wherein the first test layer 210 in each test structure and the second test layer 220 are distinguished the layer of metal layer 110 of corresponding chip under test 100.If the metal level of described chip under test is n layer, and n is even number, and so described test circuit comprises the described test structure of n/2 layer; If the metal level of described chip under test is n layer, and n is odd number, and so described test circuit comprises the described test structure of n-1/2 layer and independent one deck the first test layer or the second test layer.In order to simplify, the chip under test of only take in Fig. 4 comprises four layers of metal level and describes as example.
Please continue to refer to Fig. 4, described the first test layer 210 comprises a plurality of the first conducting blocks 211.Fig. 5 is that Fig. 4 is along the schematic cross-section of AA ' direction.As shown in Figure 5, between described a plurality of the first conducting blocks 211, be to be mutually electrically connected to, so that a follow-up test lead that described a plurality of the first conducting blocks 211 is electrically connected to leakage current test component in test process.
In embodiments of the present invention, described the second test layer 220 can be positioned at below or the top of described the first test layer 210.For the purpose of simplifying the description, the below that second test layer 220 of only take below is positioned at described the first test layer describes as example.
Please continue to refer to Fig. 4, described the second test layer 220 comprises a plurality of ring texturees 230, and described ring texture 230 and described the first conducting block 211 are corresponding one by one.
Fig. 6 is that Fig. 4 is along the cross sectional representation of BB ' direction.As shown in Figure 4 and Figure 6, each ring texture 230 comprises the second conducting block 231 that is positioned at center and the 3rd conducting block 233 that is positioned at outer shroud, and the dielectric material 232 between described the second conducting block 231 and the 3rd conducting block 233.In addition, between a plurality of described the 3rd conducting block 233 in same the second test layer 220, be mutually electrically connected to, to facilitate another test port that the 3rd conducting block 233 of the second test layer 220 is all electrically connected to leakage current test component in follow-up test process.
In an embodiment of the present invention, the material of the dielectric material 232 between described the second conducting block 231 and the second conducting block 233 can be identical with the interlevel dielectric material of chip under test, also can adopt other dielectric materials that more easily produce crack under pressure, to improve the sensitivity of described chip test circuit.
It should be noted that, in an embodiment of the present invention, the xsect of the second conducting block 221 (described xsect perpendicular to follow-up by the bearing of trend of the first conductive plunger of describing) is shaped as non-square or non-circular, and the identical square or circular Zhou Chang great of the section girth specific area of described the second conducting block 221.Can infer thus, described the second conducting block is in the situation that keeping cross-sectional area constant, have larger girth, the pressure that so described the first conducting block bears under uniform pressure is constant, but larger with the contact area of described dielectric material 232 in the situation of described the first conducting block same thickness.
Take below described the second conducting block xsect as square frame-shaped as a comparison object be elaborated.As shown in Figure 7, the left side is the cross sectional representation of the loop configuration 230 ' of the xsect of the second conducting block 231 ' while being square frame-shaped, the right is the cross sectional representation of the xsect of the second conducting block 231 loop configuration 230 while being irregularly shaped, wherein, the cross-sectional area of the second conducting block 231 ' is identical with the cross-sectional area of the second conducting block 231, that is to say that girth is that the area that described irregular figure that area and the described girth of the square encirclement of X is Y surrounds equates, this pressure that just means that described the second conducting block 231 ' and the second conducting block 231 are subject under uniform pressure equates, but, the girth Y of described irregular figure is larger than described square girth X, when described ring texture 230 ' is equal with ring texture 230 thickness, described in the contact area rate of described the second conducting block 231 ' and dielectric material 232 ', the second conducting block 231 and dielectric material 232 contacts area want large, therefore, in the situation of identical pressure, surface of contact at described the second conducting block 231 and dielectric material 232 occurs that the probability in crack is larger, thereby further improve the sensitivity of described test circuit.
Please continue to refer to Fig. 4, described test circuit 200 also comprises a plurality of the first conductive plungers 240, described the first conductive plunger 240 is between described the first test layer 210 and the second test layer 220, for being electrically connected to described the first conducting block 211 and second conducting block 231 corresponding with it.
It should be noted that, as shown in Figure 4, described the first conductive plunger 240 can be used for simulating the conductive plunger 120 in described chip under test 100.In embodiments of the present invention, the sectional area of described the first conductive plunger 240 is 1/4 ~ 3/4 of described first conducting block 231 areas, the xsect of described the first conductive plunger 240 can be any figure applicatory, and to be circles describe as example the xsect of take described the first conductive plunger 240 at this.
In addition, and the first conductive plunger 240 of being electrically connected to of the second conducting block 231 of each ring texture 230 can be one or more.For example, in Fig. 8, and the first conductive plunger 240 that the second conducting block 231 of described ring texture 230 is communicated with is 8.It should be noted that, while comprising a plurality of the first conductive plunger 240 on described the second conducting block 231, can when the first conductive plunger 240 is one the pressure that bears by a plurality of the first conductive plungers 240, disperse to be applied to a plurality of regions near described dielectric material 232 inner sides, make the dielectric material in test circuit be more prone to occur crack, thereby further improve the sensitivity of chip test circuit.
Please continue to refer to Fig. 4, described chip test circuit 200 can also comprise a plurality of the second conductive plungers 250, between adjacent two test structures, for being electrically connected to the second conducting block 231 and corresponding first conducting block 211 of adjacent test structure.
In embodiments of the present invention, when in described test structure, the second test layer 220 is positioned at the first test layer 210 below, described the second conductive plunger 250 is for being electrically connected to the second conducting block 231 and this layer of adjacent corresponding first conducting block 211 of test structure in test structure below of one deck test structure, when in described test structure, the second test layer 220 is positioned at the first test layer 210 top, described the second conductive plunger 250 is for being electrically connected to the first conducting block 211 and this layer of adjacent corresponding second conducting block 231 of test structure in test structure below of one deck test structure.
Please continue to refer to Fig. 4, described chip test circuit 200 can also comprise a plurality of the 3rd conductive plungers (figure does not show), described the 3rd conductive plunger weld pad and and the hithermost test layer of described weld pad between, for be electrically connected to weld pad and with the conducting block of the hithermost test layer of described weld pad.
Again specifically in conjunction with Fig. 4 and Fig. 9, the formation method of the chip test circuit that the embodiment of the present invention is provided is described in detail below.As mentioned above, described the second test layer can be positioned at below or the top of described the first test layer, below the formation method of described test circuit while will be first describing above described the second test layer is positioned at described the first test layer.
First, please refer to Fig. 9, form the first test layer 210.The formation method of described the first test layer 210 comprises: form the first conductive layer (figure does not show); Graphical described the first conductive layer is to form described the first test layer 210, and described the first test layer comprises the first conducting block 211 of a plurality of mutual electrical connections.
Then, please refer to Fig. 9, form the first conductive plunger 240.The formation method of described the first conductive plunger 240 comprises: on described the first test layer, form the first interlayer dielectric layer (figure does not show), described the first interlayer dielectric layer covers described the first test layer; On in described the first interlayer dielectric layer, form patterned photoresist, take described patterned photoresist as the first interlayer dielectric layer described in mask etching is to form a plurality of the first through holes; In described the first through hole, form a plurality of the first conductive plungers 240, the position of described the first conductive plunger 240 is corresponding one by one with the position of described the first conducting block.Described the first conductive plunger 240 can be used for simulating the conductive plunger 120 in described chip under test 100.
In addition, and the first conductive plunger 240 of being electrically connected to of the second conducting block 231 of each ring texture 230 can be one or more.
Then, please refer to Fig. 9, form the second test layer 220.The formation method of described the second test layer 220 comprises: form the second conductive layer (figure does not show), cover described the first interlayer dielectric layer and described the first conductive plunger; Graphical described the second conductive layer forms the second test layer 220, described the second test layer 220 comprises a plurality of ring texturees 230, the position of described ring texture 230 and described the first conducting block 210 is corresponding one by one, described in each, ring texture 220 comprises the second conducting block 231 that is positioned at center and the 3rd conducting block 233 that is positioned at outer shroud, described the second conducting block 231 is positioned on corresponding described the first conductive plunger 221, between described the 3rd conducting block 233, is mutually electrically connected to.In an embodiment of the present invention, the shape of cross section of described the second conducting block 221 is non-square or non-circular, and the identical square or circular Zhou Chang great of the section girth specific area of described the second conducting block 221.
Then, please refer to Fig. 9, filled media material 232 in described the second conducting block 231 and the 3rd conducting block 233.
Adjacent described the first test layer 210 and the second test layer 220 form a test structure, and described at least one, test structure is stacked arrangement and forms described chip test circuit.As previously mentioned, in embodiments of the present invention, described chip test circuit 200 can be arranged on chip under test 100 1 sides, and described chip under test is all positioned at weld pad below.And the number of plies of described test structure can be determined by the number of plies of the metal level of chip under test, wherein the first test layer 210 in each test structure and the second test layer 220 are distinguished the layer of metal layer of corresponding chip under test.
Then, please continue to refer to Fig. 9, after forming one deck test structure, form be positioned on this layer of test structure and another layer test structure adjacent with this layer of test structure before, can also form the second conductive plunger 250.The method of described the second conductive plunger 250 comprises: form the second interlayer dielectric layer (figure does not show), described the second interlayer dielectric layer covers described test structure; On described the second interlayer dielectric layer, form patterned photoresist; Take described patterned photoresist as the second interlayer dielectric layer described in mask etching is to form a plurality of the second through holes; In described the second through hole, form described the second conductive plunger 250, described the second conductive plunger is between adjacent two test structures, for being electrically connected to the second conducting block and corresponding first conducting block of adjacent test structure.
Then, form after the test structure be positioned at top layer, before forming weld pad, can also form the 3rd conductive plunger (figure does not show).The formation method of described the 3rd conductive plunger comprises: form the 3rd interlayer dielectric layer, top layer test structure described in described the 3rd interlayer dielectric layer covers; On described the 3rd interlayer dielectric layer, form patterned photoresist, take described patterned photoresist as the 3rd interlayer dielectric layer described in mask etching is to form a plurality of third through-holes; In described third through-hole, form described the 3rd conductive plunger, described the 3rd conductive plunger be used for being electrically connected to described weld pad and with the corresponding conducting block of described top layer test structure.
The above formation method of having described the described test circuit when described the second test layer is positioned at described the first test layer below will be specifically described below.
First, please refer to Fig. 4, form the second test layer 220.The formation method of described the second test layer comprises: form the second conductive layer (figure does not show), graphical described the second conductive layer is to form the second test layer 220, described the second test layer comprises a plurality of ring texturees 230, described in each, ring texture comprises the second conducting block 231 that is positioned at center and the 3rd conducting block 233 that is positioned at outer shroud, between described the 3rd conducting block 233, is mutually electrically connected to.The shape of cross section of described the second conducting block 221 is non-square or non-circular, and the identical square or circular Zhou Chang great of the section girth specific area of described the second conducting block 221.
Then, please refer to Fig. 4, filled media material 232 in described the second conducting block 231 and the 3rd conducting block 233.
Then, please refer to Fig. 4, form the first conductive plunger 240.The formation method of described the first conductive plunger comprises: on described the second test layer, form the first interlayer dielectric layer (figure does not show), described the first interlayer dielectric layer covers described the second test layer; On in described the first interlayer dielectric layer, form patterned photoresist, take described patterned photoresist as the first interlayer dielectric layer described in mask etching is to form a plurality of the first through holes; In described the first through hole, form a plurality of the first conductive plungers 240, the position of described the first conductive plunger 240 is corresponding one by one with the position of described the second conducting block.Described the first conductive plunger 240 can be used for simulating the conductive plunger 120 in described chip under test 110.
In addition, and the first conductive plunger 240 of being electrically connected to of the second conducting block 231 of each ring texture 230 can be one or more.For example, in Fig. 8, and the first conductive plunger 240 that the second conducting block 231 of described ring texture 230 is communicated with is 8.
Then, please refer to Fig. 4, form the first test layer 210.The formation method of described the first test layer 210 comprises: on described the first interlayer dielectric layer, form the first conductive layer (figure does not show); Graphical described the first conductive layer forms the first test layer, and described the first test layer comprises the first conducting block of a plurality of mutual electrical connections, and the position of described the first conducting block is corresponding one by one with the position of described the first conductive plunger.
Adjacent described the first test layer 210 and the second test layer 220 form a test structure, and described test structure is stacked arrangement and forms described chip test circuit.Described chip test circuit 200 can be arranged on a side of chip under test 100, and described chip under test 110 is all positioned at weld pad (not shown) below.And the number of plies of described test structure can be determined by the number of plies of the metal level 110 of chip under test 100, wherein the first test layer 210 in each test structure and the second test layer 220 are distinguished the layer of metal layer 110 of corresponding chip under test 100.
Then, please continue to refer to Fig. 4, after forming one deck test structure, form be positioned on this layer of test structure and another layer test structure adjacent with this layer of test structure before, can also form the second conductive plunger 250.The method of described the second conductive plunger 250 comprises: form the second interlayer dielectric layer (figure does not show), described the second interlayer dielectric layer covers described test structure; On described the second interlayer dielectric layer, form patterned photoresist; The described patterned photoresist of take forms a plurality of the second through holes as the second interlayer dielectric layer described in mask etching; In described the second through hole, form described the second conductive plunger 250, described the second conductive plunger is between adjacent two test structures, for being electrically connected to the second conducting block and corresponding first conducting block of adjacent test structure.
Then, form after the test structure be positioned at top layer, before forming weld pad, can also form the 3rd conductive plunger (figure does not show).The formation method of described the 3rd conductive plunger comprises: form the 3rd interlayer dielectric layer, top layer test structure described in described the 3rd interlayer dielectric layer covers; On described the 3rd interlayer dielectric layer, form patterned photoresist, take described patterned photoresist as the 3rd interlayer dielectric layer described in mask etching is to form a plurality of third through-holes; In described third through-hole, form described the 3rd conductive plunger, described the 3rd conductive plunger be used for being electrically connected to described weld pad and with the corresponding conducting block of described top layer test structure.
Below in conjunction with Figure 10 ~ 12, the chip detecting method that utilizes said chip test circuit to test that the embodiment of the present invention is provided is described in detail.
In an embodiment of the present invention, under the weld pad of chip under test one side, the first chip test circuit and the second chip test circuit can be set.Described the first chip test circuit can be the chip test circuit that aforementioned the second test layer is positioned at the first test layer top, so, the first test layer of described the first chip test circuit is corresponding with the odd-level metal level of chip under test respectively, and the second test layer of described the first chip test circuit is corresponding with the even level metal level of chip under test respectively.Described the second chip test circuit can be the chip test circuit that aforementioned the second test layer is positioned at the first test layer below, so, the first test layer of described the second chip test circuit is corresponding with the even level metal level of chip under test respectively, the second test layer that is described the first chip test circuit is corresponding with the odd-level metal level of chip under test respectively, finally can, in conjunction with utilizing the test result of two chip test circuits comprehensively to analyze the inner case of chip under test, further draw judgement more accurately.First take any one chip test circuit below describes as example.
First, provide test component, described test component has the first test lead A and the second test lead B.In embodiments of the present invention, described test component can be multimeter, but is not limited to this.
Then, please refer to Figure 10, a plurality of first conducting blocks 211 of the first test layer 210 of one deck test structure in described test circuit 200 are electrically connected to described the first test lead A, a plurality of the 3rd conducting blocks 233 of the second test layer 220 of this layer of test structure are electrically connected to described the second test lead B.
Then whether, monitoring described test component has electric current to pass through, and judges between the first test layer 210 of described test structure and the second test layer 220 whether have leakage current.
Then, according to described leakage current test result, whether the dielectric material of the second test layer that judgement is connected with described the second test lead B there is crack,, between the first test layer of described test structure and the second test layer, having leakage current, there is crack in the dielectric material of the second test layer that described the second test interface connects.
Because the layer of metal layer of described the second test layer and chip under test is corresponding, for simulating corresponding metal level, and be positioned under weld pad and the metal level of described correspondence bears identical pressure, therefore according to described the second test layer medium material, whether occur that crack can infer whether the metal level of described correspondence also occurs crack.
In addition, in embodiments of the present invention, due to the second metal level of described the first chip test circuit and the even level metal level of chip under test correspondence, therefore when above-mentioned test circuit is the first chip test circuit, can infer whether all even level metal levels occur crack according to above-mentioned test result.Due to the second metal level of described the second chip test circuit and the odd-level metal level of chip under test correspondence, therefore when described test circuit is the second chip test circuit, can infer whether all odd-level metal levels occur crack according to above-mentioned test result.
If use the first chip test circuit and the second chip test circuit to test just can to test out all metal levels of chip under test whether to occur crack simultaneously.
When described test circuit comprises multi-layer testing structure, can also between adjacent test structure, test.
First, please refer to Figure 11, a plurality of the 3rd conducting blocks 233 of the second test layer 220 of one deck test structure are electrically connected to described the first test lead A, the first conducting block 211 of the first test layer 210 of the test structure adjacent with this layer of test structure is electrically connected to described the second test lead B.
Then, whether have electric current pass through, thereby judge between described test structure and adjacent test structure whether have leakage current if monitoring described test component.
Then, according to described leakage current test result, judge whether the interlayer dielectric layer between described test structure and adjacent test structure occurs crack,, between described test structure and adjacent test structure, have leakage current, there is crack in the interlayer dielectric layer between described test structure and adjacent test structure.
Layer of metal layer due to described the first test layer and the corresponding chip under test of the second test layer difference, therefore interlayer dielectric layer and the interlevel dielectric material between two metal levels in chip under test between so described adjacent test structure are corresponding, whether occur that crack can infer that crack also appears in the interlevel dielectric material of the chip under test corresponding with described interlayer dielectric layer according to the interlayer dielectric layer between described adjacent test structure.
In addition, please refer to Figure 12, when described chip test circuit comprises the second conductive plunger 250, utilize the method that described chip test circuit is tested to comprise: a plurality of first conducting blocks 211 of the first test layer 210 of one deck test structure in described test circuit 200 to be electrically connected to described the first test lead A, a plurality of first conducting blocks 211 of the first test layer 210 of the test structure adjacent with this layer of test structure are electrically connected to described the second test lead B; Whether then, monitor described test component has leakage current to pass through.
Owing to being communicated with by the second conductive plunger 250 between the second test layer of this layer of test structure and the first test layer of the test structure that is adjacent, in fact so above-mentioned test process can test out between the first test layer of this layer of test structure and the second test layer whether occur leakage current, therefore according to above-mentioned leakage current test result, whether the dielectric material that also can judge the second test layer in this layer of test structure there is crack.
In sum, embodiments of the invention have the following advantages:
In an embodiment of the present invention, by forming the first test layer and the second test layer is simulated the metal level in chip under test, and simulate the conductive plunger in chip under test by forming the first conductive plunger, the structure of the more enough simulation chip under test more true to nature of chip test circuit that therefore embodiment of the present invention provides, thus can react more accurately the actual inside situation of chip under test.
Secondly, the shape of cross section of described the second conducting block is non-square or non-circular, and the identical square or circular Zhou Chang great of the section girth specific area of described the second conducting block.That is to say, described the second conducting block, in the situation that keeping cross-sectional area constant, has larger girth.So, the pressure that the first conducting block bears under uniform pressure is constant, and the contact area of the described dielectric material in the situation that of same thickness and between the second and the 3rd test structure is larger.Therefore,, in the situation of identical pressure, at the surface of contact of described the second conducting block and dielectric material, occur that the probability in crack is larger, thereby further improve the sensitivity of described test circuit.
Again, and the first conductive plunger of being electrically connected to of the second conducting block of each ring texture can be one or more.While comprising a plurality of the first conductive plunger on described the second conducting block, can when the first conductive plunger is one the pressure that bears by a plurality of the first conductive plungers, disperse to be applied to a plurality of regions near described dielectric material inner side, make the dielectric material in test circuit be more prone to occur crack, thereby further improve the sensitivity of chip test circuit.
Finally, the first test layer in described chip test circuit and the second test layer be the layer of metal layer of corresponding chip under test respectively, by between described the first test layer at same test structure and the second test layer and test between adjacent test structure, then according to its test result, can accurately judge that the position of damaging appears in chip under test, thereby improve the precision of chip testing.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (14)
1. a chip test circuit, is characterized in that, comprising: one deck test structure at least, and described at least one deck test structure is stacked arrangement, and is formed with interlayer dielectric layer between adjacent test structure, and every one deck test structure comprises:
The first test layer, described the first test layer comprises the first conducting block of a plurality of mutual electrical connections;
The second test layer, described the second test layer is positioned at below or the top of described the first test layer, and described the second test layer comprises a plurality of ring texturees, described ring texture and described the first conducting block are corresponding one by one, described in each, ring texture comprises at second conducting block at center with at the 3rd conducting block of outer shroud, dielectric material between described the second conducting block and the 3rd conducting block, and is mutually electrically connected between a plurality of described the 3rd conducting block; And
A plurality of the first conductive plungers, described the first conductive plunger between described the first test layer and the second test layer, for being electrically connected to described the first conducting block and second conducting block corresponding with it,
Every one deck the first test layer and every one deck the second test layer are all distinguished the layer of metal layer of corresponding chip under test.
2. chip test circuit as claimed in claim 1, is characterized in that, the identical square or circular Zhou Chang great of section girth specific area of described the second conducting block.
3. chip test circuit as claimed in claim 1, is characterized in that, also comprises: a plurality of the second conductive plungers, and between adjacent two test structures, for being electrically connected to the second conducting block and corresponding first conducting block of adjacent test structure.
4. chip test circuit as claimed in claim 1, it is characterized in that, also comprise: a plurality of the 3rd conductive plungers, described the 3rd conductive plunger weld pad and and the hithermost test layer of described weld pad between, for be electrically connected to weld pad and with the conducting block of the hithermost test layer of described weld pad.
5. chip test circuit as claimed in claim 1, is characterized in that, the first conductive plunger being connected with each second conducting block is one or more.
6. chip test circuit as claimed in claim 1, is characterized in that, the cross-sectional area of described the first conductive plunger is 1/4 ~ 3/4 of described the second conducting block.
7. a formation method for chip test circuit, is characterized in that, comprising: form at least one deck test structure, described at least one deck test structure is stacked arrangement;
The formation method of every one deck test structure comprises:
Form the first conductive layer;
Graphical described the first conductive layer forms the first test layer, and described the first test layer comprises the first conducting block of a plurality of mutual electrical connections;
On described the first test layer, form the first interlayer dielectric layer;
In described the first interlayer dielectric layer, form a plurality of the first conductive plungers, the position of described the first conductive plunger is corresponding one by one with the position of described the first conducting block;
Form the second conductive layer, cover described the first interlayer dielectric layer and described the first conduction plug;
Graphical described the second conductive layer forms the second test layer, described the second test layer comprises a plurality of ring texturees, the position of described ring texture and described the first conducting block is corresponding one by one, described in each, ring texture comprises the second conducting block that is positioned at center and the 3rd conducting block that is positioned at outer shroud, described the second conducting block is positioned on corresponding described the first conduction plug, between described the 3rd conducting block, is mutually electrically connected to; And
Filled media material in described the second conducting block and the 3rd conducting block,
Or the formation method of every one deck test structure comprises:
Form the second conductive layer, graphical described the second conductive layer is to form the second test layer, described the second test layer comprises a plurality of ring texturees, and described in each, ring texture comprises the second conducting block that is positioned at center and the 3rd conducting block that is positioned at outer shroud, between described the 3rd conducting block, is mutually electrically connected to;
Filled media material in described the second conducting block and the 3rd conducting block;
On described second layer test layer, form the first interlayer dielectric layer;
In described the first interlayer dielectric layer, form a plurality of the first conductive plungers, the position of described the first conductive plunger is corresponding one by one with the position of described the second conducting block;
And form the first conductive layer on described the first interlayer dielectric layer;
Graphical described the first conductive layer forms the first test layer, and described the first test layer comprises the first conducting block of a plurality of mutual electrical connections, and corresponding one by one with the position of described the first conductive plunger;
Wherein, every one deck the first test layer and every one deck the second test layer are all distinguished the layer of metal layer of corresponding chip under test.
8. the formation method of chip test circuit as claimed in claim 7, is characterized in that, the identical square or circular Zhou Chang great of section girth specific area of described the second conducting block.
9. the formation method of chip test circuit as claimed in claim 7, it is characterized in that, after forming one deck test structure, formation be positioned on this layer of test structure and another layer test structure adjacent with this layer of test structure before, also comprise: form the second interlayer dielectric layer, described the second interlayer dielectric layer covers this layer of test structure, in described the second interlayer dielectric layer, form the second conductive plunger, described the second conductive plunger is between adjacent two layers test structure, for being electrically connected to the second conducting block and corresponding first conducting block of adjacent test structure.
10. the formation method of chip test circuit as claimed in claim 7, it is characterized in that, also comprise: form after the test structure be positioned at top layer, before forming weld pad, also comprise: form the 3rd interlayer dielectric layer, top layer test structure described in described the 3rd interlayer dielectric layer covers; In described the 3rd interlayer dielectric layer, form a plurality of the 3rd conductive plungers, described the 3rd conductive plunger be used for being electrically connected to described weld pad and with the corresponding conducting block of described top layer test structure.
The formation method of 11. chip test circuits as claimed in claim 7, is characterized in that, the first conductive plunger being connected with each second conducting block is one or more.
The formation method of 12. chip test circuits as claimed in claim 7, is characterized in that, the cross-sectional area of described the first conductive plunger is 1/4 ~ 3/4 of described the second conducting block.
The method of testing of the chip test circuit of 13. 1 kinds of right to use requirements 1, is characterized in that, comprising:
Test component is provided, and described test component has the first test lead and the second test lead;
A plurality of first conducting blocks of the first test layer of one deck test structure are electrically connected to described the first test lead;
A plurality of the 3rd conducting blocks of the second test layer of this layer of test structure are electrically connected to described the second test lead;
Whether have electric current pass through, judge between the first test layer of described test structure and the second test layer whether have leakage current if monitoring described test component;
According to described leakage current test result, whether the dielectric material of the second test layer that judgement is connected with described the second test lead there is crack, thereby infers whether the metal level of the chip under test corresponding with described the second test layer occurs crack.
14. method of testings as claimed in claim 13, is characterized in that, also comprise:
A plurality of the 3rd conducting blocks of the second test layer of one deck test structure are electrically connected to described the first test lead;
A plurality of first conducting blocks of the first test layer of the test structure adjacent with this layer of test structure are electrically connected to described the second test lead;
Whether have electric current pass through, judge between described test structure and adjacent test structure whether have leakage current if monitoring described test component;
According to described leakage current test result, judge whether the interlayer dielectric layer between described test structure and adjacent test structure occurs crack, thereby infer whether the interlevel dielectric material of the chip under test corresponding with described interlayer dielectric layer occurs crack.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107037699A (en) * | 2016-02-03 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | The forming method of mark structure |
| CN112904180A (en) * | 2021-01-22 | 2021-06-04 | 长鑫存储技术有限公司 | Chip test board and chip test method |
| CN113823576A (en) * | 2020-06-18 | 2021-12-21 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor test structure and forming method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404122A (en) * | 2001-07-26 | 2003-03-19 | 联华电子股份有限公司 | Detection method of electric defect in inner conducting layer of tested area |
| KR100638042B1 (en) * | 2004-12-28 | 2006-10-23 | 동부일렉트로닉스 주식회사 | Test Pattern for Measuring Kelvin Resistance and Semiconductor device Including Such a Pattern |
| US20080135840A1 (en) * | 2006-12-06 | 2008-06-12 | Ta-Chih Peng | Test structure |
| CN101312181A (en) * | 2007-05-24 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semiconductor chip, integrated circuit structure and semi-conductor wafer |
| US20090057664A1 (en) * | 2007-08-28 | 2009-03-05 | Chartered Semiconductor Manufacturing, Ltd. | E-beam inspection structure for leakage analysis |
| CN101615606A (en) * | 2008-06-26 | 2009-12-30 | 台湾积体电路制造股份有限公司 | Integrated circuit (IC) chip weld pad and manufacture method thereof and comprise the integrated circuit of this weld pad |
| CN101622545A (en) * | 2007-02-22 | 2010-01-06 | 泰拉丁公司 | Design-for-test micro probe |
| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
-
2012
- 2012-08-29 CN CN201210313499.2A patent/CN103630825B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404122A (en) * | 2001-07-26 | 2003-03-19 | 联华电子股份有限公司 | Detection method of electric defect in inner conducting layer of tested area |
| KR100638042B1 (en) * | 2004-12-28 | 2006-10-23 | 동부일렉트로닉스 주식회사 | Test Pattern for Measuring Kelvin Resistance and Semiconductor device Including Such a Pattern |
| US20080135840A1 (en) * | 2006-12-06 | 2008-06-12 | Ta-Chih Peng | Test structure |
| CN101622545A (en) * | 2007-02-22 | 2010-01-06 | 泰拉丁公司 | Design-for-test micro probe |
| CN101312181A (en) * | 2007-05-24 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semiconductor chip, integrated circuit structure and semi-conductor wafer |
| US20090057664A1 (en) * | 2007-08-28 | 2009-03-05 | Chartered Semiconductor Manufacturing, Ltd. | E-beam inspection structure for leakage analysis |
| CN101615606A (en) * | 2008-06-26 | 2009-12-30 | 台湾积体电路制造股份有限公司 | Integrated circuit (IC) chip weld pad and manufacture method thereof and comprise the integrated circuit of this weld pad |
| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107037699A (en) * | 2016-02-03 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | The forming method of mark structure |
| CN107037699B (en) * | 2016-02-03 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of mark structure |
| CN113823576A (en) * | 2020-06-18 | 2021-12-21 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor test structure and forming method thereof |
| CN113823576B (en) * | 2020-06-18 | 2023-07-04 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor test structure and forming method thereof |
| CN112904180A (en) * | 2021-01-22 | 2021-06-04 | 长鑫存储技术有限公司 | Chip test board and chip test method |
| CN112904180B (en) * | 2021-01-22 | 2022-04-19 | 长鑫存储技术有限公司 | Chip test board and chip test method |
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|---|---|
| CN103630825B (en) | 2016-01-06 |
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