CN103187400B - Silicon through hole detection architecture and detection method - Google Patents
Silicon through hole detection architecture and detection method Download PDFInfo
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- CN103187400B CN103187400B CN201110459415.1A CN201110459415A CN103187400B CN 103187400 B CN103187400 B CN 103187400B CN 201110459415 A CN201110459415 A CN 201110459415A CN 103187400 B CN103187400 B CN 103187400B
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Abstract
A kind of silicon through hole detection architecture and detection method, described silicon through hole detection architecture comprises: semiconductor base, the first silicon through hole being positioned at described semiconductor base and the second silicon through hole be oppositely arranged with described first silicon through hole; At least one deck first be positioned at above described first silicon through hole and part semiconductor substrate tests metal level, the at least one deck second be positioned at above described second silicon through hole and part semiconductor substrate tests metal level, described first test metal level and the second test metal level are positioned at different layers and interval setting, between the first test metal level and the second test metal level of adjacent layer, have the region that partly overlaps.By testing puncture voltage, the electric capacity between described first test metal level and the second test metal level, can detect whether silicon through-hole surfaces exists copper projection.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of silicon through hole detection architecture and detection method.
Background technology
Along with semiconductor technology development, the characteristic size of current semiconductor device has become very little, wish that the quantity increasing semiconductor device in the encapsulating structure of two dimension becomes more and more difficult, therefore three-dimension packaging becomes a kind of method that effectively can improve chip integration.Current three-dimension packaging comprises based on chip-stacked (DieStacking) of gold thread bonding, encapsulation stacking (PackageStacking) and three-dimensional stacked based on silicon through hole (ThroughSiliconVia, TSV).Wherein, the three-dimensional stacked technology of silicon through hole is utilized to have following three advantages: (1) High Density Integration; (2) shorten the length of electrical interconnection significantly, thus the problems such as the signal delay appeared in two-dimentional system level chip (SOC) technology can be solved well; (3) utilize silicon through hole technology, the chip (as radio frequency, internal memory, logic, MEMS etc.) with difference in functionality can be integrated and realize the multi-functional of packaged chip.Therefore, the described three-dimensional stacked technology of silicon through hole interconnect structure that utilizes becomes a kind of comparatively popular chip encapsulation technology day by day.
The main method of current formation silicon through hole comprises: utilize the first surface being dry-etched in silicon substrate to form through hole; Insulating barrier is formed at described through-hole side wall and lower surface; Adopt electric plating method that copper is filled full described through hole, and remove unnecessary copper electrodeposited coating with chemico-mechanical polishing; Chemico-mechanical polishing is carried out to the second surface relative with first surface of described silicon substrate, until expose the through hole of filling full copper, forms silicon through hole.More formation process about silicon through hole please refer to the american documentation literature that publication number is US2011/0034027A1.
In the prior art, the material of described insulating barrier is generally silica, and the material of silicon substrate is silicon.Because the temperature of follow-up formation interconnection layer is usually all higher, copper, silicon, all can there is thermal expansion in silica, but because the thermal coefficient of expansion of described three kinds of materials is different, the thermal coefficient of expansion of copper is maximum, the volume amplification of copper is maximum, and be positioned at described semiconductor base, the amplification of the volume of the silicon through hole in insulating barrier is not enough to the volume amplification meeting copper, please refer to Fig. 1, copper in silicon through hole 01 is extruded from the opening part of silicon through hole, form copper projection 02, described copper projection 02 can make metal level 03 and interlayer dielectric layer 04 surface irregularity of follow-up formation, defect may be produced, affect the electric property of interconnection structure.When described silicon through-hole surfaces has been formed with interconnection structure, described copper projection more can affect the electric property of described interconnection structure, even may cause metal level short circuit or open circuit.Even if the temperature of described silicon through hole drops to room temperature from high temperature when forming interconnection layer, copper shrinks, but there occurs change due to copper arrangement of lattice when thermal expansion, and in described silicon through hole, the shape of copper is difficult to restore completely, still can form less copper projection, affect the electric property of interconnection structure.
Summary of the invention
The problem that the present invention solves is to provide a kind of silicon through hole detection architecture and detection method, can detect silicon through-hole surfaces easily and whether form copper projection.
For solving the problem, embodiments providing a kind of silicon through hole detection architecture, comprising:
Semiconductor base, the first silicon through hole being positioned at described semiconductor base and the second silicon through hole be oppositely arranged with described first silicon through hole;
At least one deck first be positioned at above described first silicon through hole and part semiconductor substrate tests metal level, the at least one deck second be positioned at above described second silicon through hole and part semiconductor substrate tests metal level, described first test metal level and the second test metal level are positioned at different layers and interval setting, between the first test metal level and the second test metal level of adjacent layer, have the region that partly overlaps.
Optionally, when the quantity of described first test metal level is greater than one deck, be connected with the first connection metal layer by the first conductive plunger between the first test metal level of different layers, the testing metal level be positioned at same layer with second of described first connection metal layer correspondence, described first conductive plunger is positioned at the top of described first silicon through hole.
Optionally, when the quantity of described second test metal level is greater than one deck, be connected with the second connection metal layer by the second conductive plunger between the second test metal level of different layers, the testing metal level be positioned at same layer with first of described second connection metal layer correspondence, described second conductive plunger is positioned at the top of described second silicon through hole.
Optionally, the first conductive plunger being positioned at same layer, the second conductive plunger being positioned at same layer at least comprise four conductive plungers.
Optionally, the minimum spacing between the first test metal level, the second connection metal layer of same layer is minimum design dimension; Minimum spacing between the second test metal level, the first connection metal layer of same layer is minimum design dimension.
Optionally, the first test metal level of described adjacent layer and the shape of the second test metal level are with the perpendicular bisector specular between the first silicon through hole and the second silicon through hole.
Optionally, when the quantity of described first silicon through hole and the second silicon through hole is all one, described first test metal level, the second test metal level are rectangular metal line, equal and be greater than the half of spacing between described first silicon through hole and the second silicon through hole in the length of the first test metal level of adjacent layer, the second test metal level.
Optionally, when the quantity of described first silicon through hole, the second silicon through hole is all at least two, the shape of described first test metal level, the second test metal level is comb metal line, the position of described first silicon through hole or the second silicon through hole corresponds to the position that each root comb of described comb metal line and comb handle are intersected, and the length of the comb of the comb metal line of described first test metal level, the second test metal level is identical and be greater than the half of spacing between described first silicon through hole and the second silicon through hole.
Optionally, the first test metal level near the first silicon through hole is formed at described first silicon through-hole surfaces, and the second test metal level near the second silicon through hole is connected with described second silicon through hole by the second conductive plunger.
Optionally, the first test metal level near the first silicon through hole is connected with described first silicon through hole by the first conductive plunger, and the second test metal level near the second silicon through hole is formed at described second silicon through-hole surfaces.
Optionally, the spacing between described the first different silicon through hole, the second silicon through hole is minimal design spacing.
The embodiment of the present invention additionally provides a kind of detection method utilizing described silicon through hole detection architecture, comprising:
Detection voltage is applied to described first test metal level and the second test metal level two ends;
Utilize described detection voltage detecting first to test puncture voltage between metal level and the second test metal level, thus judge whether described silicon through-hole surfaces exists copper projection.
Optionally, described puncture voltage is compared with reference to puncture voltage, when described puncture voltage is different from reference to puncture voltage, judge that described silicon through-hole surfaces exists copper projection.
The embodiment of the present invention additionally provides a kind of detection method utilizing described silicon through hole detection architecture, comprising:
Detection voltage is applied to described first test metal level and the second test metal level two ends;
Utilize described detection voltage detecting first to test electric capacity between metal level and the second test metal level, thus judge whether described silicon through-hole surfaces exists copper projection.
Optionally, described electric capacity and reference capacitance are compared, when described electric capacity and reference capacitance inconsistent time, judge that described silicon through-hole surfaces exists copper projection.
Compared with prior art, the present invention has the following advantages:
The second silicon through hole that described silicon through hole detection architecture comprises the first silicon through hole and is oppositely arranged with described first silicon through hole; At least one deck first is tested metal level and is positioned at above described first silicon through hole and part semiconductor substrate, at least one deck second is tested metal level and is positioned at above described second silicon through hole and part semiconductor substrate, and described first test metal level and the second test metal level are positioned at different layers and interval setting, between the first test metal level and the second test metal level of adjacent layer, there is the region that partly overlaps.Deform due to the first test metal level and the second test metal level can be made when silicon through-hole surfaces exists copper projection, spacing between first test metal level, the second test metal level can change, first test metal level, the puncture voltage of the second test metal level, electric capacity are changed, by testing corresponding puncture voltage, electric capacity, thus can detect whether silicon through-hole surfaces exists copper projection.
Accompanying drawing explanation
Fig. 1 is the existing structural representation forming copper projection in silicon through-hole surfaces;
Fig. 2 is the cross-sectional view of the silicon through hole detection architecture of first embodiment of the invention;
Fig. 3, Fig. 4 are the transversal profile structural representations of the silicon through hole detection architecture of first embodiment of the invention;
Fig. 5, Fig. 6 are the transversal profile structural representations of the silicon through hole detection architecture of second embodiment of the invention;
Fig. 7 is the cross-sectional view of the silicon through hole detection architecture of third embodiment of the invention;
Fig. 8, Fig. 9 are the structural representations that the silicon through hole detection architecture of copper projection appears in silicon through-hole surfaces in described silicon through hole detection architecture.
Embodiment
Mention in the introduction, when high temperature, the copper in silicon through hole is easily extruded from the opening part of silicon through hole, forms copper projection.Described copper projection can make the interconnect layer surfaces out-of-flatness of follow-up formation, affects the electric property of interconnection layer.When described silicon through-hole surfaces has been formed with interconnection layer, described copper projection more can affect the electric property of described interconnection layer, even may cause interconnection layer short circuit.Therefore, need to detect described silicon through hole, eliminate the semiconductor structure of existing defects as early as possible, the semiconductor structure avoiding silicon through-hole surfaces to be formed with copper projection enters back end fabrication, affects the yield of final products.
For this reason, inventor, through research, proposes a kind of silicon through hole detection architecture, comprising: semiconductor base, the first silicon through hole being positioned at described semiconductor base and the second silicon through hole be oppositely arranged with described first silicon through hole; At least one deck first be positioned at above described first silicon through hole and part semiconductor substrate tests metal level, the at least one deck second be positioned at above described second silicon through hole and part semiconductor substrate tests metal level, described first test metal level and the second test metal level are positioned at different layers and interval setting, between the first test metal level and the second test metal level of adjacent layer, have the region that partly overlaps.When detecting voltage and being applied to the first metal layer and the second metal level two ends, utilize puncture voltage, electric capacity between the first metal layer and the second metal level described in described detection voltage detecting, described puncture voltage, electric capacity and reference puncture voltage, reference capacitance are compared, thus judge whether described silicon through-hole surfaces exists copper projection, it is sensitive, convenient to detect.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
The embodiment of the present invention provide firstly a kind of silicon through hole detection architecture, please refer to Fig. 2, for the cross-sectional view of the silicon through hole detection architecture of the present embodiment, comprise: semiconductor base 100, the first silicon through hole 110 being positioned at described semiconductor base 100 and the second silicon through hole 120 be oppositely arranged with described first silicon through hole 110, be positioned at described first silicon through hole 110, second silicon through hole 120, the first metal layer on part semiconductor substrate 100 surface, described the first metal layer comprises the first test metal level 210 being positioned at described first silicon through hole 110 and part semiconductor substrate 100 surface and the second connection metal layer 320 being positioned at described second silicon through hole 120 surface, cover first interlayer dielectric layer 410 on described the first metal layer surface, run through described first interlayer dielectric layer 410 and be positioned at the first conductive plunger 510 above described first silicon through hole 110, run through described first interlayer dielectric layer 410 and be positioned at the second conductive plunger 520 above described second silicon through hole 120, be positioned at second metal level on described first interlayer dielectric layer 410 surface, described second metal level comprises the first connection metal layer 310 being positioned at described first conductive plunger 510 surface and the second test metal level 220 being positioned at dielectric layer 410 surface between described second conductive plunger 520 and segments first layer, cover the second interlayer dielectric layer 420 of described second layer on surface of metal, wherein, between described first test metal level 210 and the second test metal level 220, there is the region that partly overlaps.
Concrete, described semiconductor base 100 is single layer structure or multilayer lamination structure.When described semiconductor base 100 is single layer structure, described semiconductor base 100 is Semiconductor substrate, such as silicon substrate, germanium substrate, germanium silicon substrate etc.When described semiconductor base 100 is multilayer lamination structure, described semiconductor base 100 comprises Semiconductor substrate and is positioned at the interconnection layer of described semiconductor substrate surface.Described interconnection layer can only include one deck interlayer dielectric layer, also can comprise multiple layer metal interconnection layer and multilayer interlayer dielectric layer.
Described first silicon through hole 110, second silicon through hole 120 is positioned at described semiconductor base 100 and the surface of described silicon through hole 110 is exposed to the surface of described semiconductor base 100.Described first silicon through hole 110, second silicon through hole 120 comprises the through hole being positioned at described semiconductor base 100, be positioned at the insulating barrier (not shown) of described through-hole side wall and lower surface, be positioned at described surface of insulating layer and the electric conducting material (not shown) of the full described through hole of filling.Described electric conducting material is copper, and the material of described insulating barrier is silica or silicon nitride.In other embodiments, between described insulating barrier and electric conducting material, be also formed with diffusion impervious layer, to prevent copper metal to be diffused in insulating barrier, semiconductor base, affect the electric property of silicon through hole.Because the thermal coefficient of expansion of copper, semiconductor base, insulating barrier, diffusion impervious layer is different, the thermal coefficient of expansion of copper is maximum, in the environment of high temperature, easily makes copper extrude from the opening part of silicon through hole, forms copper projection.Described copper projection can make the interconnect layer surfaces out-of-flatness of follow-up formation, affects the electric property of interconnection layer.When described silicon through-hole surfaces has been formed with interconnection layer, described copper projection more can affect the electric property of described interconnection layer, may make to produce defect in interlayer dielectric layer, or make metal interconnected thread breakage, causes being short-circuited between interconnection layer or open circuit.In the prior art, the material of described interlayer dielectric layer is silica or low-K dielectric material.Owing to becoming more and more higher along with semiconductor device integrated level, in order to reduce the Resistance-Capacitance delay of interconnection structure, need the K value reducing interlayer dielectric layer, increasing semiconductor structure adopts low-K dielectric material as the material of interlayer dielectric layer.But because existing low-K dielectric material is mostly the material that quality comparatively loosens, the interlayer dielectric layer that copper projection more easily makes low-K dielectric material be formed produces defect.Therefore, be necessary very much to detect the surface of described silicon through hole, eliminate bad semiconductor structure as early as possible, the semiconductor structure avoiding silicon through-hole surfaces to be formed with copper projection enters back end fabrication, affects the yield of final products.
Described first silicon through hole 110 and the second silicon through hole 120 are oppositely arranged.When the quantity of described first silicon through hole 110 and the quantity of the second silicon through hole 120 are all at least two, the straight line that several the first silicon through holes 110 described are linked to be and the straight line parallel that several the second silicon through holes 120 are linked to be.Spacing between Different Silicon through hole needs little as much as possible, the quantity of silicon through hole in unit are is increased, multiple copper projection more can make interconnection layer produce defect, described defect is more easily detected by the test metal level of the silicon through hole detection architecture of the embodiment of the present invention, thus judges whether silicon through-hole surfaces has copper projection.In the present embodiment, spacing between described the first silicon through hole 110 of being oppositely arranged and the second silicon through hole 120, the spacing of the first adjacent silicon through hole, the spacing of the second adjacent silicon through hole are minimal design spacing, described minimal design spacing is the minimum spacing of two silicon through hole requirements in the design process, interacts to avoid adjacent silicon through hole.
In embodiments of the present invention, described first test metal level 210, second is tested metal level 220 and is used for testing described silicon through-hole surfaces and whether there is copper projection, and described first connection metal layer 310, second connection metal layer 320 is used for the conductive plunger into connecting different layers.In other embodiments, also can not form described first connection metal layer, the second connection metal layer, be directly connected by conductive plunger between different test metal levels, silicon through hole.
In the present embodiment, the first test metal level 210 near the first silicon through hole 110 is formed at described first silicon through hole 110 surface, and the second test metal level 210 near the second silicon through hole 120 is connected with described second silicon through hole 120 by the second conductive plunger 520.In other embodiments, the first test metal level near the first silicon through hole is connected with described first silicon through hole by the first conductive plunger, and the second test metal level near the second silicon through hole is formed at described second silicon through-hole surfaces.
In a first embodiment, please refer to Fig. 3, for the first metal layer of silicon through hole detection architecture in Fig. 2 is along the cross-sectional view of line of cut AA '.Please refer to Fig. 4, for the second metal level of silicon through hole detection architecture in Fig. 2 is along the cross-sectional view of line of cut BB '.In the present embodiment, the quantity of described first silicon through hole 110 and the second silicon through hole 120 is all one.The second test metal level 220 that in described the first metal layer first is tested in metal level 210 and the second metal level is all rectangular metal line, and the length that described first test metal level 210, second tests metal level 220 is all greater than the half of spacing between described first silicon through hole 110 and the second silicon through hole 120, make, between described first test metal level 210 and the second test metal level 220, there is the region that partly overlaps.First test metal level 210 of described adjacent layer and the shape of the second test metal level 220 can also with the perpendicular bisector specular between the first silicon through hole 110 and the second silicon through hole 120.In the present embodiment, described first test metal level 210 is equal with the second test metal level 220 length, and is all greater than the half of spacing between described first silicon through hole 110 and the second silicon through hole 120.And in order to improve measurement sensitivity, between described first test metal level 210 and the second test metal level 220, overlapping area needs large as much as possible, namely described first test metal level 210 and the second test metal level 220 length need long as much as possible.Because described the first metal layer comprises the first test metal level and the second connection metal layer, interval between described first test metal level and the second connection metal layer is set to minimum design dimension, both the length of described first test metal level can have been made long as much as possible, also helped and improve measurement sensitivity when the puncture voltage between metal level and the second test metal level is tested in test first.Because described second metal level comprises the second test metal level and the first connection metal layer, interval between described second test metal level and the first connection metal layer is set to minimum design dimension, both the length of described second test metal level can have been made long as much as possible, also helped and improve measurement sensitivity when the puncture voltage between metal level and the second test metal level is tested in test first.
In a second embodiment, please refer to Fig. 5, for the first layer metal layer of silicon through hole detection architecture in Fig. 2 is along the cross-sectional view of line of cut AA '.Please refer to Fig. 6, for the second layer metal layer of silicon through hole detection architecture in Fig. 2 is along the cross-sectional view of line of cut BB '.In the present embodiment, the shape that described first test metal level 210, second tests metal level 220 is comb metal line, because the quantity of described first silicon through hole 110, second silicon through hole 120 is respectively 3, described comb metal line comprises three comb and a comb handle, and the position in the corresponding semiconductor base 100 in position that each root comb and comb handle are intersected has a first silicon through hole 110 or a second silicon through hole 120.When the position of described first silicon through hole 110 or the second silicon through hole 120 corresponds to the position that each root comb of described comb metal line and comb handle intersect, if the surface of the first silicon through hole 110 or the second silicon through hole 120 is formed with copper projection, more easily make the comb generation deformation of described comb metal line, thus make test result sensitiveer, whether the surface more easily recording described first silicon through hole or the second silicon through hole is formed with copper projection.The length of the comb of the comb metal line of described first test metal level 210 and the second test metal level 220 is greater than the half of spacing between the first silicon through hole 110 and the second silicon through hole 120, makes to have the region that partly overlaps between described first test metal level 210 and the second test metal level 220.And in order to improve measurement sensitivity, the length of the comb of the comb metal line of described first test metal level 210 and the second test metal level 220 needs long as much as possible, is conducive to the area that improve overlapping region between the first test metal level 210 and the second test metal level 220.
In the third embodiment, please refer to Fig. 7, be the cross-sectional view of the silicon through hole detection architecture of the 3rd embodiment, comprise: semiconductor base 100, the first silicon through hole 110 being positioned at described semiconductor base 100 and the second silicon through hole 120 be oppositely arranged with described first silicon through hole 110; Be positioned at the two-layer first test metal level 210 above described first silicon through hole 110 and part semiconductor substrate 100, be connected with the first connection metal layer 310 by the first conductive plunger 510 between described two-layer first test metal level 210, described first conductive plunger 510 is positioned at the top of described first silicon through hole 110; Be positioned at the two-layer second test metal level 220 above described second silicon through hole 120 and part semiconductor substrate 100, be connected with the second connection metal layer 320 by the second conductive plunger 520 between described two-layer second test metal level 220, between described second silicon through hole 120 and the second test metal level 220, described second conductive plunger 520 is positioned at the top of described second silicon through hole 120; Described first test metal level 210 and the second test metal level 220 are positioned at different layers and interval setting, between the first test metal level 210 and the second test metal level 220 of adjacent layer, have the region that partly overlaps.
In other embodiments, described silicon through hole detection architecture can also comprise the first test metal level and at least three layer of second test metal level of at least three layers, described first test metal level and the second test metal level are positioned at different layers and interval setting, between the first test metal level and the second test metal level of adjacent layer, have the region that partly overlaps.
When being formed with the first conductive plunger 510 or the second conductive plunger 520 between described different metal level, the conductive plunger quantity of described first conductive plunger 510 or the second conductive plunger 520 is at least 4.Due to compared with the diameter of the first silicon through hole 110, second silicon through hole 120, the diameter of described first conductive plunger 510, second conductive plunger 520 is smaller, when described first silicon through hole 110, second silicon through hole 120 surface is formed with copper projection, single electrical connector mechanical strength is less, the stress that described copper projection causes easily makes conductive plunger deform, thus the first test metal level 210, second test metal level 220 can not be made to deform, effectively can not test whether there is copper projection.Therefore, the conductive plunger quantity of the first conductive plunger 510 or the second conductive plunger 520 that are positioned at same layer is at least 4, the mechanical strength of the first conductive plunger 510 or the second conductive plunger 520 can be strengthened, the stress that described copper projection is caused can be delivered to interlayer dielectric layer, in test metal level, the first test metal level 210 can be caused, the position of the second test metal level 220 changes, defect in interlayer dielectric layer increases, puncture voltage between first of described adjacent layer test metal level 210 and the second test metal level 220 and electric capacity are changed, by recording puncture voltage between the first test metal level 210 of described adjacent layer and the second test metal level 220 and electric capacity, just can detect described silicon through-hole surfaces whether existing defects.
The embodiment of the present invention additionally provides a kind of detection method utilizing the silicon through hole detection architecture of above-described embodiment, comprising: detection voltage is applied to described first test metal level and the second test metal level two ends; Utilize described detection voltage detecting first to test puncture voltage between metal level and the second test metal level, thus judge whether described silicon through-hole surfaces exists copper projection.
Concrete, please refer to Fig. 8, is the structural representation that the first silicon through hole 110 surface has the silicon through hole detection architecture of copper projection 111.Please refer to Fig. 9, is the structural representation that the first silicon through hole 110 surface has that copper projection 111, second silicon through hole 120 surface has the silicon through hole detection architecture of copper projection 121.As shown in Figure 8, Figure 9, after silicon through-hole surfaces has copper projection, described interlayer dielectric layer can deform, make to produce defect in interlayer dielectric layer, and described copper projection can make the position of metallic test layer offset, spacing between the described first test metal level of adjacent layer and the second test metal level can change, spacing between the test metal level and connection metal layer of same layer also can change, and therefore first of adjacent layer the puncture voltage of testing between metal level and the second test metal level can change.Detection voltage is applied to the first test metal level 210 and the second test metal level 220 two ends, utilize the puncture voltage between the first test metal level 210 and the second test metal level 220 described in described detection voltage detecting, and the described puncture voltage recorded is compared with reference to puncture voltage, if when described puncture voltage is different from reference to puncture voltage, show that the interlayer dielectric layer above the first silicon through hole 110 and the second silicon through hole 120 sustains damage, described first silicon through hole 110 and second at least one surface of silicon through hole 120 are formed with copper projection.Wherein, described with reference to puncture voltage be the silicon through-hole surfaces of described silicon through hole detection architecture be not formed with copper projection time, the puncture voltage between described first test metal level and the second test metal level.
The embodiment of the present invention additionally provides a kind of detection method utilizing the silicon through hole detection architecture of above-described embodiment, comprising: detection voltage is applied to described first test metal level and the second test metal level two ends; Utilize described detection voltage detecting first to test electric capacity between metal level and the second test metal level, thus judge whether described silicon through-hole surfaces exists copper projection.
Due to after silicon through-hole surfaces has copper projection, described copper projection can make the position of metallic test layer offset, spacing between the described first test metal level of adjacent layer and the second test metal level can change, described interlayer dielectric layer can deform, make to produce defect in interlayer dielectric layer, therefore first of adjacent layer the electric capacity tested between metal level and the second test metal level can change.Detection voltage is applied to the first test metal level 210 and the second test metal level 220 two ends, utilize the electric capacity between the first test metal level 210 and the second test metal level 220 described in described detection voltage detecting, and the described electric capacity that records and reference capacitance are compared, if when described electric capacity is different from reference capacitance, show that the interlayer dielectric layer between the first silicon through hole 110 and the second silicon through hole 120 sustains damage, described silicon through-hole surfaces is formed with copper projection.Wherein, described reference capacitance is the silicon through-hole surfaces of described silicon through hole detection architecture when not being formed with copper projection, the capacitance between described first test metal level and the second test metal level.
To sum up, described silicon through hole detection architecture the second silicon through hole of comprising the first silicon through hole and being oppositely arranged with described first silicon through hole; At least one deck first is tested metal level and is positioned at above described first silicon through hole and part semiconductor substrate, at least one deck second is tested metal level and is positioned at above described second silicon through hole and part semiconductor substrate, and described first test metal level and the second test metal level are positioned at different layers and interval setting, between the first test metal level and the second test metal level of adjacent layer, there is the region that partly overlaps.Deform due to the first test metal level and test two metal levels can be made when silicon through-hole surfaces exists copper projection, spacing between first test metal level, the second test metal level can change, first test metal level, the puncture voltage of the second test metal level, electric capacity are changed, by testing corresponding puncture voltage, electric capacity, thus can detect whether silicon through-hole surfaces exists copper projection.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (12)
1. a silicon through hole detection architecture, is characterized in that, comprising:
Semiconductor base, the first silicon through hole being positioned at described semiconductor base and the second silicon through hole be oppositely arranged with described first silicon through hole;
At least one deck first be positioned at above described first silicon through hole and part semiconductor substrate tests metal level, the at least one deck second be positioned at above described second silicon through hole and part semiconductor substrate tests metal level, described first test metal level and the second test metal level are positioned at different layers and interval setting, between the first test metal level and the second test metal level of adjacent layer, have the region that partly overlaps;
First test metal level of described adjacent layer and the shape of the second test metal level are with the perpendicular bisector specular between the first silicon through hole and the second silicon through hole;
When the quantity of described first silicon through hole and the second silicon through hole is all one, described first test metal level, the second test metal level are rectangular metal line, equal and be greater than the half of spacing between described first silicon through hole and the second silicon through hole in the length of the first test metal level of adjacent layer, the second test metal level;
When the quantity of described first silicon through hole, the second silicon through hole is all at least two, the shape of described first test metal level, the second test metal level is comb metal line, the position of described first silicon through hole or the second silicon through hole corresponds to the position that each root comb of described comb metal line and comb handle are intersected, and the length of the comb of the comb metal line of described first test metal level, the second test metal level is identical and be greater than the half of spacing between described first silicon through hole and the second silicon through hole.
2. silicon through hole detection architecture as claimed in claim 1, it is characterized in that, when the quantity of described first test metal level is greater than one deck, be connected with the first connection metal layer by the first conductive plunger between the first test metal level of different layers, the testing metal level be positioned at same layer with second of described first connection metal layer correspondence, described first conductive plunger is positioned at the top of described first silicon through hole.
3. silicon through hole detection architecture as claimed in claim 1, it is characterized in that, when the quantity of described second test metal level is greater than one deck, be connected with the second connection metal layer by the second conductive plunger between the second test metal level of different layers, the testing metal level be positioned at same layer with first of described second connection metal layer correspondence, described second conductive plunger is positioned at the top of described second silicon through hole.
4. silicon through hole detection architecture as claimed in claim 2 or claim 3, it is characterized in that, the first conductive plunger being positioned at same layer or the second conductive plunger being positioned at same layer at least comprise four conductive plungers.
5. silicon through hole detection architecture as claimed in claim 2 or claim 3, is characterized in that, the minimum spacing between the first test metal level and the second connection metal layer of same layer is minimum design dimension; Minimum spacing between the second test metal level and the first connection metal layer of same layer is minimum design dimension.
6. silicon through hole detection architecture as claimed in claim 1, it is characterized in that, the first test metal level near the first silicon through hole is formed at described first silicon through-hole surfaces, and the second test metal level near the second silicon through hole is connected with described second silicon through hole by the second conductive plunger.
7. silicon through hole detection architecture as claimed in claim 1, it is characterized in that, the first test metal level near the first silicon through hole is connected with described first silicon through hole by the first conductive plunger, and the second test metal level near the second silicon through hole is formed at described second silicon through-hole surfaces.
8. silicon through hole detection architecture as claimed in claim 1, it is characterized in that, the spacing of the spacing between described first silicon through hole and the second silicon through hole, the first adjacent silicon through hole and the spacing of the second adjacent silicon through hole are minimal design spacing.
9. utilize a detection method for silicon through hole detection architecture as claimed in claim 1, it is characterized in that, comprising:
Detection voltage is applied to described first test metal level and the second test metal level two ends;
Utilize described detection voltage detecting first to test puncture voltage between metal level and the second test metal level, thus judge whether described silicon through-hole surfaces exists copper projection.
10. detection method as claimed in claim 9, is characterized in that, described puncture voltage is compared with reference to puncture voltage, when described puncture voltage is different from reference to puncture voltage, judges that described silicon through-hole surfaces exists copper projection.
11. 1 kinds of detection methods utilizing silicon through hole detection architecture as claimed in claim 1, is characterized in that, comprising:
Detection voltage is applied to described first test metal level and the second test metal level two ends;
Utilize described detection voltage detecting first to test electric capacity between metal level and the second test metal level, thus judge whether described silicon through-hole surfaces exists copper projection.
12. detection methods as claimed in claim 11, is characterized in that, described electric capacity and reference capacitance are compared, when described electric capacity and reference capacitance inconsistent time, judge that described silicon through-hole surfaces exists copper projection.
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| CN109801855B (en) * | 2019-01-22 | 2021-01-29 | 上海华虹宏力半导体制造有限公司 | WAT testing device for detecting uplift of metal connecting wire, preparation method and testing method |
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