CN104392919A - Silicon base surface treatment method for NMOS element and manufacturing method of NMOS element - Google Patents
Silicon base surface treatment method for NMOS element and manufacturing method of NMOS element Download PDFInfo
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- CN104392919A CN104392919A CN201410664725.0A CN201410664725A CN104392919A CN 104392919 A CN104392919 A CN 104392919A CN 201410664725 A CN201410664725 A CN 201410664725A CN 104392919 A CN104392919 A CN 104392919A
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- silicon
- acid tank
- nmos device
- processing method
- groove
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 57
- 239000010703 silicon Substances 0.000 title claims abstract description 57
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 56
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000004381 surface treatment Methods 0.000 title abstract 2
- 239000002253 acid Substances 0.000 claims description 50
- 239000007789 gas Substances 0.000 claims description 24
- 238000003672 processing method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 13
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 12
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 8
- RWSOTUBLDIXVET-UHFFFAOYSA-N Dihydrogen sulfide Chemical compound S RWSOTUBLDIXVET-UHFFFAOYSA-N 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000002904 solvent Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 238000010926 purge Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 229910021645 metal ion Inorganic materials 0.000 claims description 4
- KFUSEUYYWQURPO-UHFFFAOYSA-N 1,2-dichloroethene Chemical compound ClC=CCl KFUSEUYYWQURPO-UHFFFAOYSA-N 0.000 claims description 3
- POFFJVRXOKDESI-UHFFFAOYSA-N 1,3,5,7-tetraoxa-4-silaspiro[3.3]heptane-2,6-dione Chemical compound O1C(=O)O[Si]21OC(=O)O2 POFFJVRXOKDESI-UHFFFAOYSA-N 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- UKDOTCFNLHHKOF-FGRDZWBJSA-N (z)-1-chloroprop-1-ene;(z)-1,2-dichloroethene Chemical group C\C=C/Cl.Cl\C=C/Cl UKDOTCFNLHHKOF-FGRDZWBJSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000004821 distillation Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02054—Cleaning before device manufacture, i.e. Begin-Of-Line process combining dry and wet cleaning steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a silicon base surface treatment method for an NMOS element and a manufacturing method of the NMOS element. A groove is formed in a silicon base, subsequently the surface of the groove is oxidized by means of washing, and then oxides of the groove are removed to expose the surface of the silicon base. Afterwards, silicon carbonate grows on the silicon base which is subjected to the treatment steps to form a source electrode and a drain electrode so as to manufacture the NMOS element. The silicon base manufactured by the method disclosed by the invention has the advantages of high surface cleanness and low roughness. The NMOS element manufactured by adopting the silicon base disclosed by the invention is good in electrical properties.
Description
Technical field
The present invention relates to the manufacture method of a kind of surface of silicon processing method and semiconductor device, particularly a kind of processing method of surface of silicon of nmos device and the manufacture method of nmos device.
Background technology
Along with the development of IC industry, the technique reducing transistor size passed through is adopted to improve the restriction that transistor performance is more and more subject to cost and technology.Strained silicon technology by introducing the mobility that stress can improve charge carrier in traditional body silicon device, and strain CMOS does not need complicated technique based on bulk silicon technological, therefore as a kind of cheapness, efficient technology obtains applying more and more widely strained silicon technology.
Embedded carborundum source and drain technology is the one of strained silicon technology, its principle improves NMOSFET (n-channelmetal-oxide-semiconductor field-effect transistor by producing uniaxial compressive stress in channels, n channel metal oxide semiconductor field effect transistor) electron mobility, thus improve its current driving ability.Its principle is: by etched recesses on a silicon substrate, optionally epitaxial growth silicon carbide layer, because carborundum lattice constant is not mated with silicon, in perpendicular grooves direction, silicon crystal lattice is compressed generation compression, be subject to stretching along channel direction silicon crystal lattice and produce tensile stress, these stress can produce strain, and strain can excitation electron mobility improve, thus reaches the performance improving silicon device.
The pre-treating technology preparing silicon carbide epitaxial layers is disclosed in prior art, step be included in growth before prerinse before extension, cleaning equipment cleaning, hcl corrosion and silicon carbide epitaxy deposition, but this treatment process can make surface of silicon for growing silicon carbide epitaxial loayer easily because above-mentioned technique produces the coarse and surface that cleannes are lower, be therefore necessary to invent a kind of technique and surface of silicon can be made to be clean before growing silicon carbide epitaxial loayer and roughness is lower.
Summary of the invention
For solving the problem, the invention provides a kind of processing method of surface of silicon of nmos device, comprising the following steps:
Step 1 a: silicon substrate is provided;
Step 2: employing is dry-etched on described silicon substrate and forms groove;
Step 3: use acid tank one to be removed by the photoresistance being used for mask;
Step 4: the groove surfaces using acid tank two cleaning step 3;
Step 5: adopt solvent gas or sour gas and along with oxygen, be oxidized the groove in described step 4, forms oxide layer, to remove the metal ion of groove surfaces and organic impurity in described groove surfaces;
Step 6: the oxide layer removing described step 5 further groove surface with purge gas, to expose surface of silicon.
As preferably, in described step 3, acid tank one is the first acid tank, the second acid tank and the 3rd acid tank.
As preferably, containing H in described first acid tank
2o
2with dense H
2sO
4, containing NH in described second acid tank
4oH, H
2o
2and H
2o, containing HCl, H in described 3rd acid tank
2o
2and H
2o.
As preferably, in described step 4, acid tank two is the 4th acid tank, the 5th acid tank and the 6th acid tank.
As preferably, described 4th acid tank has included NH
4oH, H
2o
2and H
2o, containing HCl, H in the 5th acid tank
2o
2and H
2o, containing HF in the 6th acid tank.
As preferably, the solvent gas in described step 5 is 1,2-dichloroethene gas.
As preferably, the sour gas in described step 5 is HCl gas.
As preferably, the purge gas described in step 6 comprises NF
3and NH
3.
The present invention also provides a kind of manufacture method of nmos device, comprises the surface of silicon adopted after above-mentioned disposal methods, forms drain electrode and source electrode at described surface of silicon depositing silicon carbide.
Compared with prior art, the invention has the beneficial effects as follows: by using acid tank one, the mask photoresistance for the preparation of groove is removed clean, being oxidized groove by using mobile solvent gas or sour gas with oxygen makes it form oxide, then adopt cleaning equipment to remove oxide or the organic impurities of semiconductor crystal wafer groove surfaces, obtain the silicon substrate that surface cleanness is high, roughness is low; The nmos device adopting silicon substrate of the present invention to make can improve electron mobility, to improve the electric property of nmos device.
Accompanying drawing explanation
Fig. 1 is the process flow figure of the surface of silicon of nmos device provided by the invention;
Fig. 2 a is dry etching groove schematic diagram in the processing method of surface of silicon provided by the invention;
Fig. 2 b is that surface of silicon provided by the invention carries out dry etching rearward recess formation schematic diagram;
Fig. 3 is acid tank cleaning mask photoresistance schematic diagram in the processing method of surface of silicon provided by the invention;
Fig. 4 is oxidized groove schematic diagram in the processing method of surface of silicon provided by the invention;
Fig. 5 is the schematic diagram after the processing method of surface of silicon provided by the invention removes oxide or organic impurities;
Fig. 6 is growing silicon carbide schematic diagram in surface of silicon.
In figure: 1-mask photoresistance, 2-isolate filler, 3-silicon substrate, 4-grid, 5-groove, 6-oxide layer, 7-carborundum.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Please refer to Fig. 1, the invention provides the processing method of the surface of silicon of nmos device, comprise the following steps:
Step S1 a: silicon substrate 3 is provided;
Step S2: please refer to Fig. 2 a and Fig. 2 b, employing is dry-etched on described silicon substrate 3 and forms groove 5;
Step S3: use acid tank one will be used for mask photoresistance 1 and remove;
Step S4: please refer to Fig. 3, uses groove 5 surface of acid tank two cleaning step S3, for removing the particle of groove surfaces, organic substance residues and metal ion, as Na
+, K
+;
Step S5: please refer to Fig. 4, adopts solvent gas or sour gas and along with oxygen, is oxidized the groove 5 in described step S4, forms oxide layer 6, to remove the metal ion on groove 5 surface and organic impurity on described groove 5 surface;
Step S6: please refer to Fig. 5, removes the oxide layer 6 on described step S5 further groove 5 surface with purge gas, to expose silicon substrate 3 surface, now groove 5 surface cleanness is higher.
Preferably, in described step S3, acid tank one is the first acid tank, the second acid tank and the 3rd acid tank.
Preferably, H is contained in described first acid tank
2o
2with dense H
2sO
4, containing NH in described second acid tank
4oH, H
2o
2and H
2o, containing HCl, H in described 3rd acid tank
2o
2and H
2o.
Preferably, in described step S4, acid tank two is the 4th acid tank, the 5th acid tank and the 6th acid tank.
Preferably, described 4th acid tank has included NH
4oH, H
2o
2and H
2o, containing HCl, H in the 5th acid tank
2o
2and H
2o, containing HF in the 6th acid tank.
Preferably, solvent gas in described step S5 is 1,2-dichloroethylene gas, and the ratio of 1,2-dichloroethene gas and oxygen is less than 1:10,1, the total flow scope of 2-dichloroethylene G&O is 0.5slm ~ 10slm, nitrogen flow scope is 0slm ~ 20slm, and temperature range is 450 DEG C-800 DEG C, and time range is 0.5 minute ~ 30 minutes.
Preferably, sour gas in described step S5 is HCl gas, and the ratio of HCl gas and oxygen is less than 1:10, the total flow scope of HCl gas and oxygen is 0.5slm ~ 10slm, nitrogen flow scope is 0slm ~ 20slm, temperature range is 450 DEG C-800 DEG C, and time range is 0.5 minute ~ 30 minutes.
Preferably, the purge gas described in step S6 comprises NF
3and NH
3, and step S6 comprises following three steps:
Steps A: adjustment parameter, wherein NF
3with NH
3flow-rate ratio scope be 1:4 ~ 1:19, total gas flow rate scope is 50sccm ~ 200sccm, and pressure range is 60Pa ~ 2666Pa, and time range is 20 seconds ~ 50 seconds, etching agent generate;
Step B: adjustment parameter, starts etching, wherein, NF
3with NH
3flow-rate ratio scope be 1:4 ~ 1:19, total gas flow rate scope is 50sccm ~ 200sccm, and pressure range is 60Pa ~ 2666Pa, and temperature range is 30 DEG C ~ 50 DEG C, and time range is 5 seconds ~ 60 seconds;
Step C: adjustment parameter, will etch rear impurity distillation, wherein, pressure range is 60Pa ~ 2666Pa, and temperature range is 100 DEG C ~ 150 DEG C, and time range is 50 seconds ~ 240 seconds.
The present invention also provides a kind of manufacture method of nmos device, please refer to Fig. 6, comprises silicon substrate 3 surface adopted after above-mentioned disposal methods, after this forms drain electrode and source electrode, to form nmos device at described silicon substrate 3 surface deposition carborundum 7.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.If these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. a processing method for the surface of silicon of nmos device, is characterized in that, comprises the following steps:
Step (1) a: silicon substrate is provided;
Step (2): employing is dry-etched on described silicon substrate and forms groove;
Step (3): use acid tank one to be removed by the photoresistance being used for mask;
Step (4): the groove surfaces using acid tank two cleaning step (3);
Step (5): adopt solvent gas or sour gas and along with oxygen, be oxidized the groove in described step (4), forms oxide layer, to remove the metal ion of groove surfaces and organic impurity in described groove surfaces;
Step (6): the oxide layer removing described step (5) further groove surface with purge gas, to expose surface of silicon.
2. the processing method of the surface of silicon of nmos device as claimed in claim 1, is characterized in that, in described step (3), acid tank one is the first acid tank, the second acid tank and the 3rd acid tank.
3. the processing method of the surface of silicon of nmos device as claimed in claim 2, is characterized in that, containing H in described first acid tank
2o
2with dense H
2sO
4, containing NH in described second acid tank
4oH, H
2o
2and H
2o, containing HCl, H in described 3rd acid tank
2o
2and H
2o.
4. the processing method of the surface of silicon of nmos device as claimed in claim 1, is characterized in that, in described step (4), acid tank two is the 4th acid tank, the 5th acid tank and the 6th acid tank.
5. the processing method of the surface of silicon of nmos device as claimed in claim 4, it is characterized in that, described 4th acid tank has included NH
4oH, H
2o
2and H
2o, containing HCl, H in the 5th acid tank
2o
2and H
2o, containing HF in the 6th acid tank.
6. the processing method of the surface of silicon of nmos device as claimed in claim 1, it is characterized in that, the solvent gas in described step (5) is 1,2-dichloroethene gas.
7. the processing method of the surface of silicon of nmos device as claimed in claim 1, it is characterized in that, the sour gas in described step (5) is HCl gas.
8. the processing method of the surface of silicon of nmos device as claimed in claim 1, it is characterized in that, the purge gas described in step (6) comprises NF
3and NH
3.
9. a manufacture method for nmos device, is characterized in that, comprises and adopting as the surface of silicon in claim 1-8 as described in any one, forms drain electrode and source electrode at described surface of silicon depositing silicon carbide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410664725.0A CN104392919B (en) | 2014-11-19 | 2014-11-19 | The processing method of the surface of silicon of nmos device and the preparation method of nmos device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410664725.0A CN104392919B (en) | 2014-11-19 | 2014-11-19 | The processing method of the surface of silicon of nmos device and the preparation method of nmos device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104392919A true CN104392919A (en) | 2015-03-04 |
| CN104392919B CN104392919B (en) | 2018-03-30 |
Family
ID=52610801
Family Applications (1)
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|---|---|---|---|
| CN201410664725.0A Active CN104392919B (en) | 2014-11-19 | 2014-11-19 | The processing method of the surface of silicon of nmos device and the preparation method of nmos device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047553A (en) * | 2015-08-26 | 2015-11-11 | 上海华力微电子有限公司 | Surface treatment method for depositing high-dielectric value gate medium layer |
| CN110265285A (en) * | 2019-04-26 | 2019-09-20 | 芯盟科技有限公司 | The method for oxidation of semiconductor substrate and the manufacturing method of backside-illuminated sensor chip |
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| CN102243997A (en) * | 2010-05-12 | 2011-11-16 | 上海华虹Nec电子有限公司 | Process method for etching and cleaning oxide film in deep groove before epitaxial growth |
| CN102945793A (en) * | 2012-12-03 | 2013-02-27 | 上海集成电路研发中心有限公司 | Pre-cleaning method for epitaxial growth of Ge-Si stress layer |
| CN103824764A (en) * | 2012-11-19 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Preparation method of trench gate in trench MOS device |
-
2014
- 2014-11-19 CN CN201410664725.0A patent/CN104392919B/en active Active
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| CN1494113A (en) * | 2002-08-28 | 2004-05-05 | ��ʿͨ��ʽ���� | Method for mfg. semiconductor device with differential thickness grid insulation film |
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| CN102243997A (en) * | 2010-05-12 | 2011-11-16 | 上海华虹Nec电子有限公司 | Process method for etching and cleaning oxide film in deep groove before epitaxial growth |
| CN103824764A (en) * | 2012-11-19 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Preparation method of trench gate in trench MOS device |
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| CN110265285A (en) * | 2019-04-26 | 2019-09-20 | 芯盟科技有限公司 | The method for oxidation of semiconductor substrate and the manufacturing method of backside-illuminated sensor chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104392919B (en) | 2018-03-30 |
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