CN104333369A - DDR3 PHY SSTL15 output drive circuit - Google Patents
DDR3 PHY SSTL15 output drive circuit Download PDFInfo
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- CN104333369A CN104333369A CN201410589755.XA CN201410589755A CN104333369A CN 104333369 A CN104333369 A CN 104333369A CN 201410589755 A CN201410589755 A CN 201410589755A CN 104333369 A CN104333369 A CN 104333369A
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Abstract
The invention provides a DDR3 PHY SSTL15 output drive circuit which comprises at least one output module. The output modules are parallelly connected, each output module comprises a front drive circuit and a rear drive circuit, wherein the front drive circuit comprises six NOT gates, four NAND gates, two either-or circuits, n first output conversion circuits and n second output conversion circuits, and the rear drive circuit comprises n NMOS (N-channel metal oxide semiconductor) groups, n PMOS (P-channel metal oxide semiconductor) groups and two diodes. The DDR3 PHY SSTL15 output drive circuit can output DDR3 PHY SSTL15 data to be transmitted and can be respectively in a transmitting state and a receiving state, the front drive circuit outputs the data to be transmitted in the transmitting state, and the rear drive circuit outputs a high impedance state for impedance matching in the receiving state.
Description
Technical field
The present invention relates to electronic technology field, especially relate to a kind of DDR3 PHY SSTL15 output driving circuit.
Background technology
DDR3 PHY is used to the indispensable bridge connecting DDR3 SDAM memory and DDR3 storage control.DDR3 PHY comprises DDL, PLL, transmitter, receiver, SSTL input driving circuit, SSTL output driving circuit etc.Wherein, SSTL output driving circuit is mainly used in the data to be sent exporting DDR3 PHY.
SSTL 15 is a kind of relatively more conventional SSTL interfaces, but inventor finds after deliberation, there is not DDR3 PHY SSTL15 output driving circuit in the prior art.
Summary of the invention
The technical problem that the present invention solves is to provide a kind of DDR3 PHY SSTL15 output driving circuit, to realize the data to be sent that can export DDR3 PHY SSTL15.
In addition, the technical problem that the present invention can also solve is, DDR3 PHY SSTL15 output driving circuit provided by the invention, transmission state and accepting state can be in respectively, exporting data to be sent when being in transmission state, exporting high-impedance state when being in accepting state, for impedance matching.
For this reason, the technical scheme of technical solution problem of the present invention is:
A kind of DDR3 PHY SSTL15 output driving circuit, described output driving circuit comprises: at least one output module, output module parallel join described in each;
Wherein, each described output module comprises: front wheel driving circuit and back driving circuit; Described front wheel driving circuit comprises: the first not gate, the second not gate, the 3rd not gate, the 4th not gate, the 5th not gate, the 6th not gate, the first NAND gate, the second NAND gate, the 3rd NAND gate, the 4th NAND gate, the first multiselect one circuit, the second multiselect one circuit, n the first output conversion circuit and n the second output conversion circuit; N >=1; Described back driving circuit comprises: n NMOS group, a n PMOS group, the first diode and the second diode; Each described NMOS group comprises at least one NMOS tube, and each described PMOS group comprises at least one PMOS;
Two inputs of described first NAND gate are respectively used to receive output module enable signal and send state enable signal; Wherein, when described output module is enabled state, described output module enable signal is high level, and when described output module is disabled status, described output module enable signal is low level; When described output module is transmission state, described transmission state enable signal is high level, and when described output module is accepting state, described transmission state enable signal is low level;
The output of described first NAND gate connects the input of described first not gate, and the output of described first not gate connects the first input end of described second NAND gate and the input of described second not gate;
Second input of described second NAND gate receives the data to be sent of described output driving circuit, and the output of described second NAND gate connects the first input end of described first multiselect one circuit; Second input of described first multiselect one circuit connects ground voltage;
The output of described second not gate connects the first input end of described 3rd NAND gate; Second input of described 3rd NAND gate receives described data to be sent, and the output of described 3rd NAND gate connects the first input end of described second multiselect one circuit; Second input of described second multiselect one circuit connects supply voltage;
Two inputs of described 4th NAND gate are respectively used to receive described output module enable signal and accepting state enable signal; Wherein, when described output module is accepting state, described accepting state enable signal is high level, and when described output module is transmission state, described accepting state enable signal is low level;
The output of described 4th NAND gate connects the input of described 3rd not gate; The output of described 3rd not gate connects the selecting side of described first multiselect one circuit and the selecting side of described second multiselect one circuit; When the selecting side of described first multiselect one circuit receives low level, exported the data of first input end reception by output, when the selecting side of described first multiselect one circuit receives high level, exported the data of the second input reception by output; When the selecting side of described second multiselect one circuit receives low level, exported the data of first input end reception by output, when the selecting side of described first multiselect one circuit receives high level, exported the data of the second input reception by output;
The input of described 4th not gate is for receiving the first output conversion circuit enable signal; Wherein, when the first output conversion circuit is enabled state, described first output conversion circuit enable signal is high level, and when the first output conversion circuit is disabled status, described first output conversion circuit enable signal is low level;
Each described first output conversion circuit comprises a NAND gate and a level shifting circuit, wherein, the first input end of this NAND gate connects the output of described first multiselect one circuit, second input of this NAND gate connects the output of described 4th not gate, the output of this NAND gate connects the input of this level shifting circuit, and this level shifting circuit is used for regulation voltage to adapt to external voltage;
The input of the 5th not gate is for receiving the second output conversion circuit enable signal, and the output of described 5th not gate connects the input of described 6th not gate; Wherein, when the second output conversion circuit is enabled state, described second output conversion circuit enable signal is high level, and when the second output conversion circuit is disabled status, described second output conversion circuit enable signal is low level;
Each described second output conversion circuit comprises a NAND gate and a level shifting circuit, wherein, the first input end of this NAND gate connects the output of described second multiselect one circuit, second input of this NAND gate connects the output of described 6th not gate, the output of this NAND gate connects the input of this level shifting circuit, and this level shifting circuit is used for regulation voltage to adapt to external voltage;
All PMOS in each described PMOS group form a series circuit, one end of this series circuit connects negative pole and the supply voltage of described first diode, and the other end of this series circuit connects the positive pole of described first diode and the negative pole of described second diode; In this series circuit, the grid of each PMOS connects the grid tie point of this group; The grid tie point of each described PMOS group connects the output of the described level shifting circuit in different described first output conversion circuits respectively;
All NMOS tube in each described NMOS group form a series circuit, one end of this series circuit connects positive pole and the ground voltage of described second diode, and the other end of this series circuit connects the positive pole of described first diode and the negative pole of described second diode; In this series circuit, the grid of each NMOS tube connects the grid tie point of this group; The grid tie point of each described NMOS group connects the output of the described level shifting circuit in different described second output conversion circuits respectively;
When described output driving circuit is transmission state, the output of level shifting circuit described in each in output module described in each is the output of described output driving circuit; When described output driving circuit is accepting state, the described back driving circuit in output module described in each is used for impedance matching.
Preferably, each described first output conversion circuit and each described second output conversion circuit also comprise an edge rate control circuit; The input of this edge rate control circuit connects the output of the NAND gate in the output conversion circuit belonging to it, and the output of this edge rate control circuit connects the input of the level shifting circuit in the output conversion circuit belonging to it;
Each described edge rate control circuit comprises the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 7th not gate and the 8th not gate;
The source electrode of the source electrode of described first PMOS, the source electrode of described 3rd PMOS, described 4th PMOS connects supply voltage; The drain electrode of the drain electrode of described first PMOS, the drain electrode of described 3rd PMOS, described 4th PMOS connects the source electrode of described second PMOS; The source electrode of described first NMOS tube connects the drain electrode of the drain electrode of described second NMOS tube, the drain electrode of described 3rd NMOS tube and described 4th NMOS tube; The source electrode of described second NMOS tube, the source electrode of described 3rd NMOS tube are connected ground voltage with the source electrode of described 4th NMOS tube; The grid of the grid of described first PMOS, the grid of the second PMOS, described first NMOS tube connects the grid of described second NMOS tube, as the input of described edge rate control circuit; The drain electrode of described second PMOS connects the drain electrode of described first NMOS tube, as the output of described edge rate control circuit;
The input of described 7th not gate is used for receiving velocity control signal, the output of described 7th not gate connects the input of described 8th not gate, and the output of described 8th not gate connects the grid of the grid of described 3rd PMOS, the grid of described 4th PMOS, the grid of described 3rd NMOS tube and described 4th NMOS tube.
Preferably, described n is specially 4.
Preferably, described n PMOS group comprises four PMOS respectively, i.e. the 5th PMOS, the 6th PMOS, the 7th PMOS and the 8th PMOS, two PMOS, i.e. the 9th PMOS and the tenth PMOS, a PMOS, i.e. the 11 PMOS and a PMOS, i.e. the 12 PMOS; Described n NMOS group comprises four NMOS tube respectively, i.e. the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube and the 8th NMOS tube, two NMOS tube, i.e. the 9th NMOS tube and the tenth NMOS tube, a NMOS tube, i.e. the 11 NMOS tube and NMOS tube, i.e. the 12 NMOS tube;
The drain electrode of described 5th PMOS connects the source electrode of described 6th PMOS, the drain electrode of described PMOS connects the source electrode of described 7th PMOS, the drain electrode of described 7th PMOS connects the source electrode of described 8th PMOS, the drain electrode of described 9th PMOS connects the source electrode of described tenth PMOS, and the source electrode of described 5th PMOS connects the negative pole of the source electrode of described 9th PMOS, the source electrode of described 11 PMOS, the source electrode of described 12 PMOS, supply voltage and described first diode; The drain electrode of described 8th PMOS connects the negative pole of the drain electrode of described tenth PMOS, the drain electrode of described 11 PMOS, the drain electrode of described 12 PMOS, the positive pole of described first diode and described second diode;
The source electrode of described 5th NMOS tube connects the drain electrode of described 6th NMOS tube, the source electrode of described 6th NMOS tube connects the drain electrode of described 7th NMOS tube, the source electrode of described 7th NMOS tube connects the drain electrode of described 8th NMOS tube, the source electrode of described 9th NMOS tube connects the drain electrode of described tenth NMOS tube, and the drain electrode of described 5th NMOS tube connects the positive pole of the drain electrode of described 9th NMOS tube, the drain electrode of described 11 NMOS tube, the drain electrode of described 12 NMOS tube, the negative pole of described second diode and described first diode; The source electrode of described 8th NMOS tube connects the positive pole of the source electrode of described tenth NMOS tube, the source electrode of described 11 NMOS tube, the source electrode of described 12 NMOS tube, ground voltage and described second diode.
Preferably, described back driving circuit also comprises a NMOS tube and a PMOS, and wherein, the grid of this PMOS is connected the negative pole of described first diode with source electrode, and the drain electrode of this PMOS connects the positive pole of described first diode; The grid of this NMOS tube is connected the positive pole of described second diode with source electrode, the drain electrode of this NMOS tube connects the negative pole of described second diode.
Preferably, described level shifting circuit is used for the IO voltage described supply voltage being converted to chip.
Preferably, described output driving circuit comprises 7 output modules.
Known by technique scheme, DDR3 PHY SSTL15 output driving circuit provided by the invention comprises front wheel driving circuit and back driving circuit, achieves the data to be sent that can export DDR3 PHY SSTL15.And, DDR3 PHY SSTL15 output driving circuit in the present invention can be in transmission state and accepting state respectively, export data to be sent when being in transmission state by front wheel driving circuit, when being in accepting state, back driving circuit exports high-impedance state, for impedance matching.
Accompanying drawing explanation
Fig. 1 is the structural representation of the specific embodiment of output driving circuit provided by the invention;
Fig. 2 and Fig. 3 is the structural representation of the front wheel driving circuit in output driving circuit provided by the invention;
Fig. 4 and Fig. 5 is the structural representation of forward position provided by the invention rate control circuits;
Fig. 6 is the structural representation of the back driving circuit in output driving circuit provided by the invention.
Embodiment
DDR (Double Data Rate, i.e. Double Data Rate synchronous DRAM) 3 PHY (Physical Layer, i.e. physical layer) is used to the indispensable bridge connecting DDR3 SDAM memory and DDR3 storage control.The design of PHY simultaneously needs the standard of compatible JESD79-3, provides industrial interface DDR PHY Interface (DFI) of standard to be connected with storage control.
DDR3 PHY comprises DDL (Data Definition Language, i.e. database schema definitional language), PLL (Phase Locked Loop, i.e. phase-locked loop), transmitter, receiver, SSTL input driving circuit, SSTL output driving circuit etc.Wherein, DLL and PLL is mainly used in the conversion carrying out clock zone, transmitter and receiver are used for transmitting and receive data, and realize the serioparallel exchange of data, and SSTL output driving circuit (also referred to as SSTL output circuit) is mainly used in the data to be sent exporting DDR3 PHY.
SSTL 15 is a kind of relatively more conventional SSTL interfaces, but inventor finds after deliberation, there is not DDR3 PHY SSTL15 output driving circuit in the prior art.
Therefore, the technical problem that the present invention solves is to provide a kind of DDR3 PHY SSTL15 output driving circuit (i.e. DDR3 PHY SSTL15 output circuit), to realize the data to be sent that can export DDR3 PHY SSTL15.
Refer to Fig. 1, the invention provides the specific embodiment of DDR3 PHY SSTL15 output driving circuit, in the present embodiment, described output driving circuit comprises: at least one output module, output module parallel join described in each.Such as, in Fig. 1, what illustrate is the situation that output driving circuit comprises 7 parallel output modules.
Because the circuit of each output module is identical, therefore in the present embodiment, only introduce the structure of one of them output module.
Wherein, each output module comprises: front wheel driving circuit and back driving circuit.
As shown in Figures 2 and 3, front wheel driving circuit comprises: the first not gate d1, the second not gate d2, the 3rd not gate d3, the 4th not gate d4, the 5th not gate d5, the 6th not gate d6, the first NAND gate c1, the second NAND gate c2, the 3rd NAND gate c3, the 4th NAND gate c4, the first multiselect one circuit mux1, second multiselect one circuit mux2, n the first output conversion circuit and n the second output conversion circuit; N >=1.In fig. 2, with n for 4, namely comprise four the first output conversion circuits and four the second output conversion circuits are example.
Two inputs of the first NAND gate c1 are respectively used to receive output module enable signal EN_STR and send state enable signal OUT_EN.Wherein, when output module is enabled state, output module enable signal EN_STR is high level, and when output module is disabled status, output module enable signal EN_STR is low level; When output module is transmission state, transmission state enable signal OUT_EN is high level, and when output module is accepting state, transmission state enable signal OUT_EN is low level.
It should be noted that, in the present embodiment, each output module has a module enable signal EN_STR, when EN_STR is high level, this output module is in opening, thus can control the quantity of the output module being in opening in whole output driving circuit.
The output of the first NAND gate c1 connects the input of the first not gate d1, and the output of the first not gate d1 connects the first input end of the second NAND gate c2 and the input of the second not gate d2.
Second input of the second NAND gate c2 receives the data DATA to be sent of the output driving circuit of the present embodiment, and the output of the second NAND gate c2 connects the first input end of the first multiselect one circuit mux1; Second input of the first multiselect one circuit mux1 connects ground voltage VSS.
The output of the second not gate d2 connects the first input end of the 3rd NAND gate c3.Second input of the 3rd NAND gate c3 receives the data DATA to be sent of the output driving circuit of the present embodiment, and the output of the 3rd NAND gate c3 connects the first input end of the second multiselect one circuit mux2; Second input of the second multiselect one circuit mux2 connects supply voltage VDD.
Two inputs of the 4th NAND gate c4 are respectively used to receive output module enable signal EN_STR and accepting state enable signal CAL_EN; Wherein, when output module is accepting state, accepting state enable signal CAL_EN is high level, and when output module is transmission state, accepting state enable signal CAL_EN is low level.
The output of the 4th NAND gate c4 connects the input of the 3rd not gate d3; The output output signal MUX_EN of the 3rd not gate d3, and this output connects the selecting side of the first multiselect one circuit mux1 and the selecting side of the second multiselect one circuit mux2; When the selecting side of the first multiselect one circuit mux1 receives low level, exported the data of first input end reception by the output of the first multiselect one circuit mux1, namely have selected first input end as input.When the selecting side of the first multiselect one circuit mux1 receives high level, exported the data of the second input reception by the output of the first multiselect one circuit mux1, namely have selected the second input as input.When the selecting side of the second multiselect one circuit mux2 receives low level, exported the data of first input end reception by the output of the second multiselect one circuit mux2, namely have selected first input end as input.When the selecting side of the first multiselect one circuit mux2 receives high level, exported the data of the second input reception by the output of the second multiselect one circuit mux2, namely have selected the second input as input.
The input of the 4th not gate d4 for receiving the first output conversion circuit enable signal PU_ODT, due in Fig. 2 for n for 4, therefore PU_ODT is specially PU_ODT<3:0>; Wherein, when the first output conversion circuit is enabled state, the first output conversion circuit enable signal PU_ODT is high level, and when the first output conversion circuit is disabled status, the first output conversion circuit enable signal PU_ODT is low level.
Each first output conversion circuit comprises a NAND gate and a level shifting circuit, wherein, the first input end of this NAND gate connects the output of the first multiselect one circuit mux1, second input of this NAND gate connects the output of the 4th not gate d4, and the output of this NAND gate connects the input of this level shifting circuit.Such as, comprise four the first output conversion circuits in Fig. 2 altogether, these four first output conversion circuits comprise NAND gate c5 and level shifting circuit 1, NAND gate c6 and level shifting circuit 2, NAND gate c7 and level shifting circuit 3, NAND gate c8 and level shifting circuit 4 respectively.Wherein, NAND gate c5, NAND gate c6, NAND gate c7 and the first input end of NAND gate c8 are all connected the output of the first multiselect one circuit mux1, and NAND gate c5, NAND gate c6, NAND gate c7 and second input of NAND gate c8 are connected first output conversion circuit enable signal PU_ODT<0>, PU_ODT<1>, PU_ODT<2> and PU_ODT<3> respectively.Wherein, this level shifting circuit is used for regulation voltage to adapt to external voltage, and in fact, level shifting circuit can be that supply voltage VDD is converted to VDDIO voltage, i.e. IO (input and output) voltage of chip.Generally internal power source voltage VDD can be lower than outside VDDIO voltage, and therefore level shifting circuit can be high voltage by low voltage transition.
The input of the 5th not gate d5 for receiving the second output conversion circuit enable signal PD_ODT, due in Fig. 2 for n for 4, therefore PD_ODT is specially PD_ODT<3:0>.The output of the 5th not gate d5 connects the input of the 6th not gate d6; Wherein, when the second output conversion circuit is enabled state, the second output conversion circuit enable signal is high level, and when the second output conversion circuit is disabled status, the second output conversion circuit enable signal is low level.
Each second output conversion circuit comprises a NAND gate and a level shifting circuit, wherein, the first input end of this NAND gate connects the output of the second multiselect one circuit mux2, second input of this NAND gate connects the output of the 6th not gate d6, the output of this NAND gate connects the input of this level shifting circuit, such as, comprise four the second output conversion circuits in Fig. 2 altogether, these four second output conversion circuits comprise NAND gate c9 and level shifting circuit 5 respectively, NAND gate c10 and level shifting circuit 6, NAND gate c11 and level shifting circuit 7, NAND gate c12 and level shifting circuit 8.Wherein, NAND gate c9, NAND gate c10, NAND gate c11 and the first input end of NAND gate c12 are all connected the output of the second multiselect one circuit mux2, and NAND gate c9, NAND gate c10, NAND gate c11 and second input of NAND gate c12 are connected second output conversion circuit enable signal PD_ODT<0>, PD_ODT<1>, PD_ODT<2> and PD_ODT<3> respectively.Wherein, this level shifting circuit is used for regulation voltage to adapt to external voltage, and in fact, level shifting circuit can be that supply voltage VDD is converted to VDDIO voltage, i.e. the IO voltage of chip.Generally internal power source voltage VDD can be lower than outside VDDIO voltage, and therefore level shifting circuit can be high voltage by low voltage transition.
As shown in Figure 6, back driving circuit comprises: n NMOS group, a n PMOS group, the first diode ESD1 and the second diode ESD2; Each NMOS group comprises at least one NMOS tube, and each PMOS group comprises at least one PMOS.
All PMOS in each described PMOS group form a series circuit, one end of this series circuit connects negative pole and the supply voltage of the first diode ESD1, and the other end of this series circuit connects the positive pole of the first diode ESD1 and the negative pole of the second diode ESD2; In this series circuit, the grid of each PMOS is connected to the grid tie point in this group; The grid tie point of each PMOS group connects the output of the level shifting circuit in the first different output conversion circuits respectively.
All NMOS tube in each described NMOS group form a series circuit, and one end of this series circuit connects positive pole and the ground voltage of the second diode ESD2, and the other end of this series circuit connects the negative pole of the first diode ESD1 and the second diode ESD2; In this series circuit, the grid of each NMOS tube is to the grid tie point in this group; The grid tie point of each NMOS group connects the output of the level shifting circuit in the second different output conversion circuits respectively.
Wherein, the common port of the first diode ESD1 and the second diode ESD2 is the output of back driving circuit.
In figure 6, what in fact illustrate is a kind of optimal way that n is specially 4.In this optimal way, comprise four NMOS groups and four PMOS groups altogether, wherein, four PMOS groups comprise four PMOS (P5, P6, P7 and P8), two PMOS (P9 and P10), a PMOS (P11) and PMOS (P12) respectively; Four NMOS groups comprise four NMOS tube (N5, N6, N7 and N8), two NMOS tube (N9 and N10), a NMOS tube (N11) and NMOS tube (N12) respectively.
Wherein, the drain electrode of PMOS P5 connects the source electrode of PMOS P6, the drain electrode of PMOS P6 connects the source electrode of PMOS P7, the drain electrode of PMOS P7 connects the source electrode of PMOS P8, the drain electrode of PMOS P9 connects the source electrode of PMOS P10, and the source electrode of PMOS P5 connects source electrode, the source electrode of PMOS P11, the source electrode of PMOS P12, the negative pole of supply voltage VDD and the first diode ESD1 of PMOS P9.The drain electrode of PMOS P8 connects the drain electrode of PMOS P10, the drain electrode of PMOS P11, the drain electrode of PMOS P12 and the positive pole of the first diode ESD1 and the negative pole of the second diode ESD2.The grid of the grid of PMOS P5, the grid of PMOS P7, PMOS P7 is all connected the output signal PU_LVL<3> of the output of the level shifting circuit in the first output conversion circuit with the grid of PMOS P8.The grid of PMOS P9 is all connected the output signal PU_LVL<2> of the output of the level shifting circuit in the first output conversion circuit with the grid of PMOS P10, the grid of PMOS P11 connects the output signal PU_LVL<1> of the output of the level shifting circuit in the first output conversion circuit, and the grid of PMOS P12 connects the output signal PU_LVL<0> of the output of the level shifting circuit in the first output conversion circuit.
The source electrode of NMOS tube N5 connects the drain electrode of NMOS tube N6, the source electrode of NMOS tube N6 connects the drain electrode of NMOS tube N7, the source electrode of NMOS tube N7 connects the drain electrode of NMOS tube N8, the source electrode of NMOS tube N9 connects the drain electrode of NMOS tube N10, and the drain electrode of NMOS tube N5 connects the positive pole of the drain electrode of NMOS tube N9, the drain electrode of NMOS tube N11, the drain electrode of NMOS tube N12, the negative pole of the second diode ESD2 and the first diode ESD1.The source electrode of NMOS tube N8 connects source electrode, the source electrode of NMOS tube N11, the source electrode of NMOS tube N12, the positive pole of ground voltage VSS and the second diode ESD2 of NMOS tube N10.The grid of the grid of NMOS tube N5, the grid of NMOS tube N7, NMOS tube N7 is all connected the output signal PD_LVL<3> of the output of the level shifting circuit in the second output conversion circuit with the grid of NMOS tube N8.The grid of NMOS tube N9 is all connected the output signal PD_LVL<2> of the output of the level shifting circuit in the second output conversion circuit with the grid of NMOS tube N10, the grid of NMOS tube N11 connects the output signal PD_LVL<1> of the output of the level shifting circuit in the second output conversion circuit, and the grid of NMOS tube N12 connects the output signal PD_LVL<0> of the output of the level shifting circuit in the second output conversion circuit.
Optionally, as shown in Figure 6, back driving circuit also comprises a NMOS tube (N13) and a PMOS (P13), wherein, the grid of PMOS P13 is connected the negative pole of the first diode ESD1 with source electrode, the drain electrode of PMOS P13 connects the positive pole of the first diode ESD1.The grid of NMOS tube N13 is connected the positive pole of the second diode ESD1 with source electrode, the drain electrode of NMOS tube N13 connects the negative pole of the second diode ESD2.
In the present embodiment, when output driving circuit is transmission state, transmission state enable signal OUT_EN is high level, accepting state enable signal CAL_EN is low level, now, the output signal MUX_EN of the 3rd not gate d3 is low level, first multiselect one circuit mux1 and the second multiselect one circuit mux2 all selects data DATA to be sent to be input signal, and the output of each level shifting circuit now in each output module is the output of the output driving circuit of the present embodiment, and this output exports data DATA to be sent.And when output driving circuit is accepting state, transmission state enable signal OUT_EN is low level, accepting state enable signal CAL_EN is high level, now, MUX_EN is high level, first multiselect one circuit mux1 and the second multiselect one circuit mux2 respectively selectively voltage VSS and supply voltage VDD be input signal, now the NMOS tube in the NMOS group in back driving circuit can drag down by the output signal of each level shifting circuit, PMOS in PMOS group is drawn high, therefore, each NMOS group and the conducting of PMOS group, back driving circuit now in each output module exports high-impedance state, for impedance matching.
Known by technique scheme, the DDR3 PHY SSTL15 output driving circuit that the present embodiment provides comprises front wheel driving circuit and back driving circuit, achieves the data to be sent that can export DDR3 PHY SSTL15.And, DDR3 PHY SSTL15 output driving circuit in the present invention can be in transmission state and accepting state respectively, export data to be sent when being in transmission state by front wheel driving circuit, when being in accepting state, back driving circuit exports high-impedance state, for impedance matching.
The present embodiment has not only filled up the current blank at DDR3 PHY SSTL15 output driving circuit design aspect, but also has the following advantages:
1, DDR3 SSTL15 output driving circuit needs to realize transmission rate is 1600MHZ, and under state so at a high speed, power consumption control becomes particularly important.And the output driving circuit in the present embodiment not only meets the requirement of DDR3 standard, speed reaches 1600MHZ, achieves good physical characteristic, and the eye pattern that emulation testing goes out meets industry eye pattern standard.
2, the output driving circuit in the present embodiment, also achieves esd protection by PMOS group and NMOS group in back driving circuit, and compared to existing esd protection, the mode of this employing metal-oxide-semiconductor can save area.
3, the output driving circuit of the present embodiment, has given up and has needed to design impedance matching circuit separately, but is impedance matching circuit by back driving circuit being under accepting state compatible, and this way saves area and the power consumption of chip.
4, all control circuits have been put into front wheel driving circuit by the output driving circuit of the present embodiment, and such way can make the design of back driving circuit become succinct, effectively saves chip area and design complexities.
In the present embodiment, can also edge rate control circuit be increased, thus data transmission bauds is controlled.Particularly, each described first output conversion circuit and each described second output conversion circuit also comprise an edge rate control circuit; The input of this edge rate control circuit connects the output of the NAND gate in the output conversion circuit belonging to it, and the output of this edge rate control circuit connects the input of the level shifting circuit in the output conversion circuit belonging to it.
Because the structure of each edge rate control circuit is identical, therefore only introduce the structure of one of them edge rate control circuit below.
As shown in Figure 4 and Figure 5, each edge rate control circuit comprises the first PMOS P1, the second PMOS P2, the 3rd PMOS P3, the 4th PMOS P4, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 7th not gate d7 and the 8th not gate d8.
The source electrode of the source electrode of the first PMOS P1, the source electrode of the 3rd PMOS P3, the 4th PMOS P4 connects supply voltage VDD; The drain electrode of the drain electrode of the first PMOS P1, the drain electrode of the 3rd PMOS P3, the 4th PMOS P4 connects the source electrode of the second PMOS P2; The source electrode of the first NMOS tube N1 connects the drain electrode of the drain electrode of the second NMOS tube N2, the drain electrode of the 3rd NMOS tube N3 and the 4th NMOS tube N4; The source electrode of the second NMOS tube N2, the source electrode of the 3rd NMOS tube N3 are connected ground voltage VSS with the source electrode of the 4th NMOS tube N4; The grid of the grid of the first PMOS P1, the grid of the second PMOS P2, the first NMOS tube N1 connects the grid of the second NMOS tube N2, as the input of this edge rate control circuit; The drain electrode of the second PMOS P2 connects the drain electrode of the first NMOS tube N1, as the output of edge rate control circuit.
The input of the 7th not gate d7 is used for the input of output connection the 8th not gate d8 of receiving velocity control signal SR<1:0>, the 7th not gate d7.The output of the 8th not gate d8 connects the grid of the grid of the 3rd PMOS P3, the grid of the 4th PMOS P4, the grid of the 3rd NMOS tube N3 and the 4th NMOS tube N4.The signal that 8th not gate d8 exports is SRP<1:0> and SRN<1:0>.In the diagram, the grid connection speed control signal SRP<0> of the grid connection speed control signal SRP<1> of the 3rd PMOS P3, the 4th PMOS P4.The grid connection speed control signal SRN<0> of the grid connection speed control signal SRN<1> of the 3rd NMOS tube N3, the 4th NMOS tube N4.
If the too fast signal that may cause of signal rate transmission rebounds on the transmission line.When SR<1> is high level, corresponding SRP<1> and SRN<1> is high level; When SR<0> is high level, corresponding SRP<0> and SRN<0> is high level.Therefore when SR signal is high level, add the quantity of pull-up PMOS and pull-down NMOS pipe, increase electric current, such edge will steepening, and corresponding transmission rate will accelerate.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (7)
1. a DDR3PHY SSTL15 output driving circuit, is characterized in that, described output driving circuit comprises: at least one output module, output module parallel join described in each;
Wherein, each described output module comprises: front wheel driving circuit and back driving circuit; Described front wheel driving circuit comprises: the first not gate, the second not gate, the 3rd not gate, the 4th not gate, the 5th not gate, the 6th not gate, the first NAND gate, the second NAND gate, the 3rd NAND gate, the 4th NAND gate, the first multiselect one circuit, the second multiselect one circuit, n the first output conversion circuit and n the second output conversion circuit; N >=1; Described back driving circuit comprises: n NMOS group, a n PMOS group, the first diode and the second diode; Each described NMOS group comprises at least one NMOS tube, and each described PMOS group comprises at least one PMOS;
Two inputs of described first NAND gate are respectively used to receive output module enable signal and send state enable signal; Wherein, when described output module is enabled state, described output module enable signal is high level, and when described output module is disabled status, described output module enable signal is low level; When described output module is transmission state, described transmission state enable signal is high level, and when described output module is accepting state, described transmission state enable signal is low level;
The output of described first NAND gate connects the input of described first not gate, and the output of described first not gate connects the first input end of described second NAND gate and the input of described second not gate;
Second input of described second NAND gate receives the data to be sent of described output driving circuit, and the output of described second NAND gate connects the first input end of described first multiselect one circuit; Second input of described first multiselect one circuit connects ground voltage;
The output of described second not gate connects the first input end of described 3rd NAND gate; Second input of described 3rd NAND gate receives described data to be sent, and the output of described 3rd NAND gate connects the first input end of described second multiselect one circuit; Second input of described second multiselect one circuit connects supply voltage;
Two inputs of described 4th NAND gate are respectively used to receive described output module enable signal and accepting state enable signal; Wherein, when described output module is accepting state, described accepting state enable signal is high level, and when described output module is transmission state, described accepting state enable signal is low level;
The output of described 4th NAND gate connects the input of described 3rd not gate; The output of described 3rd not gate connects the selecting side of described first multiselect one circuit and the selecting side of described second multiselect one circuit; When the selecting side of described first multiselect one circuit receives low level, exported the data of first input end reception by output, when the selecting side of described first multiselect one circuit receives high level, exported the data of the second input reception by output; When the selecting side of described second multiselect one circuit receives low level, exported the data of first input end reception by output, when the selecting side of described first multiselect one circuit receives high level, exported the data of the second input reception by output;
The input of described 4th not gate is for receiving the first output conversion circuit enable signal; Wherein, when the first output conversion circuit is enabled state, described first output conversion circuit enable signal is high level, and when the first output conversion circuit is disabled status, described first output conversion circuit enable signal is low level;
Each described first output conversion circuit comprises a NAND gate and a level shifting circuit, wherein, the first input end of this NAND gate connects the output of described first multiselect one circuit, second input of this NAND gate connects the output of described 4th not gate, the output of this NAND gate connects the input of this level shifting circuit, and this level shifting circuit is used for regulation voltage to adapt to external voltage;
The input of the 5th not gate is for receiving the second output conversion circuit enable signal, and the output of described 5th not gate connects the input of described 6th not gate; Wherein, when the second output conversion circuit is enabled state, described second output conversion circuit enable signal is high level, and when the second output conversion circuit is disabled status, described second output conversion circuit enable signal is low level;
Each described second output conversion circuit comprises a NAND gate and a level shifting circuit, wherein, the first input end of this NAND gate connects the output of described second multiselect one circuit, second input of this NAND gate connects the output of described 6th not gate, the output of this NAND gate connects the input of this level shifting circuit, and this level shifting circuit is used for regulation voltage to adapt to external voltage;
All PMOS in each described PMOS group form a series circuit, one end of this series circuit connects negative pole and the supply voltage of described first diode, and the other end of this series circuit connects the positive pole of described first diode and the negative pole of described second diode; In this series circuit, the grid of each PMOS connects the grid tie point of this group; The grid tie point of each described PMOS group connects the output of the described level shifting circuit in different described first output conversion circuits respectively;
All NMOS tube in each described NMOS group form a series circuit, one end of this series circuit connects positive pole and the ground voltage of described second diode, and the other end of this series circuit connects the positive pole of described first diode and the negative pole of described second diode; In this series circuit, the grid of each NMOS tube connects the grid tie point of this group; The grid tie point of each described NMOS group connects the output of the described level shifting circuit in different described second output conversion circuits respectively;
When described output driving circuit is transmission state, the output of level shifting circuit described in each in output module described in each is the output of described output driving circuit; When described output driving circuit is accepting state, the described back driving circuit in output module described in each is used for impedance matching.
2. output driving circuit according to claim 1, is characterized in that, each described first output conversion circuit and each described second output conversion circuit also comprise an edge rate control circuit; The input of this edge rate control circuit connects the output of the NAND gate in the output conversion circuit belonging to it, and the output of this edge rate control circuit connects the input of the level shifting circuit in the output conversion circuit belonging to it;
Each described edge rate control circuit comprises the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 7th not gate and the 8th not gate;
The source electrode of the source electrode of described first PMOS, the source electrode of described 3rd PMOS, described 4th PMOS connects supply voltage; The drain electrode of the drain electrode of described first PMOS, the drain electrode of described 3rd PMOS, described 4th PMOS connects the source electrode of described second PMOS; The source electrode of described first NMOS tube connects the drain electrode of the drain electrode of described second NMOS tube, the drain electrode of described 3rd NMOS tube and described 4th NMOS tube; The source electrode of described second NMOS tube, the source electrode of described 3rd NMOS tube are connected ground voltage with the source electrode of described 4th NMOS tube; The grid of the grid of described first PMOS, the grid of the second PMOS, described first NMOS tube connects the grid of described second NMOS tube, as the input of described edge rate control circuit; The drain electrode of described second PMOS connects the drain electrode of described first NMOS tube, as the output of described edge rate control circuit;
The input of described 7th not gate is used for receiving velocity control signal, the output of described 7th not gate connects the input of described 8th not gate, and the output of described 8th not gate connects the grid of the grid of described 3rd PMOS, the grid of described 4th PMOS, the grid of described 3rd NMOS tube and described 4th NMOS tube.
3. output driving circuit according to claim 1 and 2, is characterized in that, described n is specially 4.
4. output driving circuit according to claim 3, it is characterized in that, described n PMOS group comprises four PMOS respectively, i.e. the 5th PMOS, the 6th PMOS, the 7th PMOS and the 8th PMOS, two PMOS, i.e. the 9th PMOS and the tenth PMOS, a PMOS, i.e. the 11 PMOS and a PMOS, i.e. the 12 PMOS; Described n NMOS group comprises four NMOS tube respectively, i.e. the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube and the 8th NMOS tube, two NMOS tube, i.e. the 9th NMOS tube and the tenth NMOS tube, a NMOS tube, i.e. the 11 NMOS tube and NMOS tube, i.e. the 12 NMOS tube;
The drain electrode of described 5th PMOS connects the source electrode of described 6th PMOS, the drain electrode of described PMOS connects the source electrode of described 7th PMOS, the drain electrode of described 7th PMOS connects the source electrode of described 8th PMOS, the drain electrode of described 9th PMOS connects the source electrode of described tenth PMOS, and the source electrode of described 5th PMOS connects the negative pole of the source electrode of described 9th PMOS, the source electrode of described 11 PMOS, the source electrode of described 12 PMOS, supply voltage and described first diode; The drain electrode of described 8th PMOS connects the negative pole of the drain electrode of described tenth PMOS, the drain electrode of described 11 PMOS, the drain electrode of described 12 PMOS, the positive pole of described first diode and described second diode;
The source electrode of described 5th NMOS tube connects the drain electrode of described 6th NMOS tube, the source electrode of described 6th NMOS tube connects the drain electrode of described 7th NMOS tube, the source electrode of described 7th NMOS tube connects the drain electrode of described 8th NMOS tube, the source electrode of described 9th NMOS tube connects the drain electrode of described tenth NMOS tube, and the drain electrode of described 5th NMOS tube connects the positive pole of the drain electrode of described 9th NMOS tube, the drain electrode of described 11 NMOS tube, the drain electrode of described 12 NMOS tube, the negative pole of described second diode and described first diode; The source electrode of described 8th NMOS tube connects the positive pole of the source electrode of described tenth NMOS tube, the source electrode of described 11 NMOS tube, the source electrode of described 12 NMOS tube, ground voltage and described second diode.
5. output driving circuit according to claim 1 and 2, it is characterized in that, described back driving circuit also comprises a NMOS tube and a PMOS, wherein, the grid of this PMOS is connected the negative pole of described first diode with source electrode, the drain electrode of this PMOS connects the positive pole of described first diode; The grid of this NMOS tube is connected the positive pole of described second diode with source electrode, the drain electrode of this NMOS tube connects the negative pole of described second diode.
6. output driving circuit according to claim 1 and 2, is characterized in that, described level shifting circuit is used for the IO voltage described supply voltage being converted to chip.
7. output driving circuit according to claim 1 and 2, is characterized in that, described output driving circuit comprises 7 output modules.
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| CN109905119A (en) * | 2017-12-08 | 2019-06-18 | 武汉精立电子技术有限公司 | A kind of device generating C_PHY signal based on double SSTL circuits |
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