CN104302112A - Bad board identification method in manufacturing process of PCB - Google Patents
Bad board identification method in manufacturing process of PCB Download PDFInfo
- Publication number
- CN104302112A CN104302112A CN201410623643.1A CN201410623643A CN104302112A CN 104302112 A CN104302112 A CN 104302112A CN 201410623643 A CN201410623643 A CN 201410623643A CN 104302112 A CN104302112 A CN 104302112A
- Authority
- CN
- China
- Prior art keywords
- bad plate
- recognition result
- chip mounter
- jigsaw
- bad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Screen Printers (AREA)
Abstract
The invention provides a bad board identification method in a manufacturing process of a PCB. The method comprises the following steps: a solder paste printing inspection machine performs bad plate mark identification; the solder paste printing inspection machine generates a bad plate mark identification result; the solder paste printing inspection machine transmits the bad plate mark identification result to a chip mounter; the chip mounter produces a mounted chip according to the bad plate mark identification result. According to the method, a bad plate mark identification program is conducted earlier, process equipment prior to the chip mounter namely the solder paste printing inspection machine performs bad plate mark identification, and the chip mounter does not need to execute bad plate mark identification operation and only needs to read the bad plate mark identification result for production, so that the mounting efficiency of the chip mounter is improved.
Description
Technical field
The present invention relates to pcb board manufacture technology field, be specifically related to the bad plate recognition methods in a kind of pcb board manufacturing process.
Background technology
SMT(surface mount technology, surface mounting technology) be the technology of current electronic product production extensive use, wherein main production equipments is chip mounter, and the speed of production of chip mounter and efficiency determine whole piece SMT line speed of production and efficiency.Current electronic product is overall towards miniaturized and diversified development, and during attachment miniaturized products, because cost and efficiency factor is considered, PCB design adopts many jigsaw mode.
When producing many jigsaw mode, if PCB supplied materials is complete good plate, do not need during paster to identify bad plate mark (Badmark); But due to processing procedure restriction, mostly there is bad plate in PCB supplied materials, need during paster to open bad plate marker recognition function to identify bad plate.When jigsaw number is many, chip mounter spends in and identifies that the time of bad plate is many, has greatly dragged down the attachment efficiency of chip mounter.Such as 60 jigsaw PCB, the time mounting 1 monoblock PCB is 60 seconds, and the 60 jigsaw bad plates mark times that identified reach 6 seconds, identify that the bad plate time reaches 10% in the attachment ratio that accounts for cycle time, placement speed and efficiency are relative to identifying that the complete good plate of bad plate reduces 10%.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of bad plate recognition methods, in the method, chip mounter itself does not perform and identifies bad plate action, identify that bad plate action is completed by the equipment of chip mounter preceding processes, such as paste solder printing inspection machine (SPI) completes and identifies bad plate mark, chip mounter directly reads by network the information that SPI identifies bad plate, saves the time of chip mounter identification bad plate, greatly improves Placement efficiency.
Technical scheme of the present invention is: the bad plate recognition methods in a kind of pcb board manufacturing process, and it comprises:
Paste solder printing inspection machine carries out bad plate marker recognition;
Described paste solder printing inspection machine generates bad plate marker recognition result;
Described paste solder printing inspection machine sends described bad plate marker recognition result to chip mounter;
Described chip mounter carries out paster production according to described bad plate marker recognition result.
Preferably, described paste solder printing inspection machine generates the concrete grammar of bad plate marker recognition result and is:
Described stencil printer puts in order by jigsaw and identifies each jigsaw one by one, and generates recognition result file respectively for described each jigsaw, and described recognition result file comprises the information whether its corresponding jigsaw is bad plate.
Preferably, the concrete grammar that described bad plate marker recognition result sends chip mounter to is by described paste solder printing inspection machine:
Described paste solder printing inspection machine is by described recognition result file output to any file produced on spider lines, and described chip mounter is by producing the recognition result fileinfo in the described any file of spider lines acquisition.
Preferably, the concrete grammar that described chip mounter carries out paster production according to described bad plate marker recognition result is:
Described chip mounter reads the recognition result file corresponding to each jigsaw respectively, if the value of the bad plate mark badmark in described recognition result file is 0, then assert that the jigsaw of its correspondence is good plate, described chip mounter carries out paster production on this good plate, if the value of the bad plate mark badmark in described recognition result file is 1, then assert that the jigsaw corresponding to it is bad plate, described bad plate discards by described chip mounter.
Preferably, the filename of described recognition result file comprises the number information of its corresponding jigsaw, and described chip mounter reads the recognition result file corresponding to each jigsaw respectively according to the number information in described filename.
The invention has the beneficial effects as follows:
1., by adopting bad plate mark (Badmark) mode of reach to produce, avoiding chip mounter and performing bad plate marker recognition, saving the chip mounter identification bad plate mark time, improve chip mounter production efficiency.
2. by adopting bad plate mark reach mode to produce, SMT paster program discharge and optimization need not be considered to distinguish complete good plate and bad plate, adjustment and the optimization variation of paster program are simple, and operator does not need midway to open and close identification bad plate and teaching operation, and work flow simplifies.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, accompanying drawing required in describing embodiment is done simple introduction below, apparently, accompanying drawing described below is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic flow sheet of the inventive method.
Fig. 2 is jigsaw arrangement method for numbering serial schematic diagram in embodiments of the invention.
Embodiment
Elaborate below in conjunction with the embodiment of Figure of description to the embodiment of the present invention.
See Fig. 1, the bad plate recognition methods in a kind of pcb board manufacturing process of the present invention comprises the steps.
S101: paste solder printing inspection machine identification bad plate marks;
Suppose in the present embodiment that one piece of pcb board is made up of 12 pieces of jigsaw, and to every block jigsaw by from left to right, order is from bottom to up numbered, as shown in Figure 2, paste solder printing inspection machine carries out bad plate marker recognition according to above-mentioned number order one by one to every block jigsaw, concrete grammar and the correlation method of the prior art of bad plate marker recognition are similar, repeat no more herein.
It should be noted that, the number order of above-mentioned each jigsaw also can be from left to right, the mode such as from top to bottom, and do not limited by the present embodiment, the every other jigsaw numbering that can realize the inventive method puts in order and all should belong to limited range of the present invention.
S102: paste solder printing inspection machine generates bad plate marker recognition result;
Paste solder printing inspection machine is according to bad plate marker recognition situation, recognition result file is generated respectively for every block jigsaw, this recognition result file comprises the information whether its corresponding jigsaw is bad plate, jigsaw number information can be comprised in the filename of above-mentioned recognition result file, as filename can be: 16-20140507114110-1.BRD, wherein " 16 " represent the feeder number in the jigsaw identified, " 20140507 " representative performs the date of bad plate identification, " 114110 " represent the Hour Minute Second on the bad plate identification same day, "-1 " represents the jigsaw numbering identified, the naming rule of described filename can require to change according to chip mounter.The content of described recognition result file specifically can be:
<?xml?version=1.0?encoding=UTF-8?>
<BoardInformation>
<Element>
<Lane>l</Lane>
<BoardNumber>BK-5H</BoardNumber>
<BoardBarcode>JET_000021</?BoardBarcode?>
<BadMark>00000000000000000000000000000000000000000</BadMark>
<Element>
</BoardInformation>
<BadMark> item wherein have recorded the value of bad plate mark, in said procedure, the value of <BadMark> is 0, represent that the jigsaw of this identification is good plate, if the value of <BadMark> is 1, then represent that the jigsaw of its correspondence is bad plate.
S103: described paste solder printing inspection machine sends described bad plate marker recognition result to chip mounter.
In above-mentioned steps S102, generate the recognition result file with jigsaw number same number, above-mentioned recognition result file is all uploaded to any one file produced on spider lines by described paste solder printing inspection machine, and chip mounter can obtain the recognition result fileinfo in this file by product spider lines.
S104: described chip mounter carries out paster production according to described bad plate marker recognition result;
Described chip mounter obtains each recognition result file in described file, and the <BadMark> item information read respectively in described each recognition result file, if the value of <BadMark> item is 0, then assert that the jigsaw of its correspondence is good plate, described chip mounter carries out paster production on this good plate, if the value of <BadMark> item is 1, then assert that the jigsaw corresponding to it is bad plate, described bad plate discards by described chip mounter, when practical application, also different settings can be carried out, as the value setting <BadMark> be 1 time, represent that the jigsaw of this identification is good plate, and when the value of <BadMark> is 0, represent that the jigsaw of its correspondence is bad plate.Corresponding relation between the value of described <BadMark> item and jigsaw can be numbered by the jigsaw in the filename of each recognition result file and determined.The bad plate label information that described chip mounter reads is as shown in table 1 below according to the number order arrangement of jigsaw.Described chip mounter is according to the number order of jigsaw, and namely from left to right, bad plate flag code read from bottom to up is followed successively by 000110001110.
Table 1
The present invention is by moving forward bad plate marker recognition program, namely bad plate marker recognition is performed by the processing apparatus paste solder printing inspection machine before chip mounter, and chip mounter only need read bad plate marker recognition result produces, without the need to performing the action of bad plate marker recognition, improve the attachment efficiency of chip mounter.
The above embodiment only have expressed preferred embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (5)
1. the bad plate recognition methods in pcb board manufacturing process, it is characterized in that, described method comprises:
Paste solder printing inspection machine carries out bad plate marker recognition;
Described paste solder printing inspection machine generates bad plate marker recognition result;
Described paste solder printing inspection machine sends described bad plate marker recognition result to chip mounter;
Described chip mounter carries out paster production according to described bad plate marker recognition result.
2. the bad plate recognition methods in a kind of pcb board manufacturing process according to claim 1, is characterized in that, the concrete grammar that described paste solder printing inspection machine generates bad plate marker recognition result is:
Described stencil printer puts in order by jigsaw and identifies each jigsaw one by one, and generates recognition result file respectively for described each jigsaw, and described recognition result file comprises the information whether its corresponding jigsaw is bad plate.
3. the bad plate recognition methods in a kind of pcb board manufacturing process according to claim 2, is characterized in that, the concrete grammar that described bad plate marker recognition result sends chip mounter to is by described paste solder printing inspection machine:
Described paste solder printing inspection machine is by described recognition result file output to any file produced on spider lines, and described chip mounter is by producing the recognition result fileinfo in the described any file of spider lines acquisition.
4. the bad plate recognition methods in a kind of pcb board manufacturing process according to claim 3, is characterized in that, the concrete grammar that described chip mounter carries out paster production according to described bad plate marker recognition result is:
Described chip mounter reads the recognition result file corresponding to each jigsaw respectively, if the value of the bad plate mark badmark in described recognition result file is 0, then assert that the jigsaw of its correspondence is good plate, described chip mounter carries out paster production on this good plate, if the value of the bad plate mark badmark in described recognition result file is 1, then assert that the jigsaw corresponding to it is bad plate, described bad plate discards by described chip mounter.
5. the bad plate recognition methods in a kind of pcb board manufacturing process according to claim 4, it is characterized in that, the filename of described recognition result file comprises the number information of its corresponding jigsaw, and described chip mounter reads the recognition result file corresponding to each jigsaw respectively according to the number information in described filename.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410623643.1A CN104302112A (en) | 2014-11-07 | 2014-11-07 | Bad board identification method in manufacturing process of PCB |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410623643.1A CN104302112A (en) | 2014-11-07 | 2014-11-07 | Bad board identification method in manufacturing process of PCB |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104302112A true CN104302112A (en) | 2015-01-21 |
Family
ID=52321607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410623643.1A Pending CN104302112A (en) | 2014-11-07 | 2014-11-07 | Bad board identification method in manufacturing process of PCB |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104302112A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105873358A (en) * | 2016-05-31 | 2016-08-17 | 广东欧珀移动通信有限公司 | Circuit board jointed board |
| CN106211621A (en) * | 2016-07-25 | 2016-12-07 | 深圳天珑无线科技有限公司 | A kind of circuit board manufacturing method |
| CN106231812A (en) * | 2016-10-09 | 2016-12-14 | 陈欢欢 | A kind of self adaptation heterogenous patch system and pasting method thereof |
| CN112074103A (en) * | 2019-06-11 | 2020-12-11 | Oppo（重庆）智能科技有限公司 | Patch assembly, metal sheet and patch method |
| CN112340109A (en) * | 2021-01-07 | 2021-02-09 | 深圳和美精艺半导体科技股份有限公司 | Automatic forking machine device and forking method before packaging of packaging substrate |
| CN112579540A (en) * | 2020-11-03 | 2021-03-30 | 珠海越亚半导体股份有限公司 | Component mounting position identification method, mounting control method, device and medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101071156A (en) * | 2006-05-11 | 2007-11-14 | 鸿骐昶驎科技股份有限公司 | Multi-connecting board bad-product detecting device and method |
| CN201115318Y (en) * | 2007-09-25 | 2008-09-10 | 比亚迪股份有限公司 | Carrier with marking function |
| JP2011114099A (en) * | 2009-11-25 | 2011-06-09 | Fujikura Ltd | Method of manufacturing wiring board |
| CN102740667A (en) * | 2011-04-11 | 2012-10-17 | 鸿骐新技股份有限公司 | Placement method for integrating circuit board information |
-
2014
- 2014-11-07 CN CN201410623643.1A patent/CN104302112A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101071156A (en) * | 2006-05-11 | 2007-11-14 | 鸿骐昶驎科技股份有限公司 | Multi-connecting board bad-product detecting device and method |
| CN201115318Y (en) * | 2007-09-25 | 2008-09-10 | 比亚迪股份有限公司 | Carrier with marking function |
| JP2011114099A (en) * | 2009-11-25 | 2011-06-09 | Fujikura Ltd | Method of manufacturing wiring board |
| CN102740667A (en) * | 2011-04-11 | 2012-10-17 | 鸿骐新技股份有限公司 | Placement method for integrating circuit board information |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105873358A (en) * | 2016-05-31 | 2016-08-17 | 广东欧珀移动通信有限公司 | Circuit board jointed board |
| CN105873358B (en) * | 2016-05-31 | 2019-02-05 | Oppo广东移动通信有限公司 | Multiple-printed-panel for circuit board |
| CN106211621A (en) * | 2016-07-25 | 2016-12-07 | 深圳天珑无线科技有限公司 | A kind of circuit board manufacturing method |
| CN106231812A (en) * | 2016-10-09 | 2016-12-14 | 陈欢欢 | A kind of self adaptation heterogenous patch system and pasting method thereof |
| CN106231812B (en) * | 2016-10-09 | 2018-12-21 | 陈欢欢 | A kind of adaptive heterogenous patch system and its pasting method |
| CN112074103A (en) * | 2019-06-11 | 2020-12-11 | Oppo（重庆）智能科技有限公司 | Patch assembly, metal sheet and patch method |
| CN112074103B (en) * | 2019-06-11 | 2022-04-01 | Oppo（重庆）智能科技有限公司 | Patch assembly, metal sheet and patch method |
| CN112579540A (en) * | 2020-11-03 | 2021-03-30 | 珠海越亚半导体股份有限公司 | Component mounting position identification method, mounting control method, device and medium |
| CN112340109A (en) * | 2021-01-07 | 2021-02-09 | 深圳和美精艺半导体科技股份有限公司 | Automatic forking machine device and forking method before packaging of packaging substrate |
| CN112340109B (en) * | 2021-01-07 | 2021-04-23 | 深圳和美精艺半导体科技股份有限公司 | Automatic forking machine device and forking method before packaging of packaging substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104302112A (en) | Bad board identification method in manufacturing process of PCB | |
| WO2008086063A8 (en) | Method and apparatus for processing data at a wireless station | |
| CN104797084A (en) | Layout method and layout device for printed circuit boards | |
| CN104289832A (en) | Method for accurately indicating welding positions of components and working table | |
| CN103020586A (en) | Method, device and system for identifying PCB (printed circuit board) | |
| CN204539627U (en) | A kind of flexible PCB automatic printing equipment | |
| CN102501657B (en) | Screen printing alignment method | |
| CN102107552A (en) | Surface mount technology (SMT) printing steel mesh | |
| CN203228971U (en) | Labelling equipment of information module | |
| CN110378625A (en) | A kind of processing workshop energy management system based on data analysis | |
| CN202019517U (en) | Double-end light emitting diode (LED) light bar surface mounting machine | |
| CN203327396U (en) | SMT production line | |
| CN102946694A (en) | Surface mounting technology for components of integrated electronic modules | |
| CN107241863A (en) | Automatic processing equipment and method for photoelectric printed circuit board | |
| CN202404039U (en) | Multi-connection panel detecting device | |
| CN204605208U (en) | A kind of plate concentrator marker | |
| CN203957505U (en) | A kind of smart tags that is applied to prints the conveyer belt on line machine | |
| CN201785541U (en) | Device for automatically controlling current of rectifier | |
| CN205853570U (en) | A kind of three-in-one platemaking machine | |
| CN205275756U (en) | Electroplating clamp | |
| CN102595802B (en) | Method for automatically controlling plate delivery of light-emitting diode (LED) chip mounter | |
| CN204377261U (en) | A kind of modified model chip mounter | |
| CN206517677U (en) | A kind of pcb board automatic cutting device | |
| CN202340344U (en) | Double-head chip mounter with mechanical CCD (Charge Coupled Device) alignment function | |
| CN107396548A (en) | A kind of mainboard production line automation manages remodeling method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150121 |