CN104298033A - 一种像素结构及其制备方法、显示面板及显示装置 - Google Patents

一种像素结构及其制备方法、显示面板及显示装置 Download PDF

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CN104298033A
CN104298033A CN201410484549.2A CN201410484549A CN104298033A CN 104298033 A CN104298033 A CN 104298033A CN 201410484549 A CN201410484549 A CN 201410484549A CN 104298033 A CN104298033 A CN 104298033A
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data line
groove
pixel
dot structure
pixel electrode
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CN104298033B (zh
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陈磊
彭志龙
代伍坤
刘还平
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明涉及一种像素结构及其制备方法、显示面板及显示装置，所述像素结构包括多列像素以及多条位于相邻列像素间的数据线，每个像素包括像素电极以及具有栅极、有源层、源极和漏极的薄膜晶体管，所述栅极与有源层间设有栅极保护层，所述栅极保护层中设有至少部分位于两相邻列像素之间的沟槽；两相邻列像素的像素电极的相对端部，以及两相邻列像素之间的数据线中，一个位于所述沟槽内，另一个位于所述栅极保护层无沟槽处的表面上。所述像素结构可以减小数据线与像素电极之间的电容耦合效应，从而减小对数据线中信号传输的干扰，此外，还可以减小像素结构制备过程中的工艺波动对像素性能及其均一性的影响。

Description

一种像素结构及其制备方法、显示面板及显示装置
技术领域
本发明涉及液晶显示技术领域，具体地，涉及一种像素结构及其制备方法，以及包含上述像素结构的显示面板，包含上述显示面板的显示装置。
背景技术
随着显示技术的不断进步，显示装置的分辨率越来越高，在显示装置的尺寸不变的情况下，单位面积上的像素密度也随之升高；而伴随着像素密度的提高，相邻像素结构之间的距离，以及每个像素结构内各单元之间的距离越来越小。
图1为一种现有显示装置的像素结构的示意图，图2为图1所示像素结构沿A-A’的剖视图。如图1和图2所示，每个像素包括像素电极1以及具有栅极、有源层、源极和漏极组成的薄膜晶体管(TFT)，所述栅极与有源层之间设置有栅极保护层4，具体地，栅极保护层4一般设置在每个像素所在区域，以及相邻像素之间的区域。在相邻两列像素之间设有数据线2，在相邻两行像素之间设有栅极线3，所述数据线2与像素电极1之间设置在一个平面上。
在相邻像素之间的距离，以及每个像素内各单元之间的距离越来越小时，可以理解，像素电极1和数据线2之间的距离越来越小，在此情况下，由于距离的减小，像素电极1与数据线2之间容易产生电容耦合效应，对数据线2及其他信号线中所传输的信号产生干扰。此外，像素电极1和数据线2之间距离的减小，还会使得制备像素结构的过程中的工艺波动对像素中各单元的形状的影响增大，从而影响像素的性能，进而影响显示装置的显示效果。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提出了一种像素结构及其制备方法、显示面板及显示装置，所述像素结构可以增大数据线与像素电极之间的距离，从而减小数据线和像素电极之间的电容耦合效应，还可以减小像素结构制备过程中的工艺波动对像素性能及其均一性的影响。
为实现本发明的目的而提供一种像素结构，包括多列像素以及多条位于相邻列像素间的数据线，每个像素包括像素电极以及具有栅极、有源层、源极和漏极的薄膜晶体管，所述栅极与有源层间设有栅极保护层，所述栅极保护层中设有至少部分位于两相邻列像素之间的沟槽；两相邻列像素的像素电极的相对端部，以及两相邻列像素之间的数据线中，一个位于所述沟槽内，另一个位于所述栅极保护层无沟槽处的表面上。
其中，所述沟槽设置在与数据线对应的区域，所述数据线设置在所述沟槽内。
其中，所述沟槽的最大深度小于所述栅极保护层的厚度。
其中，所述沟槽位于数据线两侧，且所述两相邻列像素的像素电极的相对端部位于在所述沟槽内。
其中，所述像素电极的靠近所述数据线的端部设置在所述沟槽的底部。
其中，所述沟槽的深度等于所述栅极保护层的厚度。
作为另一个技术方案，本发明还提供一种像素结构的制备方法，包括：制备栅极的步骤；制备栅极保护层的步骤；在栅极保护层上制备至少部分位于两相邻列像素之间的沟槽的步骤。
其中，所述沟槽设置在与数据线对应的区域，所述像素结构的制备方法还包括：在所述沟槽内制备数据线的步骤。
其中，所述沟槽分别设置在数据线的两侧；所述像素结构的制备方法还包括：在包括所述沟槽，且以所述沟槽为边缘的区域内制备像素电极的步骤。
作为另一个技术方案，本发明还提供一种显示面板，包括本发明提供的上述像素结构。
作为另一个技术方案，本发明还提供一种显示装置，包括本发明提供的上述显示面板。
本发明具有以下有益效果：
本发明提供的像素结构，其通过在栅极保护层上设置沟槽，并将像素电极的端部设置在沟槽内，或者将数据线设置在沟槽内，使像素电极的端部与数据线不在同一垂直于沟槽的深度方向的平面内，这样在不改变二者在垂直于沟槽深度方向上的距离的情况下，增大像素电极和数据线之间的总距离，从而可以减小像素电极与数据线之间的电容耦合效应，从而可以减小对数据线以及其他信号线中信号传输的干扰。此外，通过增大像素电极与数据线之间的总距离，还可以在制备像素结构的过程中，降低工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能及其均一性，从而可以保证显示装置的显示效果。
本发明提供的像素结构的制备方法，通过在栅极保护层上制备沟槽，并将数据线，或者像素电极的端部设置在沟槽内，使像素电极的端部与数据线不在同一垂直于沟槽的深度方向的平面内，这样在不改变二者在垂直于沟槽深度方向上的距离的情况下，增大数据线与像素电极之间的总距离，从而可以降低数据线及像素电极之间的耦合电容，减小对数据线以及其他信号线中信号传输的干扰。此外，通过增大像素电极与数据线之间总距离，还可以在制备像素结构的过程中，降低工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能及其均一性。
本发明提供的显示面板，其包括本发明提供的上述像素结构，可以降低数据线和像素电极之间的电容耦合效应，从而减小对数据线以及其他信号线中信号传输的干扰；还可以减小像素结构制备过程中的工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能以及均匀性，进而可以保证显示面板的显示效果。
本发明提供的显示装置，其包括本发明提供的上述显示面板，可以降低数据线和像素电极之间的电容耦合效应，从而减小对数据线以及其他信号线中信号传输的干扰；还可以减小像素结构制备过程中的工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能以及均匀性，进而可以保证显示面板的显示效果。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1为一种现有显示装置的像素结构的示意图，
图2为图1所示像素结构沿A-A’的剖视图；
图3为本发明像素结构的第一种实施方式的示意图；
图4为图3所示像素结构沿B-B’的剖视图；
图5为本发明像素结构的第二种实施方式的示意图；
图6为图5所示像素结构沿C-C’的剖视图；
图7为本发明提供的像素结构的制备方法的优选实施方式的流程图。
其中附图标记分别表示：
1：像素电极；2：数据线；3：栅极线；4：栅极保护层；5：沟槽。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
请参看图3和图4，图3为本发明像素结构的第一种实施方式的示意图，图4为图3所示像素结构沿B-B’的剖视图。在本实施方式中，像素结构包括多列像素以及多条位于相邻列像素间的数据线，每个像素包括像素电极1以及具有栅极、有源层、源极和漏极的薄膜晶体管，在所述栅极与有源层之间的栅极保护层4，所述栅极保护层4中设有至少部分位于两相邻列像素之间的沟槽5。具体地，沟槽5位于所述数据线2的两侧，所述两相邻列像素的像素电极1的相对端部位于所述沟槽5内，数据线2位于所述栅极保护层4无沟槽5处的表面上。
具体地，所述像素电极1除其端部外的其他区域与数据线2位于同一垂直于沟槽5深度方向的平面内。在本实施方式中，通过在栅极保护层4上与每个像素电极1的端部对应的区域设置沟槽5，使每个像素电极1的靠近数据线2的端部位于所述沟槽5内，也就是，使每个像素电极1的端部与数据线2不处在同一垂直于沟槽5深度方向的平面内，从而在每个像素电极1的端部与数据线2之间在垂直于沟槽5深度方向上的距离(即现有技术中像素电极1的端部与数据线2之间的距离)不变的情况下，增大像素电极1的端部与数据线2之间的总距离，从而与现有技术相比，本实施方式增大了像素电极1的端部与数据线2之间的距离，在此情况下，由于距离的增大，可以减小像素电极1与数据线2之间的电容耦合效应，从而可以减小对数据线2以及其他信号线中信号传输的干扰。此外，像素电极1的端部与数据线2之间的距离的增大，还可以在制备像素结构的过程中，降低工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能及其均一性，从而可以保证显示装置的显示效果。
在本实施方式中，优选地，像素电极1的靠近数据线2的端部设置在沟槽5的底部，这样可以使像素电极1的端部与数据线2之间在沟槽5的深度方向上的距离尽可能地大，从而在像素电极1与数据线2之间的在垂直于沟槽5的深度方向上的距离不变的情况下，可以最大程度地增加像素电极1与数据线2之间的总距离，使像素电极1与数据线2之间的电容耦合效应最小。
进一步地，沟槽5的深度等于栅极保护层4的厚度；这样设置使沟槽5的深度达到最大，从而可以通过增大沟槽5的深度，来使像素电极1的端部与数据线2之间的总距离相应增大，从而进一步减小像素电极1与数据线2之间的电容耦合效应。
请参看图5和图6，图5为本发明像素结构的第二种实施方式的示意图，图6为图5所示像素结构沿C-C’的剖视图。与上述第一种实施方式相比，本实施方式中的像素结构同样包括多个像素和数据线，并且每个像素包括像素电极1和具有栅极、有源层、源极和漏极的薄膜晶体管，栅极和有源层之间设置有栅极保护层4，且栅极保护层4上设置有沟槽5，由于在上述第一种实施方式中已有了详细描述，本实施方式中与上述第一种实施方式的相同之处不在赘述。
下面仅就本发明像素结构的第二种实施方式与上述第一种实施方式的不同之处进行详细描述。在本实施方式中，沟槽5设置在与数据线2对应的区域，数据线2设置在沟槽5内，像素电极1则设置在栅极保护层4无沟槽5处的表面上。具体地，沟槽5设置栅极保护层4上用于设置数据线2的区域，以使数据线2可以设置在沟槽5内；这样在像素电极1的端部与数据线2之间在垂直于沟槽5深度方向上的距离(即现有技术中数据线2与像素电极1之间的距离)不变的情况下，增大数据线2与像素电极1的端部之间的总距离，从而与现有技术相比，本实施方式增大了数据线2和像素电极1的端部之间的距离，从而可以减小数据线2和像素电极1之间的电容耦合效应，减少对数据线2及其他信号线中信号传输的干扰。此外，像素电极1与数据线2之间的距离的增大，还可以在制备像素结构的过程中，降低工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能及其均一性，从而可以保证显示装置的显示效果。
优选地，在本实施方式中，数据线2设置在沟槽5的底部，这样设置可以最大程度地增大数据线2与像素电极1之间的距离，从而可以最大程度地减小数据线2与像素电极1之间的电容耦合效应。
在本实施方式中，沟槽5的最大深度小于栅极保护层4的厚度，这样可以避免设置在沟槽5底部的数据线2与制备在栅极保护层4下方的栅极线之间产生接触，进而影响数据线2和栅极线中信号的传输。
综上所述，本发明提供的像素结构，其通过在栅极保护层4上设置沟槽5，并将像素电极1的端部，或者将数据线2设置在沟槽5内，使像素电极1的端部与数据线2不在同一垂直于沟槽的深度方向的平面内，这样在不改变二者在垂直于沟槽5深度方向上的距离的情况下，增大像素电极1的端部和数据线2之间的总距离，从而可以减小像素电极1与数据线2之间的电容耦合效应，从而可以减小对数据线2以及其他信号线中信号传输的干扰。此外，通过增大像素电极1与数据线2之间的总距离，还可以在制备像素结构的过程中，降低工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能及其均一性，从而可以保证显示装置的显示效果。
作为另一个技术方案，本发明还提供一种像素结构的制备方法，请参看图7，图7为本发明提供的像素结构的制备方法的优选实施方式的流程图。在本实施方式中，像素结构的制备方法包括：
S1，制备栅极的步骤。具体地，在该步骤中，通过光刻工艺，即依次进行沉积、涂胶、曝光、刻蚀等在基底上制备出栅极。所述栅极的材料一般为铝(Al)或铜(Cu)。
S2，制备栅极保护层的步骤。具体地，在该步骤中，通过与上述制备栅极类似的光刻工艺在制备有栅极的基底上制备栅极保护层。所述栅极保护层的材料一般为二氧化硅或氮化硅。
S3，在栅极保护层上制备至少部分位于两相邻列像素之间的沟槽的步骤。在该步骤中，通过光刻及干法刻蚀工艺在栅极保护层上制备出沟槽。
具体地，在步骤S3中，制备出的沟槽在栅极保护层上的位置可以为与数据线对应的区域，在此情况下，在制备沟槽的步骤S3完成后，进行下述步骤S41：在所述沟槽内制备所述数据线。
此外，在步骤S3中，还可以在数据线的两侧分别制备沟槽，在此情况下，在制备沟槽的步骤S3完成后，进行下述步骤S42：在包括所述沟槽，且以所述沟槽为边缘的区域内制备像素电极。
此外，上述制备方法还包括制备有源层、源极、漏极等多个步骤，其制备方法与现有技术中用于制备有源层、源极、漏极的方法类似，在此不再赘述。
根据上述方法制备的像素结构，其数据线与像素电极的端部不在同一垂直于沟槽深度方向的平面内，使数据线与像素电极之间在垂直于沟槽深度方向上的距离不变的情况下，可以增大数据线与像素电极的端部之间的距离，从而可以降低数据线及像素电极之间的耦合电容，减小对数据线以及其他信号线中信号传输的干扰。此外，像素电极与数据线之间较大的距离，还可以在制备像素结构的过程中，降低工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能及其均一性。
作为另一个技术方案，本发明还提供一种显示面板，其包括本发明提供的上述像素结构。
本发明提供的显示面板，其包括本发明提供的上述像素结构，可以降低数据线和像素电极之间的电容耦合效应，从而减小对数据线以及其他信号线中信号传输的干扰；还可以减小像素结构制备过程中的工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能以及均匀性，进而可以保证显示面板的显示效果。
作为另一个技术方案，本发明还提供一种显示装置，其包括本发明提供的上述显示面板。
本发明提供的显示装置，其包括本发明提供的上述显示面板，可以降低数据线和像素电极之间的电容耦合效应，从而减小对数据线以及其他信号线中信号传输的干扰；还可以减小像素结构制备过程中的工艺波动对像素内各单元的形状的影响，从而可以保证各像素的性能以及均匀性，进而可以保证显示面板的显示效果。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (11)

1.一种像素结构，包括多列像素以及多条位于相邻列像素间的数据线，每个像素包括像素电极以及具有栅极、有源层、源极和漏极的薄膜晶体管，所述栅极与有源层间设有栅极保护层，其特征在于，
所述栅极保护层中设有至少部分位于两相邻列像素之间的沟槽；
两相邻列像素的像素电极的相对端部，以及两相邻列像素之间的数据线中，一个位于所述沟槽内，另一个位于所述栅极保护层无沟槽处的表面上。
2.根据权利要求1所述的像素结构，其特征在于，所述沟槽设置在与数据线对应的区域，所述数据线设置在所述沟槽内。
3.根据权利要求2所述的像素结构，其特征在于，所述沟槽的最大深度小于所述栅极保护层的厚度。
4.根据权利要求1所述的像素结构，其特征在于，所述沟槽位于数据线两侧，且所述两相邻列像素的像素电极的相对端部位于在所述沟槽内。
5.根据权利要求4所述的像素结构，其特征在于，所述像素电极的靠近所述数据线的端部设置在所述沟槽的底部。
6.根据权利要求4或5所述的像素结构，其特征在于，所述沟槽的深度等于所述栅极保护层的厚度。
7.一种像素结构的制备方法，其特征在于，包括：
制备栅极的步骤；
制备栅极保护层的步骤；
在栅极保护层上制备至少部分位于两相邻列像素之间的沟槽的步骤。
8.根据权利要求7所述的像素结构的制备方法，其特征在于，所述沟槽设置在与数据线对应的区域，
所述像素结构的制备方法还包括：
在所述沟槽内制备数据线的步骤。
9.根据权利要求7所述的像素结构的制备方法，其特征在于，所述沟槽分别设置在数据线的两侧；
所述像素结构的制备方法还包括：
在包括所述沟槽，且以所述沟槽为边缘的区域内制备像素电极的步骤。
10.一种显示面板，其特征在于，包括权利要求1～6任意一项所述的像素结构。
11.一种显示装置，其特征在于，包括权利要求10所述的显示面板。
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