CN104283574A - Software radio receiver circuit - Google Patents
Software radio receiver circuit Download PDFInfo
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- CN104283574A CN104283574A CN201310289188.1A CN201310289188A CN104283574A CN 104283574 A CN104283574 A CN 104283574A CN 201310289188 A CN201310289188 A CN 201310289188A CN 104283574 A CN104283574 A CN 104283574A
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Abstract
The invention provides a software radio receiver circuit. The software radio receiver circuit comprises a low-noise radio-frequency front end circuit, a high-linearity radio frequency front end circuit, a harmonic attenuation radio frequency front end circuit, a common analog intermediate-frequency circuit, a local oscillator signal generation circuit, a biasing circuit and a control circuit. One end of the low-noise radio-frequency front end circuit is connected with the first end of the common analog intermediate-frequency circuit after the low-noise radio-frequency front end circuit is connected with the high-linearity radio frequency front end circuit in parallel. One end of the harmonic attenuation radio frequency front end circuit is connected with the first end of the common analog intermediate-frequency circuit .The local oscillator signal generation circuit is connected with the low-noise radio-frequency front end circuit, the high-linearity radio frequency front end circuit and the harmonic attenuation radio frequency front end circuit. The biasing circuit is used for providing a reference bias voltage and a reference bias current for the software radio receiver circuit. The control circuit is used for controlling work modes of the software radio receiver circuit. The software radio receiver circuit can meet the requirements of various application environments.
Description
Technical field
The present invention relates to software wireless electrical domain, particularly relate to a kind of software radio receiver circuit.
Background technology
In information age today, people are using the transmission of information with alternately as the necessary component of social life.Wherein, radio communication is a part the most active in the communications field, is obtained in all fields and applies widely.In order to meet the different demands of consumer, international telecommunication unit has released one after another different communication standards.In the face of miscellaneous standard, consumer more wishes just can support different communication services by means of only an electronic equipment.
Software radio (SDR) technology is the wireless communication system architecture proposed in recent years, the earliest by military communication technical development, its basic thought carrys out configure hardware by software, and realize restructural characteristic flexibly, one of key technical problems is wherein exactly receiver circuit.
The effect of software radio receiver is configured the form of the mode of operation of radio-frequency transmitter by software, meet existing and be about to occur distinct communication standards requirement.These communication standards mainly comprise cellular communications system (2G-2.5G-3G etc.), wireless lan communication system (802.11a/b/g/n etc.), wireless personal local area network communication system (Bluetooth, Zigbee etc.), broadcast communication system (DAB, DVB, DMB etc.) and navigation communication system (GPS, Galileo, GLONASS, the Big Dipper) etc.Obviously, each communication standard has centre frequencies different separately, channel width, noise objective, linearity index etc.Therefore software radio receiver must have the configurability of great dynamic range simultaneously, meets the performance index requirement of distinct communication standards again.
In addition, software radio receiver not only has restructural feature flexibly, and it also has very large potentiality in low-power consumption application.The most rigors of traditional wireless communication receiver demand fulfillment communication system when designing, therefore will inevitably pay the cost of power consumption.The index such as the linearity, filtering performance, noiseproof feature, bandwidth sum gain of such as receiver circuit all also exists trade-off relation with power consumption.And software radio receiver can be different according to it applied environment, configure its performance index neatly, under the requirement meeting practical communication index, reduce the average power consumption of overall receiver.
Because the applied environment of distinct communication standards is different, the signal quality received by software radio receiver is also not quite similar.In order to meet the application requirement of distinct communication standards, software radio receiver also must have flexible configurable feature, meets the requirement for specific indexes under different application environment, such as: low noise feature, high linearity feature, has harmonics restraint feature and low-power consumption feature etc.
Domestic at present only have a few patents achievement to occur: include radio-frequency (RF) front-end circuit and base band control system based on the upgradeable OFDM transceiver of software radio (Chinese patent CN1964339A), but only can support the communication standard of OFDM, although possessed the restructural feature of software radio, do not possess the ability of compatible distinct communication standards; The method (Chinese patent CN1175609C) of multiple carrier software radio transceiver and raising intelligent antenna performance thereof proposes the calibration steps of many standard transceivers radio-frequency front-end and baseband circuit and smart antenna, GSM can be supported, several mobile communication standard of CDMA and WCDMA, do not support other communication service type, lack i/q signal, DC maladjustment, the calibration function of IIP2; The device and the receiver circuit (Chinese patent CN101072058A) that improve noise immunity of receiver propose a kind of method improving noise immunity of receiver, radio frequency part gain is regulated by the method for power detection, but solve only the problem of noise immunity of receiver, be still not suitable for the application demand of software radio receiver.
The present Research summing up domestic software radio receiver can find, break through although achieved some at present, receiver circuit is still the bottleneck of soft radio applications.Occurred the configurable receiver circuit of some many standards at present, but it is configurable only can to realize part, supports part communication standard, lack necessary calibration function simultaneously.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is: provide a kind of software radio receiver circuit, can meet the needs of multiple applied environment.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of software radio receiver circuit, comprise low noise radio-frequency (RF) front-end circuit, High Linear radio-frequency (RF) front-end circuit, harmonics restraint radio-frequency (RF) front-end circuit, public analog intermediate frequency circuit, local oscillation signal generation circuit, biasing circuit and control circuit;
Described low noise radio-frequency (RF) front-end circuit is connected with the first end of the one end after the parallel connection of described High Linear radio-frequency (RF) front-end circuit with described public analog intermediate frequency circuit;
One end of described harmonics restraint radio-frequency (RF) front-end circuit is connected with the first end of described public analog intermediate frequency circuit;
Described local oscillation signal produces circuit and is connected with described low noise radio-frequency (RF) front-end circuit, described High Linear radio-frequency (RF) front-end circuit and described harmonics restraint radio-frequency (RF) front-end circuit respectively;
Described biasing circuit is used for providing reference offset voltage and reference bias current to described software radio receiver circuit;
Described control circuit is for controlling the mode of operation of described software radio receiver circuit.
Further, described low noise radio-frequency (RF) front-end circuit comprises the first low noise amplifier 201, first trsanscondutance amplifier 202, first passive current mode mixer 203 and the first second nonlinear calibration circuit 204;
Described first low noise amplifier 201 carries out amplification process for the radio frequency voltage signal described low noise radio-frequency (RF) front-end circuit received;
Described first trsanscondutance amplifier 202 is connected with described first low noise amplifier 201, is converted to current signal with the voltage signal for being exported by described first low noise amplifier 201;
Described first passive current mode mixer 203 is connected with described first trsanscondutance amplifier 202, down-converts to current intermediate frequency signal for the current radio frequency signal exported by trsanscondutance amplifier 202;
Described first second nonlinear calibration circuit 204 is connected with described first passive current mode mixer 203, for improving the second nonlinear performance of described low noise radio-frequency (RF) front-end circuit.
Further, described High Linear radio-frequency (RF) front-end circuit comprises passive electrical die mould frequency mixer 101, second trsanscondutance amplifier 102 and the second second nonlinear calibration circuit 103;
Described passive electrical die mould frequency mixer 101 carries out down-converted for the radio frequency voltage signal described High Linear radio-frequency (RF) front-end circuit received;
Described second trsanscondutance amplifier 102 is connected with described passive electrical die mould frequency mixer 101, for the voltage intermediate frequency signal that passive electrical die mould frequency mixer 101 exports being converted to current intermediate frequency signal by described;
Described second second nonlinear calibration circuit 103 is connected with described passive electrical die mould frequency mixer 101, for improving the second nonlinear performance of described high-linearity radio-frequency front end circuit.
Further, described harmonics restraint radio-frequency (RF) front-end circuit comprises the second low noise amplifier 301, the 3rd trsanscondutance amplifier 302, second passive current mode mixer 303 and harmonics restraint calibration circuit 304.
Described second low noise amplifier 301 carries out amplification process for the radio frequency voltage signal described harmonics restraint radio-frequency (RF) front-end circuit received;
Described 3rd trsanscondutance amplifier 302 is connected with described second low noise amplifier 301, is converted to current signal for the voltage signal exported by described second low noise amplifier 301;
Described second passive current mode mixer 303 is connected with described 3rd trsanscondutance amplifier 302, down-converts to current intermediate frequency signal for the current radio frequency signal exported by described 3rd trsanscondutance amplifier 302;
Described harmonic suppression circuit 304 is connected with described 3rd trsanscondutance amplifier 302, for improving the harmonic inhibition capability of described harmonics restraint radio-frequency (RF) front-end circuit.
Further, described 3rd trsanscondutance amplifier 302 comprises 3 parallel trsanscondutance amplifiers, and wherein, the proportionate relationship of the gain of described 3 parallel trsanscondutance amplifiers is:
Further, described second passive current mode mixer 303 comprises 3 parallel passive current mode mixer, and described 3 parallel passive current mode mixer local oscillation signal phase places are respectively 0 °, 45 °, 90 °.
Further, described public analog intermediate frequency circuit comprises trans-impedance amplifier 401, i/q signal calibration circuit 402, 3 rank low passes/logical configurable filter 403 of multiple band, receiver low pass/logical diverter switch 405 of multiple band, programmable gain amplifier 501, i/q signal calibration circuit 502, analog to digital converter 503, automatic gain calibration circuit 505, power-sensing circuit 506, the bandwidth calibration circuit 404 of described trans-impedance amplifier 401, the bandwidth calibration circuit 406 of described 3 rank low passes/logical configurable filter 403 of multiple band, the DC maladjustment alignment loop 504 of described programmable gain amplifier 501, wherein, described trans-impedance amplifier 401, described i/q signal calibration circuit 402, described 3 rank low passes/logical configurable filter 403 of multiple band, described programmable gain amplifier 501, described i/q signal calibration circuit 502, described analog to digital converter 503 is cascaded, described receiver low pass/logical diverter switch 405 of multiple band is in parallel with described i/q signal calibration circuit 402, one end of described automatic gain calibration circuit 505 is connected with one end of described power-sensing circuit 506, the other end of described power-sensing circuit 506 connects the common node of i/q signal calibration circuit 502 and analog to digital converter 503, and the other end of described automatic gain calibration circuit 505 connects described programmable gain amplifier 501.
Further, the input of described trans-impedance amplifier 401 is the public output of the second passive current mode mixer 203 of trsanscondutance amplifier 102, first and the second passive current mode mixer 303, described trans-impedance amplifier 401 has second order Butterworth low pass wave property, and the transimpedance gain of described trans-impedance amplifier 401 is adjustable.
Further, described local oscillation signal generation circuit comprises integer/fractional frequency synthesizer 601, first local oscillator generator 602, second local oscillator generator 603 and the 3rd local oscillator generator 604;
One end of described first local oscillator generator 602 is connected with one end of described integer/fractional frequency synthesizer 601, the other end is connected with described passive electrical die mould frequency mixer 101, and the 50% duty ratio 4 phase differential quadrature signals for being exported by described integer/fractional frequency synthesizer 601 is converted to 4 phase differential quadrature signals of 25% duty ratio;
One end of described second local oscillator generator 603 is connected with one end of described integer/fractional frequency synthesizer 601, the other end is connected with the first passive current mode mixer 203, and the 50% duty ratio 4 phase differential quadrature signals for being exported by described integer/fractional frequency synthesizer 601 is converted to 4 phase differential quadrature signals of 25% duty ratio;
One end of described 3rd local oscillator generator 604 is connected with one end of described integer/fractional frequency synthesizer 601, the other end is connected with described second passive current mode mixer 303, and the 50% duty ratio 4 phase differential quadrature signals for being exported by described integer/fractional frequency synthesizer 601 is converted to 8 phase signals of 25% duty ratio.
Further, described control circuit comprises CLK, SCS, SDI and SDO tetra-ports, and described control circuit is connected with peripheral control unit.
(3) beneficial effect
Software radio receiver circuit provided by the invention, the mode of operation of low noise radio-frequency (RF) front-end circuit, High Linear radio-frequency (RF) front-end circuit and harmonics restraint radio-frequency (RF) front-end circuit is controlled by control circuit, thus realize low noise applications, high linearity application, simultaneously take into account low noise and high linearity application, harmonics restraint application, make this software radio receiver circuit have restructural feature flexibly, the needs of multiple different application environment can be met.
Accompanying drawing explanation
The structure chart of a kind of software radio receiver circuit that Fig. 1 provides for embodiment of the present invention;
The structure chart of the another kind of software radio receiver circuit that Fig. 2 provides for embodiment of the present invention;
Fig. 3 is the schematic diagram that software radio receiver circuit that embodiment of the present invention provides works under low noise applications environment;
Fig. 4 is the schematic diagram that software radio receiver circuit that embodiment of the present invention provides works under high linearity applied environment;
Fig. 5 is the schematic diagram worked under software radio receiver circuit that embodiment of the present invention provides takes into account low noise and high linearity applied environment at the same time;
Fig. 6 is the schematic diagram that software radio receiver circuit that embodiment of the present invention provides works under harmonics restraint applied environment.
Embodiment
Fig. 1 is the structure chart of a kind of software radio receiver circuit that embodiment of the present invention provides, and comprises low noise radio-frequency (RF) front-end circuit 1, High Linear radio-frequency (RF) front-end circuit 2, harmonics restraint radio-frequency (RF) front-end circuit 3, public analog intermediate frequency circuit 4, local oscillation signal generation circuit 5, biasing circuit and control circuit;
Described low noise radio-frequency (RF) front-end circuit 1 is connected with the first end of the one end after the parallel connection of described High Linear radio-frequency (RF) front-end circuit 2 with described public analog intermediate frequency circuit 4;
One end of described harmonics restraint radio-frequency (RF) front-end circuit 3 is connected with the first end of described public analog intermediate frequency circuit 4;
Described local oscillation signal produces circuit 5 and is connected with described low noise radio-frequency (RF) front-end circuit 1, described High Linear radio-frequency (RF) front-end circuit 2 and described harmonics restraint radio-frequency (RF) front-end circuit 3 respectively;
Described biasing circuit is used for providing reference offset voltage and reference bias current to described software radio receiver circuit;
Described control circuit is for controlling the mode of operation of described software radio receiver circuit.
The software radio receiver circuit that present embodiment provides, the mode of operation of low noise radio-frequency (RF) front-end circuit, High Linear radio-frequency (RF) front-end circuit and harmonics restraint radio-frequency (RF) front-end circuit is controlled by control circuit, thus realize low noise applications, high linearity application, simultaneously take into account low noise and high linearity application, harmonics restraint application, make this software radio receiver circuit have restructural feature flexibly, the needs of multiple different application environment can be met.
See Fig. 2, Fig. 2 is the structure chart of the another kind of software radio receiver circuit that embodiment of the present invention provides, wherein, described low noise radio-frequency (RF) front-end circuit comprises the first low noise amplifier 201, first trsanscondutance amplifier 202, first passive current mode mixer 203 and the first second nonlinear calibration circuit 204;
Described first low noise amplifier 201 carries out amplification process for the radio frequency voltage signal described low noise radio-frequency (RF) front-end circuit received;
Described first trsanscondutance amplifier 202 is connected with described first low noise amplifier 201, is converted to current signal with the voltage signal for being exported by described first low noise amplifier 201;
Described first passive current mode mixer 203 is connected with described first trsanscondutance amplifier 202, down-converts to current intermediate frequency signal for the current radio frequency signal exported by trsanscondutance amplifier 202;
Described first second nonlinear calibration circuit 204 is connected with described first passive current mode mixer 203, for improving the second nonlinear performance of described low noise radio-frequency (RF) front-end circuit.
Preferably, see Fig. 2, described High Linear radio-frequency (RF) front-end circuit comprises passive electrical die mould frequency mixer 101, second trsanscondutance amplifier 102 and the second second nonlinear calibration circuit 103;
Described passive electrical die mould frequency mixer 101 carries out down-converted for the radio frequency voltage signal described High Linear radio-frequency (RF) front-end circuit received;
Described second trsanscondutance amplifier 102 is connected with described passive electrical die mould frequency mixer 101, for the voltage intermediate frequency signal that passive electrical die mould frequency mixer 101 exports being converted to current intermediate frequency signal by described;
Described second second nonlinear calibration circuit 103 is connected with described passive electrical die mould frequency mixer 101, for improving the second nonlinear performance of described high-linearity radio-frequency front end circuit.
Preferably, see Fig. 2, described harmonics restraint radio-frequency (RF) front-end circuit comprises the second low noise amplifier 301, the 3rd trsanscondutance amplifier 302, second passive current mode mixer 303 and harmonics restraint calibration circuit 304.
Described second low noise amplifier 301 carries out amplification process for the radio frequency voltage signal described harmonics restraint radio-frequency (RF) front-end circuit received;
Described 3rd trsanscondutance amplifier 302 is connected with described second low noise amplifier 301, is converted to current signal for the voltage signal exported by described second low noise amplifier 301;
Described second passive current mode mixer 303 is connected with described 3rd trsanscondutance amplifier 302, down-converts to current intermediate frequency signal for the current radio frequency signal exported by described 3rd trsanscondutance amplifier 302;
Described harmonic suppression circuit 304 is connected with described 3rd trsanscondutance amplifier 302, for improving the harmonic inhibition capability of described harmonics restraint radio-frequency (RF) front-end circuit.
Preferably, described 3rd trsanscondutance amplifier 302 comprises 3 parallel trsanscondutance amplifiers, and wherein, the proportionate relationship of the gain of described 3 parallel trsanscondutance amplifiers is:
Preferably, described second passive current mode mixer 303 comprises 3 parallel passive current mode mixer, and described 3 parallel passive current mode mixer local oscillation signal phase places are respectively 0 °, 45 °, 90 °.
Preferably, described public analog intermediate frequency circuit comprises trans-impedance amplifier 401, i/q signal calibration circuit 402, 3 rank low passes/logical configurable filter 403 of multiple band, receiver low pass/logical diverter switch 405 of multiple band, programmable gain amplifier 501, i/q signal calibration circuit 502, analog to digital converter 503, automatic gain calibration circuit 505, power-sensing circuit 506, the bandwidth calibration circuit 404 of described trans-impedance amplifier 401, the bandwidth calibration circuit 406 of described 3 rank low passes/logical configurable filter 403 of multiple band, the DC maladjustment alignment loop 504 of described programmable gain amplifier 501, wherein, described trans-impedance amplifier 401, described i/q signal calibration circuit 402, described 3 rank low passes/logical configurable filter 403 of multiple band, described programmable gain amplifier 501, described i/q signal calibration circuit 502, described analog to digital converter 503 is cascaded, described receiver low pass/logical diverter switch 405 of multiple band is in parallel with described i/q signal calibration circuit 402, one end of described automatic gain calibration circuit 505 is connected with one end of described power-sensing circuit 506, the other end of described power-sensing circuit 506 connects the common node of i/q signal calibration circuit 502 and analog to digital converter 503, and the other end of described automatic gain calibration circuit 505 connects described programmable gain amplifier 501.Wherein, the testing result of analog to digital converter 503 input signal power is sent into automatic gain calibration circuit 505 by power-sensing circuit 506, the gain shift of the calibrating signal adjustment programmable gain amplifier 501 that automatic gain calibration circuit 505 exports.
Preferably, the input of described trans-impedance amplifier 401 is the public output of the second passive current mode mixer 203 of trsanscondutance amplifier 102, first and the second passive current mode mixer 303, described trans-impedance amplifier 401 has second order Butterworth low pass wave property, and the transimpedance gain of described trans-impedance amplifier 401 is adjustable.
Wherein, zero intermediate frequency and low intermediate frequency receiver is realized respectively by configuring 3 rank low passes/multiple logical configurable filter 403 and receiver low pass/logical diverter switch 405 of multiple band be with, when receiver is configured to zero-IF operation pattern, the logical diverter switch 405 of receiver low pass/multiple band closes, i/q signal calibration circuit 402 turns off, and 3 rank low passes/logical configurable filter 403 of multiple band is configured to low pass filter pattern; When receiver is configured to Low Medium Frequency mode of operation, receiver low pass/logical diverter switch 405 of multiple band is cut off, and i/q signal calibration circuit 402 is opened, and 3 rank low passes/logical configurable filter 403 of multiple band is configured to multiple band pass filter pattern.The software radio receiver circuit that embodiment of the present invention provides receives application model for zero intermediate frequency, possesses reception 1GHz ~ 5GHz, and signal bandwidth covers the ability of 0.7MHz ~ 20MHz radiofrequency signal; For low intermediate frequency receiver application model, possess reception 100MHz ~ 1.5GHz, signal bandwidth covers the ability of 5KHz ~ 2MHz radiofrequency signal, can meet the requirement of current most of arrowband and broadband main flow communication standard.
Preferably, described local oscillation signal generation circuit comprises integer/fractional frequency synthesizer 601, first local oscillator generator 602, second local oscillator generator 603 and the 3rd local oscillator generator 604;
One end of described first local oscillator generator 602 is connected with one end of described integer/fractional frequency synthesizer 601, the other end is connected with described passive electrical die mould frequency mixer 101, and the 50% duty ratio 4 phase differential quadrature signals for being exported by described integer/fractional frequency synthesizer 601 is converted to 4 phase differential quadrature signals of 25% duty ratio; Phase alignment module improves the orthogonal performance of output signal;
One end of described second local oscillator generator 603 is connected with one end of described integer/fractional frequency synthesizer 601, the other end is connected with the first passive current mode mixer 203, and the 50% duty ratio 4 phase differential quadrature signals for being exported by described integer/fractional frequency synthesizer 601 is converted to 4 phase differential quadrature signals of 25% duty ratio; Phase alignment module improves the orthogonal performance of output signal;
One end of described 3rd local oscillator generator 604 is connected with one end of described integer/fractional frequency synthesizer 601, the other end is connected with described second passive current mode mixer 303, and the 50% duty ratio 4 phase differential quadrature signals for being exported by described integer/fractional frequency synthesizer 601 is converted to 8 phase signals of 25% duty ratio; Difference is 45 °, and phase alignment module improves the orthogonal performance of output signal.
Preferably, described control circuit comprises CLK, SCS, SDI and SDO tetra-ports, and described control circuit is connected with peripheral control unit, can communicate with peripheral control unit, the mode of operation of the inner each modular circuit of control chip.
The software radio receiver circuit that present embodiment provides can meet the multiple needs without applied environment, comprising: low noise applications, high linearity are applied, take into account low noise and high linearity application and harmonics restraint simultaneously applies.
See Fig. 3, when operation of receiver is in low noise applications pattern, low noise radio-frequency (RF) front-end circuit, public analog intermediate frequency circuit, local oscillation signal produce circuit, biasing circuit and control circuit work.The radiofrequency signal of receiver inlet is amplified by the first low noise amplifier 201, and the voltage signal of output is sent into the first trsanscondutance amplifier 202 and is converted to current signal, then sends into the first passive current mode mixer 203 and carry out down-conversion.Because the receiver first order adopts the first low noise amplifier 201, its noiseproof feature is improved.In order to improve the second nonlinear performance of receiver, first second nonlinear calibration circuit 204 realizes calibration function by the grid voltage of the passive current mode mixer 203 of adjustment first, the current intermediate frequency signal that first passive current mode mixer 203 exports is converted to voltage signal by the trans-impedance amplifier 401 with second order Butterworth filtering characteristic, and realizes certain filter action.
The logical diverter switch 405 of receiver low pass/multiple band closes, i/q signal calibration circuit 402 turns off, 3 rank low passes/logical configurable filter 403 of multiple band is configured to low pass filter pattern, and programmable gain amplifier 501 sends into analog to digital converter 503 after being amplified further by signal again after i/q signal calibration circuit 502.The 50% duty ratio 4 phase differential quadrature signals that integer/fractional frequency synthesizer 601 exports by the second local oscillator generator 603 sends into the first passive current mode mixer 203 after being converted to 4 phase differential quadrature signals of 25% duty ratio, and phase alignment module improves the orthogonal performance of output signal.
The bandwidth calibration circuit 406 of the bandwidth calibration circuit 404 and 3 rank low pass/logical configurable filter 403 of multiple band of trans-impedance amplifier 401 realizes the automatic adjustment of bandwidth, DC maladjustment alignment loop 504 calibrates the output DC offset voltage of programmable gain amplifier 501, the testing result of analog to digital converter 503 input signal power is sent into automatic gain calibration circuit 505 by power-sensing circuit 506, the gain shift of the calibrating signal adjustment programmable gain amplifier 501 that automatic gain calibration circuit 505 exports, the output signal of programmable gain amplifier 501 carries out calibrating rear feeding analog to digital converter 503 by i/q signal calibration circuit 502.
See Fig. 4, when operation of receiver is in high linearity application model, High Linear radio-frequency (RF) front-end circuit, the first low noise amplifier 201, public analog intermediate frequency circuit, local oscillation signal produce circuit, biasing circuit and control circuit work.The radiofrequency signal of receiver inlet is carried out down-converted by passive electrical die mould frequency mixer 101, the signal exported is converted to current signal through the second trsanscondutance amplifier 102, in order to realize receiver inlet coupling, first low noise amplifier 201 works in low-power consumption mode, provides the Input matching required for receiver.Passive electrical die mould frequency mixer has the characteristic that impedance is moved, and the impedance operator of intermediate frequency can be moved radio frequency domains, and therefore the input impedance of passive electrical die mould frequency mixer 101 input has the characteristic of radio-frequency filter, can the outer high reject signal of filter out-band.Compare low noise amplifier, passive electrical die mould frequency mixer has the higher linearity, and therefore the linearity performance of receiver is promoted.
The current intermediate frequency signal that second trsanscondutance amplifier 102 exports is converted to voltage signal by the trans-impedance amplifier 401 with second order Butterworth filtering characteristic, and realizes certain filter action.The logical diverter switch 405 of receiver low pass/multiple band closes, i/q signal calibration circuit 402 turns off, 3 rank low passes/logical configurable filter 403 of multiple band is configured to low pass filter pattern, and programmable gain amplifier 501 sends into analog to digital converter 503 after being amplified further by signal again after I/Q calibration circuit 502.
Send into passive electrical die mould frequency mixer 101 after the 50% duty ratio 4 phase differential quadrature signals that integer/fractional frequency synthesizer 601 exports by the first local oscillator generator 602 is converted to 4 phase differential quadrature signals of 25% duty ratio, phase alignment module improves the orthogonal performance of output signal.
The bandwidth calibration circuit 406 of the bandwidth calibration circuit 404 and 3 rank low pass/logical configurable filter 403 of multiple band of trans-impedance amplifier 401 realizes the automatic adjustment of bandwidth, DC maladjustment alignment loop 504 calibrates the output DC offset voltage of programmable gain amplifier 501, the testing result of analog to digital converter 503 input signal power is sent into automatic gain calibration circuit 505 by power-sensing circuit 506, the gain shift of the calibrating signal adjustment programmable gain amplifier 501 that automatic gain calibration circuit 505 exports, the output signal of programmable gain amplifier 501 carries out calibrating rear feeding analog to digital converter 503 by i/q signal calibration circuit 502.
See Fig. 5, when operation of receiver is in time taking into account low noise and high linearity application model, low noise radio-frequency (RF) front-end circuit, passive electrical die mould frequency mixer 101, public analog intermediate frequency circuit, local oscillation signal produce circuit, biasing circuit and control circuit work.Compare the low noise applications shown in Fig. 3, unique difference is, passive electrical die mould frequency mixer 101 works simultaneously, input due to passive electrical die mould frequency mixer has the characteristic of radio frequency band filter, therefore use in parallel with passive electrical die mould frequency mixer 101 for the first low noise amplifier 201, improve the energy of the outer high reject signal of receiver inlet filter out-band, the linearity of receiver is improved.The first order due to signalling channel is still the first low noise amplifier 201, and the noiseproof feature of receiver is also improved.
See Fig. 6, when operation of receiver is in harmonics restraint application model, harmonics restraint radio-frequency (RF) front-end circuit, public analog intermediate frequency circuit, local oscillation signal produce circuit, biasing circuit and control circuit work.The radiofrequency signal of receiver inlet is amplified by the second low noise amplifier 301, and the voltage signal of output is sent into the 3rd trsanscondutance amplifier 302 and is converted to current signal, then sends into the second passive current mode mixer 303 and carry out down-conversion.Receiver have employed harmonics restraint structure, and the ratio of gains of three parallel subelements of the 3rd trsanscondutance amplifier 302 is
the local oscillation signal phase place of three parallel subelements of the second passive current mode mixer 303 is 0 °, 45 °, 90 °, therefore receiver for 3 rank and 5 order harmonic signal inhibited, simultaneously owing to have employed differential configuration, even-order harmonics signal is inhibited too.
The current intermediate frequency signal that second passive current mode mixer 303 exports is converted to voltage signal by the trans-impedance amplifier 401 with second order Butterworth filtering characteristic, and realizes certain filter action.Receiver low pass/logical diverter switch 405 of multiple band disconnects, i/q signal calibration circuit 402 is opened, 3 rank low passes/logical configurable filter 403 of multiple band is configured to multiple band pass filter pattern, and programmable gain amplifier 501 sends into analog to digital converter 503 after being amplified further by signal again after i/q signal calibration circuit 502.
8 phase signals that the 50% duty ratio 4 phase differential quadrature signals that integer/fractional frequency synthesizer 601 exports by the 3rd local oscillator generator 604 is converted to 25% duty ratio send into the second passive current mode mixer 303, difference is 45 °, the phase deviation of phase alignment modular calibration output signal.
The bandwidth calibration circuit 406 of the bandwidth calibration circuit 404 and 3 rank low pass/logical configurable filter 403 of multiple band of trans-impedance amplifier 401 realizes the automatic adjustment of bandwidth, DC maladjustment alignment loop 504 calibrates the output DC offset voltage of programmable gain amplifier 501, the testing result of analog to digital converter 503 input signal power is sent into automatic gain calibration circuit 505 by power-sensing circuit 506, the gain shift of the calibrating signal adjustment programmable gain amplifier 501 that automatic gain calibration circuit 505 exports, the output signal of programmable gain amplifier 501 carries out calibrating rear feeding analog to digital converter 503 by i/q signal calibration circuit 502.
The software radio receiver circuit that present embodiment provides, when operation of receiver is in low noise applications pattern, low noise radio-frequency (RF) front-end circuit, public analog intermediate frequency circuit, local oscillation signal produce circuit, biasing circuit and control circuit work; When operation of receiver is in high linearity application model, High Linear radio-frequency (RF) front-end circuit, the first low noise amplifier 201, public analog intermediate frequency circuit, local oscillation signal produce circuit, biasing circuit and control circuit work; When operation of receiver is in time taking into account low noise and high linearity application model, low noise radio-frequency (RF) front-end circuit, passive electrical die mould frequency mixer 101, public analog intermediate frequency circuit, local oscillation signal produce circuit, biasing circuit and control circuit work; When operation of receiver is in harmonics restraint application model, harmonics restraint radio-frequency (RF) front-end circuit, public analog intermediate frequency circuit, local oscillation signal produce circuit and biased and control circuit work.Thus realize low noise applications, high linearity application, simultaneously take into account low noise and high linearity application, harmonics restraint application, this software radio receiver circuit is made to have restructural feature flexibly, the needs of multiple different application environment can be met, be applicable to most of main flow communication standard.
Claims (10)
1. a software radio receiver circuit, it is characterized in that, comprise low noise radio-frequency (RF) front-end circuit, High Linear radio-frequency (RF) front-end circuit, harmonics restraint radio-frequency (RF) front-end circuit, public analog intermediate frequency circuit, local oscillation signal generation circuit, biasing circuit and control circuit;
Described low noise radio-frequency (RF) front-end circuit is connected with the first end of the one end after the parallel connection of described High Linear radio-frequency (RF) front-end circuit with described public analog intermediate frequency circuit;
One end of described harmonics restraint radio-frequency (RF) front-end circuit is connected with the first end of described public analog intermediate frequency circuit;
Described local oscillation signal produces circuit and is connected with described low noise radio-frequency (RF) front-end circuit, described High Linear radio-frequency (RF) front-end circuit and described harmonics restraint radio-frequency (RF) front-end circuit respectively;
Described biasing circuit is used for providing reference offset voltage and reference bias current to described software radio receiver circuit;
Described control circuit is for controlling the mode of operation of described software radio receiver circuit.
2. software radio receiver circuit according to claim 1, it is characterized in that, described low noise radio-frequency (RF) front-end circuit comprises the first low noise amplifier (201), the first trsanscondutance amplifier (202), the first passive current mode mixer (203) and the first second nonlinear calibration circuit (204);
Described first low noise amplifier (201) carries out amplification process for the radio frequency voltage signal described low noise radio-frequency (RF) front-end circuit received;
Described first trsanscondutance amplifier (202) is connected with described first low noise amplifier (201), is converted to current signal with the voltage signal for described first low noise amplifier (201) being exported;
Described first passive current mode mixer (203) is connected with described first trsanscondutance amplifier (202), down-converts to current intermediate frequency signal for the current radio frequency signal exported by trsanscondutance amplifier (202);
Described first second nonlinear calibration circuit (204) is connected with described first passive current mode mixer (203), for improving the second nonlinear performance of described low noise radio-frequency (RF) front-end circuit.
3. software radio receiver circuit according to claim 2, is characterized in that, described High Linear radio-frequency (RF) front-end circuit comprises passive electrical die mould frequency mixer (101), the second trsanscondutance amplifier (102) and the second second nonlinear calibration circuit (103);
Described passive electrical die mould frequency mixer (101) carries out down-converted for the radio frequency voltage signal described High Linear radio-frequency (RF) front-end circuit received;
Described second trsanscondutance amplifier (102) is connected with described passive electrical die mould frequency mixer (101), for the voltage intermediate frequency signal that passive electrical die mould frequency mixer (101) exports being converted to current intermediate frequency signal by described;
Described second second nonlinear calibration circuit (103) is connected with described passive electrical die mould frequency mixer (101), for improving the second nonlinear performance of described high-linearity radio-frequency front end circuit.
4. software radio receiver circuit according to claim 3, it is characterized in that, described harmonics restraint radio-frequency (RF) front-end circuit comprises the second low noise amplifier (301), the 3rd trsanscondutance amplifier (302), the second passive current mode mixer (303) and harmonics restraint calibration circuit (304);
Described second low noise amplifier (301) carries out amplification process for the radio frequency voltage signal described harmonics restraint radio-frequency (RF) front-end circuit received;
Described 3rd trsanscondutance amplifier (302) is connected with described second low noise amplifier (301), is converted to current signal for the voltage signal described second low noise amplifier (301) exported;
Described second passive current mode mixer (303) is connected with described 3rd trsanscondutance amplifier (302), down-converts to current intermediate frequency signal for the current radio frequency signal exported by described 3rd trsanscondutance amplifier (302);
Described harmonic suppression circuit (304) is connected with described 3rd trsanscondutance amplifier (302), for improving the harmonic inhibition capability of described harmonics restraint radio-frequency (RF) front-end circuit.
5. software radio receiver circuit according to claim 4, is characterized in that, described 3rd trsanscondutance amplifier (302) comprises 3 parallel trsanscondutance amplifiers, and wherein, the proportionate relationship of the gain of described 3 parallel trsanscondutance amplifiers is:
6. software radio receiver circuit according to claim 4, it is characterized in that, described second passive current mode mixer (303) comprises 3 parallel passive current mode mixer, and described 3 parallel passive current mode mixer local oscillation signal phase places are respectively 0 °, 45 °, 90 °.
7. software radio receiver circuit according to claim 4, is characterized in that, described public analog intermediate frequency circuit comprises trans-impedance amplifier (401), i/q signal calibration circuit (402), 3 rank low passes/logical configurable filter (403) of multiple band, receiver low pass/logical diverter switch (405) of multiple band, programmable gain amplifier (501), i/q signal calibration circuit (502), analog to digital converter (503), automatic gain calibration circuit (505), power-sensing circuit (506), the bandwidth calibration circuit (404) of described trans-impedance amplifier (401), the bandwidth calibration circuit (406) of described 3 rank low passes/logical configurable filter (403) of multiple band, the DC maladjustment alignment loop (504) of described programmable gain amplifier (501), wherein, described trans-impedance amplifier (401), described i/q signal calibration circuit (402), described 3 rank low passes/logical configurable filter (403) of multiple band, described programmable gain amplifier (501), described i/q signal calibration circuit (502), described analog to digital converter (503) is cascaded, described receiver low pass/logical diverter switch (405) of multiple band is in parallel with described i/q signal calibration circuit (402), one end of described automatic gain calibration circuit (505) is connected with one end of described power-sensing circuit (506), the other end of described power-sensing circuit (506) connects the common node of i/q signal calibration circuit (502) and analog to digital converter (503), and the other end of described automatic gain calibration circuit (505) connects described programmable gain amplifier (501).
8. software radio receiver circuit according to claim 7, it is characterized in that, the input of described trans-impedance amplifier (401) is the public output of the second trsanscondutance amplifier (102), the first passive current mode mixer (203) and the second passive current mode mixer (303), described trans-impedance amplifier (401) has second order Butterworth low pass wave property, and the transimpedance gain of described trans-impedance amplifier (401) is adjustable.
9. software radio receiver circuit according to claim 4, it is characterized in that, described local oscillation signal produces circuit and comprises integer/fractional frequency synthesizer (601), the first local oscillator generator (602), the second local oscillator generator (603) and the 3rd local oscillator generator (604);
One end of described first local oscillator generator (602) is connected with one end of described integer/fractional frequency synthesizer (601), the other end is connected with described passive electrical die mould frequency mixer (101), and the 50% duty ratio 4 phase differential quadrature signals for being exported by described integer/fractional frequency synthesizer (601) is converted to 4 phase differential quadrature signals of 25% duty ratio;
One end of described second local oscillator generator (603) is connected with one end of described integer/fractional frequency synthesizer (601), the other end is connected with the first passive current mode mixer (203), and the 50% duty ratio 4 phase differential quadrature signals for being exported by described integer/fractional frequency synthesizer (601) is converted to 4 phase differential quadrature signals of 25% duty ratio;
One end of described 3rd local oscillator generator (604) is connected with one end of described integer/fractional frequency synthesizer (601), the other end is connected with described second passive current mode mixer (303), and the 50% duty ratio 4 phase differential quadrature signals for being exported by described integer/fractional frequency synthesizer (601) is converted to 8 phase signals of 25% duty ratio.
10. software radio receiver circuit according to claim 1, is characterized in that, described control circuit comprises CLK, SCS, SDI and SDO tetra-ports, and described control circuit is connected with peripheral control unit.
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| CN111130577A (en) * | 2019-11-20 | 2020-05-08 | 深圳市纽瑞芯科技有限公司 | Anti-interference receiver circuit for radio frequency transceiver chip |
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