CN111245457A - Zero intermediate frequency receiver compatible with wide and narrow band signals and direct current processing method thereof - Google Patents
Zero intermediate frequency receiver compatible with wide and narrow band signals and direct current processing method thereof Download PDFInfo
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- CN111245457A CN111245457A CN202010336390.5A CN202010336390A CN111245457A CN 111245457 A CN111245457 A CN 111245457A CN 202010336390 A CN202010336390 A CN 202010336390A CN 111245457 A CN111245457 A CN 111245457A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
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- H04B1/30—Circuits for homodyne or synchrodyne receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
- H04B2001/305—Circuits for homodyne or synchrodyne receivers using dc offset compensation techniques
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Abstract
The invention relates to the field of communication, in particular to a zero intermediate frequency receiver compatible with wide and narrow band signals and a direct current processing method thereof.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a zero intermediate frequency receiver compatible with wide and narrow band signals and a direct current processing method thereof.
Background
In a communication system, an on-chip integrated zero intermediate frequency receiver generally comprises a Low Noise Amplifier (LNA), a quadrature mixer (Qmixer), a Low Pass Filter (LPF), and an analog-to-digital converter (ADC), wherein the low noise amplifier amplifies an input radio frequency signal to reduce the influence of a later stage on a signal-to-noise ratio; the quadrature mixer mixes the radio frequency signal with a local oscillator signal to generate I, Q two paths of zero intermediate frequency signals; the low-pass filter filters out-of-band interference, and provides a certain gain to amplify the signal into an ADC receiving dynamic range; and the ADC converts the signals into digital signals and delivers the digital signals to a rear-stage baseband chip for processing. The receiver of the zero intermediate frequency architecture has small size and low cost, particularly along with the development of a 5G mobile communication protocol, the receiver has the requirements of being downward compatible with the existing communication modes such as GSM, CDMA and the like and supporting a new communication protocol such as 5G NR and the like, and the zero intermediate frequency is a main development direction of an integrated circuit because the zero intermediate frequency has the characteristics of high integration level, easy realization of a filter and good compatibility, and can realize multi-protocol multi-mode and wide-narrow-wide compatibility.
However, the zero intermediate frequency receiver has an inherent defect that, since the local oscillation signal is the same as the radio frequency signal, the direct current interference and the low frequency noise are in the signal band, and the direct current processing is required to avoid affecting the signal-to-noise ratio of the final baseband reception. At present, a zero intermediate frequency receiver in the prior art can only reduce noise for narrow-band received signals, and has low configurability, so that the zero intermediate frequency receiver is difficult to meet the requirements of realizing various modes and function upgrading of a single receiver chip. Therefore, in response to the above deficiencies, it is desirable to provide a wideband-narrowband compatible receiver that covers kHz to hundreds of MHz bandwidth signals.
Disclosure of Invention
The invention aims to provide a zero intermediate frequency receiver which can realize the compatibility of wide and narrow band signals covering kHz to hundreds of MHz and solve the problem of direct current interference corresponding to the wide band and the narrow band.
In order to achieve the above object, the present invention provides a zero intermediate frequency receiver compatible with a wide and narrow band signal, comprising:
the frequency source, the quadrature mixer, the bandwidth-configurable filter, the direct current correction circuit, the direct current offset cancellation loop, the analog-to-digital converter and the digital processing module;
the frequency source is used for generating a local oscillation signal;
the quadrature mixer comprises an I-path radio frequency mixer and a Q-path radio frequency mixer, which are connected with the input radio frequency signal and the frequency source, and are used for mixing the radio frequency signal with the local oscillator signal to respectively generate I, Q two paths of signals;
the bandwidth-configurable filter comprises an I-path analog filter and a Q-path analog filter, which are respectively connected with the output ends of the I-path radio frequency mixer and the Q-path radio frequency mixer and used for filtering out-of-band interference in I, Q two paths of signals;
the analog-to-digital converter comprises an I-path ADC and a Q-path ADC, which are respectively connected with the output ends of the I-path analog filter and the Q-path analog filter and are used for converting the filtered I, Q two-path signals into digital signals;
the digital processing module is connected with the output end of the analog-to-digital converter and is used for detecting the output of the analog-to-digital converter in a broadband receiving mode, carrying out secondary frequency mixing on I, Q two paths of digital signals in a narrow-band receiving mode and outputting signals in any mode;
the direct current offset eliminating loop comprises an I path direct current offset loop and a Q path direct current offset loop, which are respectively connected between the output ends and the input ends of the I path analog filter and the Q path analog filter and are used for respectively forming a band-pass receiving function with the corresponding I path analog filter and the Q path analog filter in a narrow band receiving mode;
the direct current correction circuit comprises an I path direct current offset correction DAC and a Q path direct current offset correction DAC, is connected with the digital processing module and is used for determining correction code values before receiving radio frequency signals according to the I path ADC and the Q path ADC in a broadband receiving mode so as to eliminate direct current offset.
Preferably, the digital processing module comprises a digital mixer, a digital oscillator and a digital selector;
the digital mixer comprises a first I-path digital mixer, a second I-path digital mixer, a first Q-path digital mixer and a second Q-path digital mixer, and the digital selector comprises an I-path selector and a Q-path selector;
the second input end of the I-path selector is connected with an adder for executing addition operation, and the first input end of the Q-path selector is connected with a subtracter for executing subtraction operation;
the output end of the I-path ADC is connected to the first input end of the I-path selector, and is connected to the adder through a first I-path digital mixer, and is connected to the subtracter through a second Q-path digital mixer;
the output end of the Q-path ADC is connected to the second input end of the Q-path selector, and is connected to the adder through a second I-path digital mixer, and is connected to the subtracter through a first Q-path digital mixer;
one end of the digital oscillator is arranged between the first I-path digital mixer and the first Q-path digital mixer, and the other end of the digital oscillator is arranged between the second I-path digital mixer and the second Q-path digital mixer.
Preferably, the local oscillator signal generated by the frequency source is input to the I-path radio frequency mixer and the Q-path radio frequency mixer through the divide-by-2 frequency divider respectively, and the divide-by-2 frequency divider generates an IQ clock.
Preferably, the low-noise amplifier is arranged at the radio-frequency signal input end and used for amplifying the input radio-frequency signal.
Preferably, the mobile terminal further comprises a control module, wherein the control module is connected with the frequency source, the bandwidth-configurable filter, the dc correction circuit, the dc offset cancellation loop and the digital processing module, and is configured to confirm to execute a broadband reception mode or a narrowband reception mode according to a user instruction and/or a radio frequency signal to be input, generate a corresponding control instruction, and send the control instruction.
The invention also provides a direct current processing method of the zero intermediate frequency receiver compatible with the wide and narrow band signals, which adopts the zero intermediate frequency receiver compatible with the wide and narrow band signals, and comprises the following steps:
(1) determining the working modes of the zero intermediate frequency receiver, including a broadband receiving mode and a narrowband receiving mode;
(2) configuring the zero intermediate frequency receiver in a broadband receiving mode, closing the direct current offset elimination loop, detecting the output of the analog-to-digital converter by the digital processing module and inputting the output of the analog-to-digital converter into the direct current correction circuit, correcting the direct current offset by the direct current correction circuit before receiving the radio frequency signal, and keeping the direct current correction circuit unchanged after the radio frequency signal begins to be received;
(3) and configuring the zero intermediate frequency receiver in a narrow band receiving mode, closing the direct current correction circuit, removing direct current offset through the direct current offset eliminating loop, and keeping the direct current offset eliminating loop working in the process of receiving radio frequency signals.
Preferably, in the step (2), when the zero intermediate frequency receiver is configured in a broadband receiving mode, the local oscillation signal output by the frequency source has the same frequency as the radio frequency signal, and the bandwidth configurable filter is switched to a low-pass mode.
Preferably, in step (3), when the zero intermediate frequency receiver is configured in the narrow band receiving mode, a local oscillation signal output by the frequency source and the frequency of the radio frequency signal have a certain frequency offset, the bandwidth-configurable filter is switched to the band pass mode, and the digital processing module performs secondary frequency mixing on I, Q two paths of digital signals in the process of receiving the radio frequency signal.
The technical scheme of the invention has the following advantages: the invention provides a zero intermediate frequency receiver compatible with wide and narrow band signals, which adopts two different circuit structures of a direct current correction circuit and a direct current offset cancellation loop, combines a digital processing module, and respectively processes a broadband receiving signal and a narrow band receiving signal by using two different modes, supports the compatibility of the wide and narrow band signals, and can effectively reduce noise in the received signals.
The invention also provides a zero intermediate frequency receiver direct current processing method compatible with the wide and narrow band signals, which is realized by adopting the zero intermediate frequency receiver and supports the compatibility of the wide and narrow band signals.
Drawings
Fig. 1 is a schematic circuit diagram of a zero intermediate frequency receiver compatible with wide and narrow band signals according to an embodiment of the present invention;
fig. 2 is a diagram of an exemplary dc offset cancellation (DCOC) loop provided in an embodiment of the present invention.
In the figure: 1: an I-path radio frequency mixer; 2: a frequency source; 3: a divide-by-2 frequency divider; 4: a Q-path radio frequency mixer; 5: a Q-path analog filter; 6: q path of direct current offset correction DAC; 7: q direct current offset loop; 8: an I-path analog filter; 9: the I path of direct current offset correction DAC; 10: an I path direct current offset loop; 11: an I-way ADC; 12: a Q-way ADC; 13: an I-path digital mixer; 14: a Q-path digital mixer; 15: a digital oscillator; 16: an I-way path selector; 17: q-way path selector.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Example one
As shown in fig. 1, a zero intermediate frequency receiver compatible with wide and narrow band signals according to an embodiment of the present invention includes: frequency source 2, quadrature mixer, bandwidth configurable filter, direct current correction circuit, direct current offset cancellation loop, analog-to-digital converter and digital processing module, wherein:
the frequency source 2 is connected to a quadrature mixer for generating a local oscillator signal. The frequency at which the frequency source 2 generates the local oscillator signal may be set as desired.
The quadrature mixer comprises an I-path radio frequency mixer 1 and a Q-path radio frequency mixer 4 which are both connected with the externally input radio frequency signal and the frequency source 2 and are used for mixing the externally input radio frequency signal with the local oscillation signal provided by the frequency source 2 to respectively generate I, Q two paths of signals. Preferably, the local oscillator signal generated by the frequency source 2 is input to the I-path radio frequency mixer 1 and the Q-path radio frequency mixer 4 through the divide-by-2 frequency divider 3, respectively, and the divide-by-2 frequency divider 3 generates an IQ clock.
The filter that can be joined in marriage to bandwidth includes I way analog filter 8, Q way analog filter 5, is connected with the output of I way radio frequency mixer 1, Q way radio frequency mixer 4 respectively, promptly, I way analog filter 8 connects the output of I way radio frequency mixer 1, and Q way analog filter 5 connects the output of Q way radio frequency mixer 4 for out of band interference in the filtering I, Q two way signal. The working bandwidth of the bandwidth configurable filter can be determined according to a receiving mode, preferably, a broadband receiving mode corresponds to a low-pass mode of the analog filter, and a narrowband receiving mode corresponds to a band-pass mode of the analog filter.
The analog-to-digital converter comprises an I-path ADC 11 and a Q-path ADC 12, which are respectively connected to the output ends of the I-path analog filter 8 and the Q-path analog filter 5, that is, the I-path ADC 11 is connected to the output end of the I-path analog filter 8, and the Q-path ADC 12 is connected to the output end of the Q-path analog filter 5, and is configured to convert the filtered I, Q two-path signals into digital signals.
The digital processing module is connected with the output end of the analog-to-digital converter, and is used for detecting the output of the analog-to-digital converter in a broadband receiving mode, namely detecting the output of the I-path ADC 11 and the Q-path ADC 12, performing secondary mixing on I, Q paths of digital signals in a narrowband receiving mode, and outputting signals in any mode. The digital processing module has both digital frequency mixing and output detection functions, and a block corresponding to a digital part in fig. 1 shows a manner in which the digital processing module implements digital frequency mixing, and the detection function part is not shown. The broadband signal can be received by adopting zero intermediate frequency, the integral is carried out in the whole bandwidth, and the proportion of direct current/low frequency noise is not large. In a broadband receiving mode, a zero intermediate frequency architecture is preferably adopted, namely, a quadrature mixer is used for mixing, the frequency of a local oscillation signal is the same as that of a radio frequency signal, and foreground calibration is carried out before a channel normally works through the detection function of a digital processing module to eliminate direct current offset. The narrow-band signal is limited by low-frequency noise and direct-current interference, and zero intermediate frequency receiving is not suitable. In a narrow-band receiving mode, in order to avoid direct current offset and low-frequency noise to deteriorate the signal-to-noise ratio, a low-intermediate frequency architecture is preferably adopted, first frequency mixing is carried out, namely, frequency mixing is carried out through a quadrature frequency mixer, a certain frequency offset exists between a local oscillator signal and the frequency of a radio frequency signal, so that direct current offset of a bandwidth-configurable filter can be removed subsequently, secondary frequency mixing is carried out through the frequency mixing function of a digital processing module, and the frequency offset existing between the local oscillator signal and the frequency of the radio frequency signal can be.
The direct current offset cancellation loop comprises an I path direct current offset loop 10 and a Q path direct current offset loop 7 which are respectively connected between the output end and the input end of the I path analog filter 8 and the Q path analog filter 5 and are used for respectively forming a band-pass receiving function with the corresponding I path analog filter 8 and the Q path analog filter 5 in a narrow-band receiving mode, namely, the I path direct current offset loop 10 is connected between the output end and the input end of the I path analog filter 8 and forms a band-pass receiving function with the I path analog filter 8, and the Q path direct current offset loop 7 is connected between the output end and the input end of the Q path analog filter 5 and forms a band-pass receiving function with the Q path analog filter 5. Through the direct current offset elimination loop, the direct current offset can be eliminated in a narrow-band receiving mode.
The direct current correction circuit comprises an I path direct current offset correction DAC 9 and a Q path direct current offset correction DAC 6, wherein the I path direct current offset correction DAC 9 and the Q path direct current offset correction DAC 6 are connected with the digital processing module and used for determining correction code values before receiving radio frequency signals according to the output of an I path ADC 11 and a Q path ADC 12 detected by the digital processing module in a broadband receiving mode so as to eliminate direct current offset.
The zero intermediate frequency receiver provided by the invention has two different working modes, namely a broadband receiving mode and a narrowband receiving mode, and has the function of receiving a wide-range broadband and narrowband signal with a kHz-MHz bandwidth with a high signal-to-noise ratio; meanwhile, the zero intermediate frequency receiver has difference in direct current processing modes in broadband and narrowband receiving modes, but for a user/upper computer, the zero intermediate frequency receiver is a zero intermediate frequency framework, and signals finally output by the zero intermediate frequency receiver are zero intermediate frequency baseband signals without direct current interference no matter broadband and narrowband signals, so that subsequent processing is easy.
Preferably, the digital processing module comprises a digital mixer, a digital oscillator 15 and a digital selector, as shown in fig. 1. The digital mixer includes 2I-channel digital mixers 13, which are a first I-channel digital mixer, a second I-channel digital mixer, and 2Q-channel digital mixers 14, which are a first Q-channel digital mixer and a second Q-channel digital mixer, respectively, and the digital selector includes an I-channel selector 16 and a Q-channel selector 17.
The second input end of the path-I selector 16 is connected to an adder for performing addition, the first input end of the path-Q selector 17 is connected to a subtractor for performing subtraction, that is, the output end of the adder is connected to the second input end of the path-I selector 16, and the output end of the subtractor is connected to the first input end of the path-Q selector 17. The output of the I-path ADC 11 is connected to a first input of the I-path selector 16, and is connected to one of the inputs of the adder via a first I-path digital mixer, and is connected to one of the inputs of the subtractor via a second Q-path digital mixer. The output of the Q-path ADC 12 is connected to the second input of the Q-path selector 17, to one of the inputs of the adder via a second I-path digital mixer, and to one of the inputs of the subtractor via a first Q-path digital mixer.
The digital oscillator 15 has one end disposed between the first I-channel digital mixer and the first Q-channel digital mixer, and one end disposed between the second I-channel digital mixer and the second Q-channel digital mixer.
The technical scheme can realize digital frequency mixing of the digital processing module, and realizes a function of receiving signals compatible with wide and narrow bands by matching with the filter with the configurable bandwidth; in the narrow-band receiving mode, the bandwidth can be matched with a filter and switched into a band-pass mode, the suppression of direct current interference and low-frequency noise is realized through loop suppression in the normal working process of a channel, and the digital mixer is enabled. While fig. 2 shows a typical dc offset cancellation (DCOC) loop, it will be appreciated that in other embodiments, other forms of dc offset cancellation (DCOC) loops may be used.
Preferably, the zero intermediate frequency receiver further comprises a low noise amplifier, and the low noise amplifier is arranged at the radio frequency signal input end and is used for amplifying the input radio frequency signal so as to reduce the influence of the later stage on the signal-to-noise ratio.
Further, in order to realize more convenient switching between the broadband receiving mode and the narrowband receiving mode, in some preferred embodiments, the zero intermediate frequency receiver further includes a control module, and the control module is connected to the frequency source 2, the bandwidth-configurable filter, the dc correction circuit, the dc offset cancellation loop, and the digital processing module. The control module is used for confirming to execute a broadband receiving mode or a narrowband receiving mode according to a user instruction and/or a radio frequency signal to be input, generating a corresponding control instruction and sending the control instruction.
Further, in a broadband receiving mode, the control module generates and sends a corresponding control instruction, responds to the corresponding control instruction, adjusts the local oscillator signal to be the same as the radio frequency signal by the frequency source 2, switches the bandwidth matched filter to a low-pass mode, closes the direct current offset elimination loop, disables the digital mixer, and determines a correction code value before receiving a formal externally input radio frequency signal through the direct current correction circuit to eliminate direct current offset; under the narrow-band receiving mode, the control module generates and sends a corresponding control instruction, in response to the corresponding control instruction, the frequency source 2 adjusts the local oscillation signal until a certain frequency deviation exists between the local oscillation signal and the radio frequency signal, the bandwidth can be matched with the filter and switched to the band-pass mode, the direct current correction circuit is closed, the digital mixer is enabled, the direct current offset elimination loop and the corresponding filter form a band-pass receiving function, and the direct current offset is eliminated.
Example two
The second embodiment provides a method for processing a dc of a zero intermediate frequency receiver compatible with a wide-band signal and a narrow-band signal, which adopts the zero intermediate frequency receiver compatible with a wide-band signal and a narrow-band signal as described in any of the above embodiments, and specifically includes the following steps:
(1) determining the working mode of the zero intermediate frequency receiver, wherein the working mode comprises a broadband receiving mode and a narrow band receiving mode;
(2) configuring a zero intermediate frequency receiver in a broadband receiving mode, closing a direct current offset eliminating loop, detecting the output of an analog-to-digital converter by a digital processing module, inputting the output into a direct current correction circuit, correcting direct current offset by the direct current correction circuit before receiving radio frequency signals, and keeping the direct current correction circuit unchanged after the radio frequency signals are received after the correction is finished;
(3) and configuring a zero intermediate frequency receiver in a narrow band receiving mode, closing the direct current correction circuit, removing direct current offset through the direct current offset eliminating loop, and keeping the direct current offset eliminating loop working in the process of receiving radio frequency signals.
Preferably, in step (2), when the zero intermediate frequency receiver is configured in the broadband receiving mode, the local oscillator signal output by the frequency source 2 has the same frequency as the radio frequency signal, the quadrature mixer mixes the radio frequency signal with the local oscillator signal to generate I, Q two paths of zero intermediate frequency signals, and the bandwidth configurable filter switches to the low-pass mode to implement broadband receiving of the radio frequency signal.
Preferably, in step (3), when the zero intermediate frequency receiver is configured in the narrowband receiving mode, a local oscillation signal output by the frequency source 2 and the frequency of the radio frequency signal have a certain frequency offset, the bandwidth may be configured with a filter to switch to the bandpass mode, and the digital processing module performs secondary frequency mixing on the I, Q two paths of digital signals in the process of receiving the radio frequency signal. The non-digital part of the narrow-band receiving mode zero intermediate frequency receiver adopts a low intermediate frequency architecture, namely, a local oscillator signal and the frequency of a radio frequency signal have certain frequency deviation, and then the frequency deviation is removed by carrying out frequency mixing on the digital part, so that the problem that the direct current offset of a filter cannot be removed because the radio frequency signal is mixed to zero frequency by first frequency mixing is avoided.
Further, in the step (3), the frequency deviation range of the local oscillator signal and the radio frequency signal output by the frequency source 2 is the output frequency range of a digital oscillator (NCO) in the digital processing module, and for simplification of design, the frequency deviation range may be set to 1/N of the system clock, where N is a positive integer and ranges from 8 to 128, and the frequency deviation range is generally 1 to 2MHz, for example, the system clock is 64MHz, and the frequency deviation may be designed to 1MHz, which is sufficient to move the signal to a frequency spectrum far away from direct current and 1/f noise.
The invention provides a direct-current processing method of a zero intermediate frequency receiver compatible with wide and narrow band signals, aiming at the condition of wide band receiving, the receiver adopts a zero intermediate frequency architecture, a direct-current offset elimination loop is closed, a direct-current correction circuit is used, a correction code value is determined before the signals are received, and the correction circuit is not changed after the signals are received. When narrow-band reception is carried out, the receiver adopts a low intermediate frequency framework, a direct current correction circuit is closed, a direct current offset cancellation loop is used, the direct current offset loop always works in the signal receiving process, and a band-pass receiving function is formed by a band-width matched filter. Therefore, the wide-band and narrow-band signals are compatible, and the noise caused by direct current offset is reduced.
The boundary between the specific wideband reception and the narrow-band reception can be considered according to the implementation cost of the bandwidth-configurable filter, and is not further limited herein, and in a typical CMOS process, it is easier to implement a filter bandwidth of several MHz.
EXAMPLE III
The third embodiment is basically the same as the second embodiment, and the same parts are not described again, except that:
in the embodiment, the bandwidths of the I path radio frequency mixer and the Q path radio frequency mixer are designed to be 2 MHz-20 MHz, and 8 bits can be configured; the NCO input reference frequency of the digital oscillator is 25MHz, and the precision is designed to be 32 bit. The precision of the I path of direct current offset correction DAC and the precision of the Q path of direct current offset correction DAC are designed to be 6 bits, and the calibration range is designed to be-8 mV-7 mV. The high pass cut-off point for DCOC is designed to be 100 kHz.
When the frequency of an input radio frequency signal is 800MHz and the bandwidth is 5MHz, the operation mode is determined to be a broadband receiving mode in step (1), and the zero intermediate frequency receiver is configured as follows in step (2):
1. the bandwidth of the filter is configured to be 5MHz, the local oscillation frequency is configured to be 800MHz, and the direct current offset correction DAC is configured to be 32;
2. closing the radio frequency signal input;
3. checking I, Q the size of the two paths of output direct currents in a digital domain, setting a certain data length, and finding out the configuration values of the DACs (the I path direct current offset correction DAC and the Q path direct current offset correction DAC) which enable the direct currents to be minimum through a dichotomy;
4. and fixing the DAC configuration, turning on the radio-frequency signal input, and starting to normally receive the radio-frequency signal.
When the input signal radio frequency is 800MHz and the bandwidth is 50kHz, the operation mode is determined to be the narrowband receiving mode in step (1), and the receiver is configured as follows in step (2):
1. the bandwidth can be configured with a filter to be 2MHz, the local oscillator frequency is configured with 801MHz, and the digital oscillator is configured with 1 MHz;
2. and opening the direct current offset elimination loop (the direct current offset loop I and the direct current offset loop Q) and starting to normally receive the radio frequency signal.
In summary, the present invention provides a zero intermediate frequency receiver compatible with wide and narrow band signals and a dc processing method thereof, in which a filter capable of matching bandwidth in the zero intermediate frequency receiver can perform function switching, and a digital mixer and a dc calibration method in a digital part are used to realize receiving of the wide and narrow band signals. When the broadband is received, the bandwidth can be matched with a filter to be switched into a low-pass mode, the direct current offset is removed before the channel normally receives the radio frequency signal, and the digital mixer is not enabled; when the narrow band is received, the bandwidth can be matched with a filter to be switched into a band-pass mode, direct current interference and low-frequency noise are inhibited through a loop in the process that a channel normally receives radio-frequency signals, and the digital mixer is enabled. The invention can realize the high signal-to-noise ratio reception of wide-range wide-band and narrow-band signals compatible with the kHz-MHz bandwidth; and the structure is relatively simple, the realization is easy, a new zero intermediate frequency framework is provided for a user/upper computer, and the connection is easy.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (8)
1. A zero if receiver compatible with wide and narrow band signals, comprising:
the frequency source, the quadrature mixer, the bandwidth-configurable filter, the direct current correction circuit, the direct current offset cancellation loop, the analog-to-digital converter and the digital processing module;
the frequency source is used for generating a local oscillation signal;
the quadrature mixer comprises an I-path radio frequency mixer and a Q-path radio frequency mixer, which are connected with the input radio frequency signal and the frequency source, and are used for mixing the radio frequency signal with the local oscillator signal to respectively generate I, Q two paths of signals;
the bandwidth-configurable filter comprises an I-path analog filter and a Q-path analog filter, which are respectively connected with the output ends of the I-path radio frequency mixer and the Q-path radio frequency mixer and used for filtering out-of-band interference in I, Q two paths of signals;
the analog-to-digital converter comprises an I-path ADC and a Q-path ADC, which are respectively connected with the output ends of the I-path analog filter and the Q-path analog filter and are used for converting the filtered I, Q two-path signals into digital signals;
the digital processing module is connected with the output end of the analog-to-digital converter and is used for detecting the output of the analog-to-digital converter in a broadband receiving mode, carrying out secondary frequency mixing on I, Q two paths of digital signals in a narrow-band receiving mode and outputting signals in any mode;
the direct current offset eliminating loop comprises an I path direct current offset loop and a Q path direct current offset loop, which are respectively connected between the output ends and the input ends of the I path analog filter and the Q path analog filter and are used for respectively forming a band-pass receiving function with the corresponding I path analog filter and the Q path analog filter in a narrow band receiving mode;
the direct current correction circuit comprises an I path direct current offset correction DAC and a Q path direct current offset correction DAC, is connected with the digital processing module and is used for determining correction code values before receiving radio frequency signals according to the I path ADC and the Q path ADC in a broadband receiving mode so as to eliminate direct current offset.
2. A zero intermediate frequency receiver according to claim 1, characterized in that: the digital processing module comprises a digital mixer, a digital oscillator and a digital selector;
the digital mixer comprises a first I-path digital mixer, a second I-path digital mixer, a first Q-path digital mixer and a second Q-path digital mixer, and the digital selector comprises an I-path selector and a Q-path selector;
the second input end of the I-path selector is connected with an adder for executing addition operation, and the first input end of the Q-path selector is connected with a subtracter for executing subtraction operation;
the output end of the I-path ADC is connected to the first input end of the I-path selector, and is connected to the adder through a first I-path digital mixer, and is connected to the subtracter through a second Q-path digital mixer;
the output end of the Q-path ADC is connected to the second input end of the Q-path selector, and is connected to the adder through a second I-path digital mixer, and is connected to the subtracter through a first Q-path digital mixer;
one end of the digital oscillator is arranged between the first I-path digital mixer and the first Q-path digital mixer, and the other end of the digital oscillator is arranged between the second I-path digital mixer and the second Q-path digital mixer.
3. A zero intermediate frequency receiver according to claim 1, characterized in that:
the frequency source further comprises a divide-by-2 frequency divider, the local oscillator signals generated by the frequency source are respectively input into the I-path radio frequency mixer and the Q-path radio frequency mixer through the divide-by-2 frequency divider, and the divide-by-2 frequency divider generates an IQ clock.
4. A zero intermediate frequency receiver according to claim 1, characterized in that:
the low-noise amplifier is arranged at the input end of the radio frequency signal and is used for amplifying the input radio frequency signal.
5. A zero intermediate frequency receiver according to claim 1, characterized in that:
the control module is connected with the frequency source, the bandwidth-configurable filter, the direct current correction circuit, the direct current offset cancellation loop and the digital processing module, and is used for confirming to execute a broadband receiving mode or a narrowband receiving mode according to a user instruction and/or a radio frequency signal to be input, generating a corresponding control instruction and sending the control instruction.
6. A method for dc processing of a wideband/narrowband signal compatible zero-if receiver, comprising the steps of:
(1) determining the working modes of the zero intermediate frequency receiver, including a broadband receiving mode and a narrowband receiving mode;
(2) configuring the zero intermediate frequency receiver in a broadband receiving mode, closing the direct current offset elimination loop, detecting the output of the analog-to-digital converter by the digital processing module and inputting the output of the analog-to-digital converter into the direct current correction circuit, correcting the direct current offset by the direct current correction circuit before receiving the radio frequency signal, and keeping the direct current correction circuit unchanged after the radio frequency signal begins to be received;
(3) and configuring the zero intermediate frequency receiver in a narrow band receiving mode, closing the direct current correction circuit, removing direct current offset through the direct current offset eliminating loop, and keeping the direct current offset eliminating loop working in the process of receiving radio frequency signals.
7. The method of claim 6, wherein:
in the step (2), when the zero intermediate frequency receiver is configured in a broadband receiving mode, the local oscillation signal output by the frequency source has the same frequency as the radio frequency signal, and the bandwidth-configurable filter is switched to a low-pass mode.
8. The method of claim 6, wherein:
in step (3), when the zero intermediate frequency receiver is configured in the narrow band receiving mode, a local oscillation signal output by the frequency source and the frequency of the radio frequency signal have a certain frequency offset, the bandwidth can be configured with a filter to switch to the band pass mode, and the digital processing module performs secondary frequency mixing on I, Q two paths of digital signals in the process of receiving the radio frequency signal.
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