CN104282665A - High-voltage static protection structure - Google Patents
High-voltage static protection structure Download PDFInfo
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- CN104282665A CN104282665A CN201310294138.2A CN201310294138A CN104282665A CN 104282665 A CN104282665 A CN 104282665A CN 201310294138 A CN201310294138 A CN 201310294138A CN 104282665 A CN104282665 A CN 104282665A
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Abstract
The invention discloses a high-voltage static protection structure. The high-voltage static protection structure comprises an N-type LDMOS which is arranged in an N-type buried layer on a silicon substrate; an active region on the right side of a polycrystalline silicon gate is a drain region of the LDMOS, and is composed of a high-voltage N trap, a P-type injection region, an N-type injection region, a first P+ type diffusion zone and a first N+ type diffusion zone; the P-type injection region is arranged below the first P+ type diffusion zone and part of a field oxidation region, the N-type injection region is arranged below the first N+ type diffusion zone, and the P-type injection region and the N-type injection region are surrounded by the high-voltage N trap; an active region on the left side of the polycrystalline silicon gate is a source region of the N-type LDMOS and is composed of a second N+ type diffusion zone; a second P+ type diffusion zone is arranged between the second N+ type diffusion zone and a third field oxidation zone; the first N+ type diffusion zone of the drain region is connected with an ESD inlet end, and the second N+ type diffusion zone, the second P+ type diffusion zone and the polycrystalline silicon gate of the source region are jointly connected with the ground. By means of the high-voltage static protection structure, the even conduction capacity can be improved, and the snapback voltage can be improved for preventing the latch-up effect.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the high-voltage electrostatic protection structure for electrostatic protection.
Background technology
Electrostatic Discharge is masty problem for the injury of electronic product always; for high-pressure process; the electrostatic protection device not only withstand voltage requirement being greater than supply voltage of demand fulfillment, its electrostatic trigger voltage also needs the damage voltage being less than protected device just passable.As shown in Figure 1; a kind of existing high pressure NLDMOS structure for electrostatic protection is under electrostatic occurs; after ESD positive charge enters the drain electrode of this structure from import and export weld pad; raise the current potential of N-diffusion region; there is avalanche breakdown; breakdown current is drawn by the P+ diffusion region in P trap, raises the current potential of P trap simultaneously, causes the parasitic triode conducting in this structure.The horizontal triode that this triode is made up of the high pressure P trap under drain electrode N-type diffusion region, the N+ diffusion region of source electrode and its raceway groove.This triode is opened and is mainly triggered by the junction breakdown between N-diffusion region and high pressure P trap, and such trigger voltage is general higher, and rapid pressure of wiring back is very low, and not easily regulates, easy trigger latch effect.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of and existing high pressure NLDMOS(horizontal proliferation metal field effect transistor) high-voltage electrostatic protection structure of not easily trigger latch effect compared with structure.
For solving the problems of the technologies described above, high-voltage electrostatic protection structure of the present invention, comprising: a N-type LDMOS entirety is placed in the n type buried layer above a silicon substrate;
Active area on the right side of polysilicon gate is the drain region of described LDMOS, the P-injection region that described drain region comprises a P+ diffusion region and is positioned at below it, one N+ diffusion region and the N-injection region be positioned at below it, one P+ diffusion region is adjacent with a N+ diffusion region, and P-injection region is adjacent with N-injection region; One N+ diffusion region has the first Chang Yang district away from the side of polysilicon gate, and a P+ diffusion region has the second Chang Yang district near the side of polysilicon gate;
Active area on the left of polysilicon gate is the source region of N-type LDMOS, and described source region comprises the 2nd N+ diffusion region, and the 2nd N+ diffusion region has the 3rd Chang Yang district away from polysilicon gate side, and the 2nd P+ diffusion region has the 4th Chang Yang district away from polysilicon gate side;
P-injection region and N-injection region are surrounded by high pressure N trap, and the 2nd P+ diffusion region and the 2nd N+ diffusion region are surrounded by high pressure P trap; Polysilicon gate is positioned at above high pressure P trap, high pressure N trap and n type buried layer;
One N+ diffusion region connects ESD input, the 2nd N+ diffusion region, the 2nd P+ diffusion region and polysilicon gate ground connection in the lump.
Wherein, a N+ diffusion region is all positioned at above N-injection region, and the first Chang Yang district part is positioned at above N-injection region, and part is positioned at above n type buried layer.
Wherein, a P+ diffusion region is all positioned at above P-injection region, and the second Chang Yang district part is positioned at above P-injection region, and part is positioned at above high pressure N trap.
When there being electrostatic to enter from drain electrode, being opened by the parasitic triode of the high pressure P trap composition under the 2nd N+ diffusion region of drain electrode high pressure N trap, source electrode and its raceway groove and releasing.Relative to existing LDMOS structure (as shown in Figure 1), structure of the present invention adds a P+ expanding district and P-injection region at drain terminal, CURRENT DISTRIBUTION after parasitic triode is opened, away from the beak region easily causing the field oxide region lost efficacy, ensure that the lifting of the electrostatic leakage ability of LDMOS device.In addition, due to the increase of a P+ expanding district and P-injection region, make LDMOS when there is rapid returning, namely n-n+ the diode drained puncture generation time, the base width of its equivalent triode and relative concentration are wider denseer in the common LDMOS, cause the multiplication factor of triode now (Beta) to diminish like this, therefore its pressure of suddenly wiring back also can correspondingly improve.
Such change had both been conducive to the uniform conducting ability of LDMOS under many finger-like arrangements, was also conducive to improving the generation that rapid pressure of wiring back prevents latch-up, improved the electrostatic of entirety of the present invention and the protective capacities of breech lock with this.Structure of the present invention can apply in the electrostatic protection application of the high pressure port of BCD technique.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is a kind of high pressure NLDMOS structure of existing electrostatic protection.
Fig. 2 is the structural representation of one embodiment of the invention.
Description of reference numerals
1 ~ 4 is the first Chang Yang district ~ the 4th Chang Yang districts
5 is N+ diffusion regions
6 is P+ expanding districts
7 is P-injection regions
8 is N-injection regions
9 is high pressure N traps
10 is n type buried layers
11 is silicon substrates
12 is the 2nd N+ diffusion regions
13 is the 2nd P+ diffusion regions
14 is high pressure P traps
15 is polysilicon gates
E is electrostatic end
G is ground
Embodiment
One embodiment of the invention comprises: a N-type LDMOS entirety is placed in the n type buried layer 10 above a silicon substrate 11; Active area on the right side of polysilicon gate 15 is the drain region of described LDMOS, the P-injection region 7 that described drain region comprises a P+ diffusion region 5 and is positioned at below it, one N+ diffusion region 6 and the N-injection region 8 be positioned at below it, one P+ diffusion region 5 is adjacent with a N+ diffusion region 6, and P-injection region 7 is adjacent with N-injection region 8; One N+ diffusion region 6 has the first P+ diffusion region 5, Chang Yang district the 1, one away from the side of polysilicon gate 15 and has the second Chang Yang district 2 near the side of polysilicon gate 15;
Active area on the left of polysilicon gate 15 is the source region of N-type LDMOS, described source region comprises the 2nd N+ diffusion region 12,2nd N+ diffusion region 12 has the 3rd P+ diffusion region 13, Chang Yang district the 3, two away from side, polysilicon gate 15 pole and has the 4th Chang Yang district 4 away from polysilicon gate 15 side;
P-injection region 7 and N-injection region 8 are surrounded by high pressure N trap 9, and the 2nd P+ diffusion region 12 and the 2nd N+ diffusion region 13 are surrounded by high pressure P trap 14; Polysilicon gate 15 is positioned at above high pressure P trap 14, high pressure N trap 9 and n type buried layer 10;
One N+ diffusion region 6 connects ESD input E, the 2nd N+ diffusion region 12, the 2nd P+ diffusion region 13 and polysilicon gate 15 ground connection G in the lump.
The thickness in the first Chang Yang district 1 is greater than N+ diffusion region thickness the 6, an one N+ diffusion region 6 and is all positioned at above N-injection region 8, and the first Chang Yang district 1 part is positioned at above N-injection region 8, and part is positioned at above n type buried layer 10.
The thickness in the second Chang Yang district 2 is greater than P+ diffusion region thickness the 5, an one P+ diffusion region 5 and is all positioned at above P-injection region 7, and the second Chang Yang district 2 part is positioned at above P-injection region 7, and part is positioned at above high pressure N trap 10.
Below through the specific embodiment and the embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (3)
1. a high-voltage electrostatic protection structure, is characterized in that, comprising: a N-type LDMOS entirety is placed in the n type buried layer above a silicon substrate;
Active area on the right side of polysilicon gate is the drain region of described LDMOS, the P-injection region that described drain region comprises a P+ diffusion region and is positioned at below it, one N+ diffusion region and the N-injection region be positioned at below it, one P+ diffusion region is adjacent with a N+ diffusion region, and P-injection region is adjacent with N-injection region; One N+ diffusion region has the first Chang Yang district away from the side of polysilicon gate, and a P+ diffusion region has the second Chang Yang district near the side of polysilicon gate;
Active area on the left of polysilicon gate is the source region of N-type LDMOS, and described source region comprises the 2nd N+ diffusion region, and the 2nd N+ diffusion region has the 3rd Chang Yang district away from polysilicon gate side, and the 2nd P+ diffusion region has the 4th Chang Yang district away from polysilicon gate side;
P-injection region and N-injection region are surrounded by high pressure N trap, and the 2nd P+ diffusion region and the 2nd N+ diffusion region are surrounded by high pressure P trap; Polysilicon gate is positioned at above high pressure P trap, high pressure N trap and n type buried layer;
One N+ diffusion region connects ESD input, the 2nd N+ diffusion region, the 2nd P+ diffusion region and polysilicon gate ground connection in the lump.
2. high-voltage electrostatic protection structure as claimed in claim 1, it is characterized in that: a N+ diffusion region is all positioned at above N-injection region, the first Chang Yang district part is positioned at above N-injection region, and part is positioned at above n type buried layer.
3. high-voltage electrostatic protection structure as claimed in claim 1, it is characterized in that: a P+ diffusion region is all positioned at above P-injection region, the second Chang Yang district part is positioned at above P-injection region, and part is positioned at above high pressure N trap.
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| CN201310294138.2A CN104282665B (en) | 2013-07-12 | 2013-07-12 | High-voltage electrostatic protection structure |
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| CN201310294138.2A CN104282665B (en) | 2013-07-12 | 2013-07-12 | High-voltage electrostatic protection structure |
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| CN104282665B CN104282665B (en) | 2017-04-05 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244349A (en) * | 2015-10-27 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Electrostatic protection circuit |
| CN108336085A (en) * | 2018-03-21 | 2018-07-27 | 湖南静芯微电子技术有限公司 | A kind of small island thyristor electrostatic protection device of grid insertion |
| CN110828426A (en) * | 2018-08-10 | 2020-02-21 | 世界先进积体电路股份有限公司 | Semiconductor structure and electrostatic protection device |
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| US20090096022A1 (en) * | 2007-10-15 | 2009-04-16 | Fitipower Integrated Technology, Inc. | Lateral diffused metal oxide semiconductor device |
| CN101752347A (en) * | 2008-12-19 | 2010-06-23 | 上海华虹Nec电子有限公司 | Electrostatic protection structure and manufacturing method thereof |
| JP2011211078A (en) * | 2010-03-30 | 2011-10-20 | Oki Semiconductor Co Ltd | Semiconductor device and method of manufacturing the same |
| US20120074497A1 (en) * | 2010-09-25 | 2012-03-29 | Xiang Gao | Esd protection structure |
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2013
- 2013-07-12 CN CN201310294138.2A patent/CN104282665B/en active Active
Patent Citations (4)
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| US20090096022A1 (en) * | 2007-10-15 | 2009-04-16 | Fitipower Integrated Technology, Inc. | Lateral diffused metal oxide semiconductor device |
| CN101752347A (en) * | 2008-12-19 | 2010-06-23 | 上海华虹Nec电子有限公司 | Electrostatic protection structure and manufacturing method thereof |
| JP2011211078A (en) * | 2010-03-30 | 2011-10-20 | Oki Semiconductor Co Ltd | Semiconductor device and method of manufacturing the same |
| US20120074497A1 (en) * | 2010-09-25 | 2012-03-29 | Xiang Gao | Esd protection structure |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244349A (en) * | 2015-10-27 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Electrostatic protection circuit |
| CN105244349B (en) * | 2015-10-27 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | Electrostatic discharge protective circuit |
| CN108336085A (en) * | 2018-03-21 | 2018-07-27 | 湖南静芯微电子技术有限公司 | A kind of small island thyristor electrostatic protection device of grid insertion |
| CN108336085B (en) * | 2018-03-21 | 2023-12-19 | 湖南静芯微电子技术有限公司 | Grid embedded island type silicon controlled electrostatic protection device |
| CN110828426A (en) * | 2018-08-10 | 2020-02-21 | 世界先进积体电路股份有限公司 | Semiconductor structure and electrostatic protection device |
| CN110828426B (en) * | 2018-08-10 | 2024-03-05 | 世界先进积体电路股份有限公司 | Semiconductor structure and electrostatic protection device |
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|---|---|
| CN104282665B (en) | 2017-04-05 |
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