CN104253124B - High-voltage electrostatic protection structure - Google Patents

High-voltage electrostatic protection structure Download PDF

Info

Publication number
CN104253124B
CN104253124B CN201310261537.9A CN201310261537A CN104253124B CN 104253124 B CN104253124 B CN 104253124B CN 201310261537 A CN201310261537 A CN 201310261537A CN 104253124 B CN104253124 B CN 104253124B
Authority
CN
China
Prior art keywords
active area
ldmos
type
region
high
Prior art date
Application number
CN201310261537.9A
Other languages
Chinese (zh)
Other versions
CN104253124A (en
Inventor
苏庆
邓樟鹏
苗彬彬
张强
Original Assignee
上海华虹宏力半导体制造有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海华虹宏力半导体制造有限公司 filed Critical 上海华虹宏力半导体制造有限公司
Priority to CN201310261537.9A priority Critical patent/CN104253124B/en
Publication of CN104253124A publication Critical patent/CN104253124A/en
Application granted granted Critical
Publication of CN104253124B publication Critical patent/CN104253124B/en

Links

Abstract

The invention discloses a kind of high-voltage electrostatic protection structure, including:One N-type LDMOS is integrally placed in the n type buried layer above a silicon substrate;Active area on the right side of the polysilicon gate of the LDMOS device is the drain region of the device, and there are N+ types injection region, N injection regions and high pressure N traps in the drain region lower section;Active area on the left of the polysilicon gate is the source region of the device, there is N+ types injection region the source region lower section, opposite field oxygen zone isolation has the first p-type active area on the left of the N+ types injection region, and opposite field oxygen zone isolation has the second p-type active area on the left of the first p-type active area;The present invention can effectively reduce the trigger voltage of LDMOS structure, be conducive to uniform conducting abilities of the LDMOS under the arrangement of many finger-like, and improve the high-voltage electrostatic protection structure of overall antistatic capacity.

Description

High-voltage electrostatic protection structure

Technical field

The present invention relates to IC manufacturing field, more particularly to a kind of high-voltage electrostatic protection structure.

Background technology

Static discharge(ESD)It is always masty problem for the injury of electronic product, for high-pressure process, Electrostatic protection device is not only needed to meet the pressure-resistant requirement for being greater than supply voltage, and its electrostatic trigger voltage is also needed to be less than and protected The damage voltage for protecting device just can be with.As shown in figure 1, the high pressure NLDMOS structures for being generally used for electrostatic protection occur in electrostatic Under, after ESD positive charges enter the drain electrode of this structure from import and export weld pad, the current potential of N- diffusion regions is raised, there is avalanche breakdown, puncture Electric current is drawn by the P+ diffusion regions in p-well, while raising the current potential of p-well, causes the parasitic triode in this structure to turn on.Should The horizontal triode that triode is made up of the high pressure p-well under drain electrode N-type diffusion region, the N+ diffusion regions of source electrode and its raceway groove. This triode is opened and mainly triggered by the junction breakdown between N- diffusion regions and high pressure p-well, and trigger voltage is typically higher, no Easily play a protective role.

The content of the invention

The technical problem to be solved in the present invention is to provide a kind of trigger voltage that can effectively reduce LDMOS structure, favorably In uniform conducting abilities of the LDMOS under the arrangement of many finger-like, and improve the high-voltage electrostatic protection structure of overall antistatic capacity.

In order to solve the above technical problems, electrostatic preventing structure of the invention, including:One N-type LDMOS is integrally placed at silicon lining In n type buried layer above bottom;Active area on the right side of the polysilicon gate of the LDMOS device is the drain region of the device, its connection There are N+ types injection region, N- injection regions and high pressure N traps in ESD upstream ends, the drain region lower section;It is active on the left of the polysilicon gate Area is the source region of the device, and there is N+ types injection region source region lower section, on the left of the N+ types injection region opposite field oxygen region every From there is the first p-type active area, opposite field oxygen zone isolation has the second p-type active area on the left of the first p-type active area;

The LDMOS device its drain electrode connection ESD upstream end, its source electrode is grounded with the first p-type active area, and described the Two p-type active areas connect altogether with the LDMOS device polysilicon gate.

Wherein, the polysilicon gate of the LDMOS passes through its drain region of a capacitance connection.

During present invention work, when there is electrostatic to enter from drain electrode, by the electric capacity between drain electrode and grid(Or LDMOS sheets Parasitic capacitance between body grid leak)And the resistance that the p-well between grid and ground terminal is formed, RC termination powers are constituted, can be in grid It is extremely upper to couple a current potential.So that the raceway groove of this LDMOS turns on to form electric current, and trigger by drain electrode N-type diffusion region, the N of source electrode The parasitic triode of the high pressure p-well composition under+diffusion region and its raceway groove is opened.Relative to common LDMOS structure(Such as Fig. 1 It is shown), the knot that structure of the present invention can be between N- diffusion regions and high pressure p-well is provided with a substrate before reaching breakdown voltage Electric current so that substrate electric potential triggers parasitic triode and open higher than more than the current potential 0.6V of source N-type diffusion region.Thus have The trigger voltage for reducing LDMOS structure of effect, is conducive to uniform conducting abilities of the LDMOS under the arrangement of many finger-like, also favorably Electrostatic damage is not received in internal circuit is protected, and overall antistatic capacity is improved with this.Electrostatic preventing structure of the invention In the electrostatic protection application of the high pressure port that can also apply to BCD techniques.

Brief description of the drawings

The present invention is further detailed explanation with specific embodiment below in conjunction with the accompanying drawings:

Fig. 1 is a kind of structural representation of existing high-pressure electrostatic protection.

Fig. 2 is the structural representation one of high-pressure electrostatic protection of the present invention, its display plan structure of the invention.

Fig. 3 is the structural representation two of high-pressure electrostatic protection of the present invention, its display sectional structure of the invention.

Description of reference numerals

1 is silicon substrate

2 is n type buried layer

3 is high pressure p-well

4 is high pressure N traps

5 is N- injection regions

6 is polysilicon gate

7th, 8 is N+ types injection region

9th, 11 is an oxygen region

10 is the first p-type active area

12 is the second p-type active area

13 is metal connecting line

C is electric capacity

Specific embodiment

As shown in Figure 2 and Figure 3, one embodiment of the invention, including:One N-type LDMOS is integrally placed at the N of the top of a silicon substrate 1 In type buried regions 2;The active area on the right side of polysilicon gate 6 of the LDMOS device is the drain region of the device, and its connection ESD enters There are N+ types injection region 7, N- injection regions 5 and high pressure N traps 4 in end, the drain region lower section;Active area on the left of the polysilicon gate is There is N+ types injection region 8 source region of the device, the source region lower section, isolates in the left side opposite field oxygen region 9 of the N+ types injection region 8 There is the first p-type active area 10, isolation has the second p-type active area 12 in 10 left side opposite field oxygen region of the first p-type active area 11;

Its drain region of the LDMOS device connects ESD upstream ends, and its source region is grounded with the first p-type active area 10, described Second p-type active area 12 connects altogether with the LDMOS device polysilicon gate, and the polysilicon gate of the LDMOS passes through an electric capacity C Connect its drain region.

When there is electrostatic to enter from drain electrode during work, by between the electric capacity and grid and ground terminal between drain electrode and grid The resistance that p-well is formed, constitutes RC termination powers, and a current potential can be coupled on grid.So that the raceway groove of this LDMOS turns on to be formed Electric current, and trigger parasitic three pole being made up of the high pressure p-well under drain electrode N-type diffusion region, the N+ diffusion regions of source electrode and its raceway groove Pipe is opened.Structure of the present invention can be between N- diffusion regions and high pressure p-well knot reach breakdown voltage before be provided with one lining Bottom electric current so that substrate electric potential triggers parasitic triode and open higher than more than the current potential 0.6V of source N-type diffusion region.

The present invention has been described in detail above by specific embodiment and embodiment, but these not constitute it is right Limitation of the invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change Enter, these also should be regarded as protection scope of the present invention.

Claims (2)

1. a kind of high-voltage electrostatic protection structure, it is characterised in that including:One N-type LDMOS is integrally placed at the N above a silicon substrate In type buried regions;Active area on the right side of the polysilicon gate of the LDMOS device is the drain region of the device, its connection ESD upstream end, There are N+ types injection region, N- injection regions and high pressure N traps in the drain region lower section;Active area on the left of the polysilicon gate is the device Source region, there is N+ types injection region source region lower section, and opposite field oxygen zone isolation has the first p-type on the left of the N+ types injection region Active area, opposite field oxygen zone isolation has the second p-type active area on the left of the first p-type active area;
The LDMOS device its drain electrode connection ESD upstream end, its source electrode is grounded with the first p-type active area, the 2nd P Type active area connects altogether with the LDMOS device polysilicon gate.
2. high-voltage electrostatic protection structure as claimed in claim 1, it is characterised in that:The polysilicon gate of the LDMOS passes through Its drain region of one capacitance connection.
CN201310261537.9A 2013-06-27 2013-06-27 High-voltage electrostatic protection structure CN104253124B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310261537.9A CN104253124B (en) 2013-06-27 2013-06-27 High-voltage electrostatic protection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310261537.9A CN104253124B (en) 2013-06-27 2013-06-27 High-voltage electrostatic protection structure

Publications (2)

Publication Number Publication Date
CN104253124A CN104253124A (en) 2014-12-31
CN104253124B true CN104253124B (en) 2017-06-06

Family

ID=52187882

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310261537.9A CN104253124B (en) 2013-06-27 2013-06-27 High-voltage electrostatic protection structure

Country Status (1)

Country Link
CN (1) CN104253124B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105489602B (en) * 2015-12-29 2018-07-20 东南大学 A kind of electrostatic discharge protector with low trigger voltage

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101752347A (en) * 2008-12-19 2010-06-23 上海华虹Nec电子有限公司 Electrostatic protection structure and manufacturing method thereof
CN102376761A (en) * 2010-08-24 2012-03-14 中芯国际集成电路制造(上海)有限公司 LDMOS ESD(Laterally Diffused Metal Oxide Semiconductor Electro-Static Discharge) structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI358813B (en) * 2008-04-21 2012-02-21 Vanguard Int Semiconduct Corp Trig modulation electrostatic discharge (esd) prot

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101752347A (en) * 2008-12-19 2010-06-23 上海华虹Nec电子有限公司 Electrostatic protection structure and manufacturing method thereof
CN102376761A (en) * 2010-08-24 2012-03-14 中芯国际集成电路制造(上海)有限公司 LDMOS ESD(Laterally Diffused Metal Oxide Semiconductor Electro-Static Discharge) structure

Also Published As

Publication number Publication date
CN104253124A (en) 2014-12-31

Similar Documents

Publication Publication Date Title
TWI343119B (en)
CN102714205B (en) There is the bond pad of integrated transient overvoltage protection
TW201613111A (en) Semiconductor device and manufacturing method thereof
TW200941721A (en) Simulated 3D View of 2D Background Images and Game Objects
CN100592533C (en) Transversely diffused metal oxide transistor
CN101517727B (en) Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch
CN101741073B (en) Structures for electrostatic discharge protection
CN101807598B (en) One kind pnpnp type triac
CN101339956A (en) Semi-conductor apparatus
TWI256669B (en) Semiconductor device and manufacturing method of the same
US7838924B2 (en) MOS device with substrate potential elevation
US20140167099A1 (en) Integrated circuit including silicon controlled rectifier
US8912605B1 (en) ESD protection circuit
CN203811938U (en) Display panel and display device
US8466514B2 (en) Semiconductor power device integrated with improved gate source ESD clamp diodes
US20130285113A1 (en) Bidirectional electrostatic discharge (esd) protection device
US8492834B2 (en) Electrostatic discharge protection device and applications thereof
CN102842576A (en) Semiconductor device
US9018705B2 (en) ESD transistor
CN102412294A (en) Device used as electric static protection structure
TW200845353A (en) A semiconductor structure for protecting an internal integrated circuit
US8703547B2 (en) Thyristor comprising a special doped region characterized by an LDD region and a halo implant
CN100470803C (en) ESD protection circuit for enlarging the valid circulation area of the static current
CN101047178A (en) Low trigger voltage silicon control rectifier and its circuit
KR20140145263A (en) Electrostatic discharge high voltage type transistor and electrostatic dscharge protection circuit thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant