CN104280964B - A kind of array base palte, display panel and display device - Google Patents
A kind of array base palte, display panel and display device Download PDFInfo
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- CN104280964B CN104280964B CN201410594437.2A CN201410594437A CN104280964B CN 104280964 B CN104280964 B CN 104280964B CN 201410594437 A CN201410594437 A CN 201410594437A CN 104280964 B CN104280964 B CN 104280964B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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Abstract
The invention discloses a kind of array base palte, display panel and display device, the array base palte includes：A plurality of data lines；1st gate line is to 2N gate lines；Multiple pixels, are arranged as N number of pixel column, and multiple pixels include the first pixel and the second pixel；First pixel is alternately distributed with the second pixel along gate line bearing of trend and along along data wire bearing of trend, the opposite polarity for the data-signal that the first pixel is applied in the second pixel；In one frame, in the first stage, the first pixel of any odd number pixel rows and any even pixel row is gradually driven simultaneously, until first pixel of driving all pixels row；In second stage, the second pixel of any odd number pixel rows and any even pixel row is gradually driven simultaneously, until second pixel of driving all pixels row.Row is driven into the invention enables the first pixel and the second pixel charger assembled by several branch, as long as data wire carries out primary voltage dipole inversion, it is to avoid data wire charging ability is not enough, the problem of power consumption is big.
Description
Technical field
The present invention relates to display device technology field, more particularly to a kind of array base palte, display panel and display dress
Put.
Background technology
Liquid crystal display device has the advantages that profile is frivolous, power consumption is few, radiationless pollution, has been widely used in electricity
On the electronic products such as brain, personal digital assistant, mobile phone.The type of drive of existing liquid crystal display device includes：Frame is inverted
(Frame Inversion) mode, line reversion (Line Inversion) mode and dot inversion (Dot Inversion) mode,
And in dot inversion mode as the liquid crystal display device of type of drive, cross-talk phenomenon is improved, improve display effect.
With reference to Fig. 1, Fig. 1 is the schematic diagram for the principle that array base palte carries out dot inversion driving, when carrying out dot inversion driving,
In same two field picture, its polarity of voltage and the polarity of voltage of four pixels of its arest neighbors is needed to be contrary to any pixel；And
The image a and image b adjacent to two frames, polarity of voltage of any pixel in image a and the polarity of voltage phase in image b
Instead.
For the pixel of n × m array arrangement, existing array base palte is to use n-th grade of gate lines G n of first order gate lines G 1-
Common n bars gate line, each grid line traffic control one-row pixels, using the first common m data lines of data wire D1- m data wires Dm,
Each data line controls a row pixel.Wherein m, n are positive integer.
, it is necessary to each gate line be opened line by line, in order to meet each picture of dot inversion type of drive during progress raster data model
The polarity of voltage of element, per data line when adjacent gate polar curve is scanned, it is necessary to change polarity of voltage, to meet dot inversion drive
The polarity of voltage requirement of flowing mode pixel.Due to there is parasitic capacitance on data wire, the change of data line voltage polarity can cause
The charging ability of data wire is not enough, and power consumption is larger.
With reference to Fig. 2, Fig. 2 is a kind of structural representation for the array base palte for realizing dot inversion type of drive in the prior art,
In Fig. 2 by taking the pixel of 4 × 4 array arrangements as an example explanation.First data wire during pixel charging effect to realize image b in Fig. 1
Exemplified by D1 working methods, when first order gate lines G 1 is opened, the first data wire D1 is needed for positive voltage, in second level gate line
During opening, it needs to be converted to negative voltage, and when third level gate line is opened, it needs to be converted to positive voltage, in fourth stage grid
When polar curve is opened, it needs to be converted to negative voltage.The conversion of data wire polarity of voltage each time, is required to overcome its parasitic electricity
Hold, cause power consumption larger, and it is not enough to be easily caused data wire charging ability.
Although dot inversion mode is the liquid crystal display device of type of drive in the prior art, improves cross-talk phenomenon,
Improve display effect, it is to avoid the problem of stroboscopic, still, existing dot inversion type of drive can cause the data of display panel
The charging ability of line is not enough, and power consumption is big.
The content of the invention
In view of this, the invention provides a kind of array base palte, display panel and display device, it is to avoid number during dot inversion
Not enough, the problem of power consumption is big according to the charging ability of line.
To achieve the above object, the present invention provides following technical scheme：
A kind of array base palte, the array base palte includes：
A plurality of data lines；
2N bar gate lines, including the 1st gate line, to 2N gate lines, N is positive integer；
Multiple pixels, are arranged as N number of pixel column, and the data wire outputting data signals give the pixel, the multiple picture
Element includes the first pixel and the second pixel；
First pixel is alternately distributed with second pixel along along gate line bearing of trend, and is prolonged along data wire
Stretch and be alternately distributed on direction, the opposite polarity for the data-signal that first pixel is applied in the second pixel；
Wherein, in a frame, including first stage and second stage,
In the first stage, first pixel and any even pixel row of any odd number pixel rows are gradually driven simultaneously
First pixel, until first pixel of driving all pixels row；
In second stage, the second pixel and the second of any even pixel row of any odd number pixel rows is gradually driven simultaneously
Pixel, until second pixel of driving all pixels row.
It is preferred that, in above-mentioned array base palte,
It is described in the first stage, first pixels of any odd number pixel rows and any even pixel are gradually driven simultaneously
The first capable pixel, until first pixel of driving all pixels row is specifically included：
In the first stage, first pixel in a pixel columns and a+b pixel columns is first driven simultaneously, is driven simultaneously afterwards
First pixel in dynamic a+1 pixel columns and a+1+b pixel columns, with this rule, until the institute of driving all pixels row
State the first pixel；
Second pixel and any even pixel row for gradually driving any odd number pixel rows in second stage simultaneously
Second pixel, until second pixel of driving all pixels row is specifically included：
In second stage, second pixel in a pixel columns and a+b pixel columns is first driven simultaneously, is driven simultaneously afterwards
Second pixel in dynamic a+1 pixel columns and a+b+1 pixel columns, with this rule, until the institute of driving all pixels row
State the second pixel；
Wherein, a is positive integer, and b is the odd number more than 1, and a+1+b is less than or equal to N.
It is preferred that, in above-mentioned array base palte,
It is described in the first stage, first pixels of any odd number pixel rows and any even pixel are gradually driven simultaneously
The first capable pixel, until first pixel of driving all pixels row is specifically included：
In the first stage, a+2+b is less than or equal to N, first drives simultaneously described in a pixel columns and a+b pixel columns
First pixel, rear first pixel driven simultaneously in a+2 pixel columns and a+2+b pixel columns, with this rule, until driving
First pixel of dynamic all pixels row；Or, a+2+b is more than N, first drives simultaneously in a pixel columns and a+b pixel columns
First pixel, rear first pixel driven simultaneously in a+2 pixel columns and a+2+b-N pixel columns advised with this
Rule, until first pixel of driving all pixels row；
Second pixel and any even pixel row for gradually driving any odd number pixel rows in second stage simultaneously
Second pixel, until second pixel of driving all pixels row is specifically included：
In second stage, a+2+b is less than or equal to N, first drives simultaneously described in a pixel columns and a+b pixel columns
Second pixel, rear second pixel driven simultaneously in a+2 pixel columns and a+2+b pixel columns, with this rule, until driving
Second pixel of dynamic all pixels row；Or, a+2+b is more than N, first drives simultaneously in a pixel columns and a+b pixel columns
Second pixel, rear second pixel driven simultaneously in a+2 pixel columns and a+2+b-N pixel columns advised with this
Rule, until second pixel of driving all pixels row；Wherein, a is positive integer, and b is odd number, and a+2 is less than N.
It is preferred that, in above-mentioned array base palte,
In the first stage, first pixel and any even pixel row of any odd number pixel rows are gradually driven simultaneously
First pixel, until first pixel of driving all pixels row is specifically included：
In the first stage, a+3 is less than or equal to N, and described the in a pixel columns and a+1 pixel columns is first driven simultaneously
One pixel, rear first pixel driven simultaneously in a+2 pixel columns and a+3 pixel columns；Or, a+3 is more than N, first same
When drive first pixel in a pixel columns and a+1 pixel columns, it is rear to drive a+2 pixel columns and a+3-N pictures simultaneously
First pixel in plain row, with this rule, until first pixel of driving all pixels row；
In second stage, the second pixel and the second of any even pixel row of any odd number pixel rows is gradually driven simultaneously
Pixel, until second pixel of driving all pixels row is specifically included：
In second stage, a+3 is less than or equal to N, and described the in a pixel columns and a+1 pixel columns is first driven simultaneously
Two pixels, rear second pixel driven simultaneously in a+2 pixel columns and a+3 pixel columns, or, a+3 is more than N, first same
When drive second pixel in a pixel columns and a+1 pixel columns, it is rear to drive a+2 pixel columns and a+3-N pictures simultaneously
Second pixel in plain row is with this rule, until second pixel of driving all pixels row；
Wherein, a is positive integer.
It is preferred that, in above-mentioned array base palte,
First pixel of ith pixel row is coupled to 2i-1 gate lines, the second pixel coupling of the ith pixel row
In 2i gate lines, i is the positive integer less than or equal to N；Also,
First pixel of i+1 pixel column is coupled to 2i+2 gate lines, the second pixel of the i+1 pixel column
2i+1 gate lines are coupled to, i is the positive integer less than or equal to N-1.
It is preferred that, in above-mentioned array base palte,
First pixel of jth pixel column is coupled to 2j-1 gate lines, the second pixel coupling of the jth pixel column
In 2j gate lines, j is the positive integer less than or equal to N；Also,
First pixel of the pixel column of jth+1 is coupled to 2j+1 gate lines, the second pixel of the pixel column of jth+1
2j+2 gate lines are coupled to, j is the positive integer less than or equal to N-1.
It is preferred that, in above-mentioned array base palte,
In the first stage, the data-signal of all described data wire outputs is the first polarity；
In second stage, the data-signal of all described data wire outputs is the second polarity；
Wherein, first polarity and the second polarity opposite polarity each other.
It is preferred that, in above-mentioned array base palte, 2c-1 gate lines and 2c gate lines are positioned at the same side of c pixel columns
Or it is located at the both sides of the c pixel columns respectively, c is the positive integer less than or equal to N.
It is preferred that, in above-mentioned array base palte, the polarity and the opposite polarity of the second frame of the first frame of each pixel,
Wherein, first frame and second frame are front and rear two adjacent frames.
Present invention also offers a kind of display panel, the display panel includes the array base palte described in any of the above-described.
Present invention also offers a kind of display device, the display device includes the array base palte described in any of the above-described.
First pixel described in the array base palte provided by foregoing description, technical solution of the present invention and second picture
Element is alternately distributed along along gate line bearing of trend, and is alternately distributed along along data wire bearing of trend, first pixel with
The opposite polarity for the data-signal that second pixel is applied in；Wherein, in a frame, including first stage and second stage,
In one stage, first pixel of any odd number pixel rows and the first pixel of any even pixel row gradually are driven simultaneously, directly
To first pixel for driving all pixels row；In second stage, the second picture of any odd number pixel rows is gradually driven simultaneously
Plain the second pixel with any even pixel row, until second pixel of driving all pixels row.So, institute can be caused
There is the charging process of the first pixel and second pixel completely separable, arbitrary data line is charged in same two field picture pixel
When, as long as carrying out primary voltage dipole inversion, the number of times of data line voltage dipole inversion is greatly reduced, so as to avoid data
Line charging ability is not enough, the problem of power consumption is big.
The display panel and display device that the present invention is provided, with the array base palte, can realize that its point is anti-
Turn, type of drive is simple, low in energy consumption.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is the schematic diagram for the principle that array base palte carries out dot inversion driving；
Fig. 2 is a kind of structural representation for the array base palte for realizing dot inversion type of drive in the prior art；
A kind of structural representation for array base palte that Fig. 3 provides for the embodiment of the present application；
The structural representation for another array base palte that Fig. 4 provides for the embodiment of the present application；
The structural representation for another array base palte that Fig. 5 provides for the embodiment of the present application；
The structural representation for another array base palte that Fig. 6 provides for the embodiment of the present application；
The structural representation for another array base palte that Fig. 7 provides for the embodiment of the present application；
The structural representation for another array base palte that Fig. 8 provides for the embodiment of the present application；
Flow signal when the array base palte first stage shown in a kind of Fig. 5 that Fig. 9 a provide for the embodiment of the present application charges
Figure；
Flow signal when the array base palte first stage shown in another Fig. 5 that Fig. 9 b provide for the embodiment of the present application charges
Figure；
Flow signal when the array base palte first stage shown in another Fig. 5 that Fig. 9 c provide for the embodiment of the present application charges
Figure；
A kind of structural representation for display panel that Figure 10 provides for the embodiment of the present application；
A kind of structural representation for display device that Figure 11 provides for the embodiment of the present application.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
In order to solve the above problems, the embodiment of the present application provides a kind of array base palte, with reference to Fig. 3, the array base palte
Including：A plurality of data lines 11,2N bars gate line 12 and multiple pixels 13.
The 2N articles of gate line 12 includes the 1st gate line to 2N gate lines, and N is positive integer.The multiple row of pixel 13
N number of pixel column is classified as, the multiple pixel 13 includes：First pixel P1 and the second pixel P2.The data wire 11 exports number
It is believed that number give the pixel 13.
Wherein, the multiple pixel 13 is into array distribution, and the bar number of the data wire 11 is equal to the columns of the pixel column,
The bearing of trend of each data wire 11 is parallel with the column direction of array.Line direction extension of each gate line 12 along array.Data wire 11
Bar number is equal to the columns of pel array, and respective data lines 11 are used to provide data-signal for the pixel of corresponding pixel column.
Also include switching element T FT (not shown), each switching element T FT in the intersection of data wire 11 and gate line 12
Grid electric connection grid polar curve 12, its source electrode electrical connection data wire 11, its drain electrical connection first pixel P1 or the second pixel P2.
When driving the first pixel P1 or the second pixel P2, the corresponding gate line 12 of its pixel provides gate drive signal to switching device
TFT, to cause switching element T FT to turn on, so that pixel electrode is applied in the data-signal provided by data wire 11.Described first
Pixel P1 is alternately distributed with the second pixel P2 on the direction of gate line 12, and is being replaced along along the bearing of trend of data wire 11
Distribution.The opposite polarity for the data-signal that the first pixel P1 and the second pixel P2 are applied in.
It should be noted that taking N=8 in Fig. 3,8 rows, the picture element array structure of 5 row are illustrate only, shows that G1-G16 is total to
16 gate lines 12 and D1-D5 totally 5 data line 11.The bar number of the gate line 12 and the bar number of the data wire 11 can
With the picture element array structure according to array base palte, it is set as any positive integer.The array arrangement mode of the multiple pixel 13 is also
Can be with as shown in figure 4, the first pixel P1 in Fig. 3 be exchanged into position with the second pixel P2.
By foregoing description, each pixel column of array base palte described in the embodiment of the present application is driven using two gate lines
It is dynamic, can be right therewith using another using a corresponding gate line 21 its first pixel of driving P1 to any pixel column
The gate line 121 answered drives its second pixel P2.So, to when array base palte is driven described in the present embodiment, in a frame,
Including first stage and second stage.In the first stage, the first pixel P1 of any odd number pixel rows is gradually driven simultaneously
With the first pixel P1 of any even pixel row, the first pixel P1 up to driving all pixels row.In second stage, by
It is secondary while drive the second pixel P2 and any even pixel row of any odd number pixel rows the second pixel P2, until driving is all
The second pixel P2 of pixel column.
Can be by the first pixel P1 of the array base palte and being driven apart for the second pixel P2 using above-mentioned type of drive
Carry out, complete all first pixel P1 driving so that after all first pixel P1 are the first polarity, then complete all second pictures
Plain P2 driving so that all second pixel P2 are the second polarity, realizes that dot inversion drives.
In the embodiment of the present application, the data-signal of all described data wire outputs is the first polarity, in the first rank
Section fills the voltage of the first polarity for all first pixel P1；In second stage, the data-signal of all described data wire outputs
It is the second polarity, is the voltage that all second pixel P2 fill the second polarity in second stage.
Wherein, first polarity and the second polarity opposite polarity each other, one of the first polarity and the second polarity are
Positive charge, another one is negative electrical charge.And by controlling the scanning sequency of pixel column, each data wire 11 can be caused to complete again
Before the charging of one polarity, without carrying out polarity of voltage upset, only primary voltage polarity need to be carried out when carrying out the charging of the second polarity
Conversion, greatly reduces the number of times of the polarity of voltage of data wire 11 conversion, so that the charging ability of data wire 11 deficiency is avoided,
The problem of power consumption is big.
In other embodiments, the second pixel of any odd-numbered line also gradually can also can be simultaneously driven in the first stage
P2 and any even number the second pixel, until the second pixel P2 of driving all pixels row.In second stage, gradually drive simultaneously
First pixel P1 of any odd-numbered line and the first pixel P1 of any even number line, until the first pixel of driving all pixels boat
P1。
Array base palte provided in an embodiment of the present invention, pixel electrode is by way of switching element T FT and gate line coupling
Including a variety of, the first pixel P1 of settable ith pixel row is coupled to 2i-1 gate lines, and the of the ith pixel row
Two pixel P2 are coupled to 2i gate lines, and i is the positive integer less than or equal to N；Also, first picture of i+1 pixel column
Plain P1 is coupled to 2i+2 gate lines, and the second pixel P2 of the i+1 pixel column is coupled to 2i+1 gate lines, i be less than
Or the positive integer equal to N-1.Now, for dot structure shown in Fig. 3, each pixel is such as schemed with the connected mode of corresponding gate line 12
Shown in 5, for dot structure shown in Fig. 4, each pixel and the connected mode of corresponding gate line 12 are as shown in Figure 6.
The the first pixel P1 that may also set up jth pixel column is coupled to 2j-1 gate lines, the of the jth pixel column
Two pixel P2 are coupled to 2j gate lines, and j is the positive integer less than or equal to N；Also, first picture of the pixel column of jth+1
Plain P1 is coupled to 2j+1 gate lines, and the second pixel P2 of the pixel column of jth+1 is coupled to 2j+2 gate lines, j be less than
Or the positive integer equal to N-1.Now, for dot structure shown in Fig. 3, each pixel is such as schemed with the connected mode of corresponding gate line 12
Shown in 7, for dot structure shown in Fig. 4, each pixel and the connected mode of corresponding gate line 12 are as shown in Figure 8.
In the present embodiment, in a frame, the first stage can have a variety of implementations with the second stage, a kind of
The mode of preferably implementing is：
It is described in the first stage, first pixels of any odd number pixel rows and any even pixel are gradually driven simultaneously
The first capable pixel, until first pixel of driving all pixels row is specifically included：In the first stage, first driving the simultaneously
First pixel in a pixel columns and a+b pixel columns, it is rear to drive simultaneously in a+1 pixel columns and a+1+b pixel columns
First pixel, with this rule, until first pixel of driving all pixels row.
Second pixel and any even pixel row for gradually driving any odd number pixel rows in second stage simultaneously
Second pixel, until second pixel of driving all pixels row is specifically included：In second stage, a pictures are first driven simultaneously
Second pixel in plain row and a+b pixel columns, the rear institute driven simultaneously in a+1 pixel columns and a+b+1 pixel columns
The second pixel is stated, with this rule, until second pixel of driving all pixels row.Wherein, a is positive integer, and b is more than 1
Odd number, and a+1+b be less than or equal to N.
By taking structure shown in Fig. 5 as an example, N=8, since the first pixel column, i.e. a=1, and b=3 is set, in the first stage：It is first
First pass through first grid polar curve G1 and the 7th gate lines G 7 drives the first pixel P1 of the first pixel column and the 4th pixel column, so that
The voltage of first polarity can be provided by respective data lines 11 for the first pixel P1 of two pixel column.Afterwards, according to first
Rule described in implementation is planted, a and a+b is stepped up 1, successively to the first pixel of the second pixel column and the 5th pixel column
P1, the first pixel P1 of the 3rd pixel column and the 6th pixel column, the first pixel P1 of the 4th pixel column and the 7th pixel column and
First pixel P1 of the 5th pixel column and the 8th pixel column is driven, when the first pixel P1 of fifth line and the 8th row has driven
Cheng Shi, due to a+b+1=8, you can stop, the first pixel P1 of now all pixel columns is scanned.In above-mentioned drive
During dynamic, the voltage of the first polarity can be provided for its first pixel P1 by respective data lines 11, until all pixels row
It is scanned finishing, and then so that all first pixel P1 voltage is the first polarity, Fig. 9 a are shown by taking Fig. 5 structures as an example
When the first polar voltages are positive voltage, first stage driving pixel is filled with the process of the first polar voltages.
In second stage, since the first pixel column, afterwards, a is stepped up 1, is advised according to the first implementation
Rule, successively to the first pixel column and the second pixel P2, the 3rd pixel column of the 4th pixel column, the second pixel column and the 5th pixel column
With the second pixel P2, the 4th pixel column and the 7th pixel column of the 6th pixel column the second pixel P2 and the 5th pixel column and
First the second pixels of pixel P1 P2 of eight pixel columns is driven, so as to by respective data lines 11 be its second pixel P2
The voltage of the second polarity is provided, so that all second pixel P2 voltages are the second polarity.
Another preferred is achieved in that：
It is described in the first stage, first pixels of any odd number pixel rows and any even pixel are gradually driven simultaneously
The first capable pixel, until first pixel of driving all pixels row is specifically included：In the first stage, a+2+b be less than or
Equal to N, first pixel in a pixel columns and a+b pixel columns is first driven simultaneously, it is rear to drive a+2 pixel columns simultaneously
With first pixel in a+2+b pixel columns, with this rule, first pixel up to driving all pixels row；Or
Person, a+2+b is more than N, and first pixel in a pixel columns and a+b pixel columns is first driven simultaneously, rear to drive a+ simultaneously
First pixel in 2 pixel columns and a+2+b-N pixel columns, with this rule, until described the of driving all pixels row
One pixel.
Second pixel and any even pixel row for gradually driving any odd number pixel rows in second stage simultaneously
Second pixel, until second pixel of driving all pixels row is specifically included：In second stage, a+2+b is less than or equal to
N, first drives second pixel in a pixel columns and a+b pixel columns simultaneously, rear to drive a+2 pixel columns and a simultaneously
Second pixel in+2+b pixel columns, with this rule, until second pixel of driving all pixels row；Or, a+2
+ b is more than N, and second pixel in a pixel columns and a+b pixel columns is first driven simultaneously, rear to drive a+2 pixels simultaneously
Second pixel in row and a+2+b-N pixel columns, with this rule, until second picture of driving all pixels row
Element；Wherein, a is positive integer, and b is odd number, and a+2 is less than N.
In this kind of implementation, equally by taking structure shown in Fig. 5 as an example, N=8 initially sets a=1, b=3, first
Stage：Now, a+2+b ＜ N, so, first by first grid polar curve G1 and the 8th gate lines G 8 drive the first pixel column with
And the 4th pixel column the first pixel P1, so as to be provided by respective data lines 11 for the first pixel P1 of two pixel column
The voltage of first polarity.Afterwards, the rule according to second of implementation, a and a+b is stepped up 2, drives the 3rd pixel
First pixel P1 of row and the first pixel P1, the 5th pixel column and the 8th pixel column of the 6th pixel column, the first pole is provided for it
Property voltage；When having driven the 5th pixel column and eight pixel columns, a and a+b is stepped up 2 again, i.e., can make a+b+2=10>8,
So then the first pixel P1 progress of driving a+2 pixel columns, i.e. the 7th pixel column and a+b+2-N, i.e. the second pixel column
Driving, so as to provide the voltage of the first polarity for its first pixel P1 by respective data lines 11, until all pixels row
It is scanned finishing, and then so that all first pixel P1 voltage is the first polarity, Fig. 9 b are shown by taking Fig. 5 structures as an example
When the first polar voltages are positive voltage, first stage driving pixel is filled with the process of the first polar voltages.
In second stage, scanned equally since the first pixel column, afterwards, a and a+b is stepped up 2, according to second
Rule described in implementation, successively to the first pixel column and the second pixel P2, the 3rd pixel column and the 6th picture of the 4th pixel column
Second pixel P2 of plain row, the second pixel P2 of the 5th pixel column and the 8th pixel column, the 7th pixel column and the second pixel column
Second pixel P2 is driven, so as to provide the voltage of the second polarity for its second pixel P2 by respective data lines 11,
So that all second pixel P2 voltages are the second polarity.
Mode is preferably implemented another, and as b=3, above-mentioned scanning sequency is successively to the first pixel column and
Four pixel columns, the 3rd pixel column and the 6th pixel column, the 5th pixel column and the 8th pixel column and the 7th pixel column and the second picture
Plain row is scanned.
B=1 can also be set in mode in another preferably implement, now, in above-mentioned second of implementation,
One stage, a+3 is less than or equal to N, first pixel in a pixel columns and a+1 pixel columns is first driven simultaneously, afterwards simultaneously
Drive first pixel in a+2 pixel columns and a+3 pixel columns；Or, a+3 is more than N, and a pixels are first driven simultaneously
It is described in first pixel in row and a+1 pixel columns, rear driving a+2 pixel columns and a+3-N pixel columns simultaneously
First pixel, with this rule, until first pixel of driving all pixels row；In second stage, a+3 is less than or equal to N,
Second pixel in a pixel columns and a+1 pixel columns is first driven simultaneously, it is rear to drive a+2 pixel columns and a+3 simultaneously
Second pixel in pixel column, or, a+3 is more than N, first drives simultaneously described in a pixel columns and a+1 pixel columns
Second pixel, it is rear to drive second pixel in a+2 pixel columns and a+3-N pixel columns simultaneously with this rule, until driving
Second pixel of dynamic all pixels row.Wherein, a is positive integer, and Fig. 9 c are shown by taking Fig. 5 structures as an example when the first polarity electricity
When pressing as positive voltage, first stage driving pixel is filled with the process of the first polar voltages.
In second of implementation, work as b=1, it is real according to second for N=8 pel array during a=1
Rule described in existing mode, it is possible to achieve the scanning from top to bottom of pixel column.In the first stage, successively to the first pixel column and second
First pixel P1 of pixel column, the 3rd pixel column and the 4th pixel column the first pixel P1, the 5th pixel column and the 6th pixel column
The first pixel P1 and the first pixel P1 of the 7th pixel column and the 8th pixel column be driven, realize all the first pixel P1
The voltage of the first polarity is filled, in second stage, is filled to the second pixel P2 of all pixels row according to same scanning sequency
The voltage of two polarity.
In the present embodiment, the driving process to pixel by taking array base palte shown in Fig. 5 as an example is described, for Fig. 6-figure
Array base palte shown in 8, it drives process identical, will not be repeated here.
In the array base palte, driven for any pixel row by two gate lines, corresponding two grid of the pixel column
Line can live apart the both sides of the pixel column, can also be located at the same side of the pixel every trade.Specifically, by taking c pixel columns as an example,
2c-1 gate lines and 2c gate lines are located at the same side of c pixel columns or are located at the both sides of the c pixel columns, c respectively
For the positive integer less than or equal to N.
In the present embodiment, the polarity and the opposite polarity of the second frame of the first frame of each pixel, to realize two frame figures
The dot inversion driving of picture.Wherein, first frame and second frame are front and rear two adjacent frames.
By foregoing description, array base palte described in the embodiment of the present application is when carrying out pixel driver, in same frame figure
As in, driving process can be divided into two stages, using the stage as all first as P1 fills the voltage of the first polarity, the
It is the voltage that all second pixel P2 fill the second polarity in two-stage, and in the first phase, the voltage pole of all data wires 11
Property always be the first polarity, be the second polarity in the voltage of all data wires 11 of second stage, in a two field picture, each data
Line 11 only needs to carry out a dipole inversion, so that the number of times of data line voltage dipole inversion is greatly reduced, so as to avoid
Data wire charging ability is not enough, the problem of power consumption is big.
With reference to Figure 10, a kind of structural representation for display panel 90 that Figure 10 provides for the embodiment of the present application, the display
Panel 90 includes：Array base palte 91.Wherein, the array base palte 91 is the array base palte described in above-described embodiment.
The display panel can be set to include：Viewing area 92 and rim area 93.The viewing area 92 is used to set institute
State array base palte 91.The rim area 93 is used for the drive circuit for setting display panel 90.
Display panel 90 described in the present embodiment is using array base palte described in above-described embodiment, when carrying out dot inversion driving,
Each data wire 11 only needs to carry out a dipole inversion, so that the number of times of data line voltage dipole inversion is greatly reduced, so that
Avoid data wire charging ability not enough, the problem of power consumption is big.
With reference to Figure 11, a kind of structural representation for display device 100 that Figure 11 provides for the embodiment of the present application, the display
Device 100 includes：Display panel 90 described in above-described embodiment.
The display device uses above-mentioned display panel 90, can realize that dot inversion drives, secondly reducing display power consumption.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (11)
1. a kind of array base palte, including：
A plurality of data lines；
2N bar gate lines, including the 1st gate line, to 2N gate lines, N is positive integer；
Multiple pixels, are arranged as N number of pixel column, and the data wire outputting data signals give the pixel, the multiple pixel bag
Include the first pixel and the second pixel；
First pixel is alternately distributed with second pixel along along gate line bearing of trend, and along data wire extension side
It is alternately distributed upwards, the opposite polarity for the data-signal that first pixel is applied in the second pixel；
Wherein, in a frame, including first stage and second stage,
In the first stage, first pixel and the first of any even pixel row of any odd number pixel rows is gradually driven simultaneously
Pixel, until first pixel of driving all pixels row；
In second stage, gradually the second pixel of any odd number pixel rows and the second picture of any even pixel row are driven simultaneously
Element, until second pixel of driving all pixels row.
2. array base palte according to claim 1, it is characterised in that
It is described in the first stage, first pixels of any odd number pixel rows and any even pixel row are gradually driven simultaneously
First pixel, until first pixel of driving all pixels row is specifically included：
In the first stage, first pixel in a pixel columns and a+b pixel columns is first driven simultaneously, it is rear to drive a simultaneously
First pixel in+1 pixel column and a+1+b pixel columns, with this rule, until described the first of driving all pixels row
Pixel；
Second pixel and the second of any even pixel row for gradually driving any odd number pixel rows in second stage simultaneously
Pixel, until second pixel of driving all pixels row is specifically included：
In second stage, second pixel in a pixel columns and a+b pixel columns is first driven simultaneously, it is rear to drive a simultaneously
Second pixel in+1 pixel column and a+b+1 pixel columns, with this rule, until described the second of driving all pixels row
Pixel；
Wherein, a is positive integer, and b is the odd number more than 1, and a+1+b is less than or equal to N.
3. array base palte according to claim 1, it is characterised in that
It is described in the first stage, first pixels of any odd number pixel rows and any even pixel row are gradually driven simultaneously
First pixel, until first pixel of driving all pixels row is specifically included：
In the first stage, a+2+b is less than or equal to N, and described first in a pixel columns and a+b pixel columns is first driven simultaneously
Pixel, rear first pixel driven simultaneously in a+2 pixel columns and a+2+b pixel columns, with this rule, until driving institute
There is first pixel of pixel column；Or, a+2+b is more than N, and the institute in a pixel columns and a+b pixel columns is first driven simultaneously
The first pixel is stated, rear first pixel driven simultaneously in a+2 pixel columns and a+2+b-N pixel columns, with this rule, directly
To first pixel for driving all pixels row；
Second pixel and the second of any even pixel row for gradually driving any odd number pixel rows in second stage simultaneously
Pixel, until second pixel of driving all pixels row is specifically included：
In second stage, a+2+b is less than or equal to N, and described second in a pixel columns and a+b pixel columns is first driven simultaneously
Pixel, rear second pixel driven simultaneously in a+2 pixel columns and a+2+b pixel columns, with this rule, until driving institute
There is second pixel of pixel column；Or, a+2+b is more than N, and the institute in a pixel columns and a+b pixel columns is first driven simultaneously
The second pixel is stated, rear second pixel driven simultaneously in a+2 pixel columns and a+2+b-N pixel columns, with this rule, directly
To second pixel for driving all pixels row；Wherein, a is positive integer, and b is odd number, and a+2 is less than N.
4. array base palte according to claim 1, it is characterised in that
In the first stage, first pixel and the first of any even pixel row of any odd number pixel rows is gradually driven simultaneously
Pixel, until first pixel of driving all pixels row is specifically included：
In the first stage, a+3 is less than or equal to N, and first picture in a pixel columns and a+1 pixel columns is first driven simultaneously
Element, rear first pixel driven simultaneously in a+2 pixel columns and a+3 pixel columns；Or, a+3 is more than N, first drives simultaneously
First pixel in dynamic a pixel columns and a+1 pixel columns, it is rear to drive a+2 pixel columns and a+3-N pixel columns simultaneously
In first pixel, with this rule, until first pixel of driving all pixels row；
In second stage, gradually the second pixel of any odd number pixel rows and the second picture of any even pixel row are driven simultaneously
Element, until second pixel of driving all pixels row is specifically included：
In second stage, a+3 is less than or equal to N, and second picture in a pixel columns and a+1 pixel columns is first driven simultaneously
Element, rear second pixel driven simultaneously in a+2 pixel columns and a+3 pixel columns, or, a+3 is more than N, first drives simultaneously
Second pixel in dynamic a pixel columns and a+1 pixel columns, it is rear to drive a+2 pixel columns and a+3-N pixel columns simultaneously
In second pixel with this rule, until second pixel of driving all pixels row；
Wherein, a is positive integer.
5. the array base palte according to any one of claim 1-3, it is characterised in that
First pixel of ith pixel row is coupled to 2i-1 gate lines, and the second pixel of the ith pixel row is coupled to
2i gate lines, i is the positive integer less than or equal to N；Also,
First pixel of i+1 pixel column is coupled to 2i+2 gate lines, the second pixel coupling of the i+1 pixel column
In 2i+1 gate lines, i is the positive integer less than or equal to N-1.
6. the array base palte according to any one of claim 1-3, it is characterised in that
First pixel of jth pixel column is coupled to 2j-1 gate lines, and the second pixel of the jth pixel column is coupled to
2j gate lines, j is the positive integer less than or equal to N；Also,
First pixel of the pixel column of jth+1 is coupled to 2j+1 gate lines, the second pixel coupling of the pixel column of jth+1
In 2j+2 gate lines, j is the positive integer less than or equal to N-1.
7. the array base palte according to any one of claim 1-3, it is characterised in that
In the first stage, the data-signal of all described data wire outputs is the first polarity；
In second stage, the data-signal of all described data wire outputs is the second polarity；
Wherein, first polarity and the second polarity opposite polarity each other.
8. the array base palte according to any one of claim 1-3, it is characterised in that 2c-1 gate lines and 2c grids
Line is located at the same side of c pixel columns or is located at the both sides of the c pixel columns respectively, and c is the positive integer less than or equal to N.
9. the array base palte according to any one of claim 1-3, it is characterised in that the first frame of each pixel
Polarity and the opposite polarity of the second frame, wherein, first frame and second frame are front and rear two adjacent frames.
10. a kind of display panel, it is characterised in that including array base palte as claimed in any one of claims 1-9 wherein.
11. a kind of display device, it is characterised in that including array base palte as claimed in any one of claims 1-9 wherein.
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| CN106094380B (en) * | 2016-08-24 | 2019-07-19 | 上海天马微电子有限公司 | Array substrate, display panel and liquid crystal display device |
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| CN101464602A (en) * | 2007-12-20 | 2009-06-24 | 乐金显示有限公司 | Liquid crystal display device and driving method thereof |
| CN101609651A (en) * | 2008-06-18 | 2009-12-23 | 北京京东方光电科技有限公司 | The driving voltage polarity reversal by liquid crystal panel method and apparatus |
| CN101726896A (en) * | 2008-10-30 | 2010-06-09 | 乐金显示有限公司 | Liquid crystal display |
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| US7602465B2 (en) * | 2002-10-31 | 2009-10-13 | Lg Display Co., Ltd. | In-plane switching mode liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101464602A (en) * | 2007-12-20 | 2009-06-24 | 乐金显示有限公司 | Liquid crystal display device and driving method thereof |
| CN101609651A (en) * | 2008-06-18 | 2009-12-23 | 北京京东方光电科技有限公司 | The driving voltage polarity reversal by liquid crystal panel method and apparatus |
| CN101726896A (en) * | 2008-10-30 | 2010-06-09 | 乐金显示有限公司 | Liquid crystal display |
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