CN104269483A - Method for preparing light-emitting diode chip with full-width reflecting mirror - Google Patents
Method for preparing light-emitting diode chip with full-width reflecting mirror Download PDFInfo
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- CN104269483A CN104269483A CN201410374193.7A CN201410374193A CN104269483A CN 104269483 A CN104269483 A CN 104269483A CN 201410374193 A CN201410374193 A CN 201410374193A CN 104269483 A CN104269483 A CN 104269483A
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- epitaxial wafer
- dicing lane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
Abstract
The invention discloses a method for preparing a light-emitting diode chip with a full-width reflecting mirror, and belongs to the technical field of semiconductors. The method comprises the steps that an epitaxial wafer is provided, wherein the epitaxial wafer comprises a sapphire substrate, a PSS and an epitaxial layer, and the PSS and the epitaxial layer are stacked on the sapphire substrate in sequence; a scribing channel is formed in the front face of the epitaxial wafer, wherein the front face of the epitaxial wafer is the surface of one side opposite to the sapphire substrate, and the depth of the scribing channel is equal to the sum of the thickness of the part, at the scribing channel, of the epitaxial layer and the thickness of the PSS; a current barrier layer, a current expanding layer and an electrode are prepared on the epitaxial wafer, and the epitaxial wafer is thinned; the back face of the epitaxial wafer is plated with an ODR in an evaporation mode, wherein the back face of the epitaxial wafer is the surface where the PSS does not grow on the sapphire substrate; laser scribing is carried out on the front face of the epitaxial wafer along the scribing channel; splinter machining is carried out on the epitaxial wafer, and then the LED chip is obtained. The method solves the problems that an epitaxial wafer is very prone to fragmenting, the epitaxial wafer is directly scrapped, and the cost allowance is brought to manufacturers.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of preparation method possessing the light-emitting diode chip for backlight unit of full-shape speculum.
Background technology
LED (Light Emitting Diode, light-emitting diode) is a kind of semiconductor electronic component that can be luminous, has the advantages that volume is little, brightness is high, energy consumption is little, is widely used in display screen, backlight and lighting field.
ODR (Omni Directional Reflector, full-shape speculum) be mainly made up of metal and silicon dioxide, titanium oxide, all high reflectance can be had to the light of any direction incidence, usually by ODR evaporation in the Sapphire Substrate of LED, increase average reflection efficiency, improve the light extraction efficiency of LED chip.
Realizing in process of the present invention, inventor finds that prior art at least exists following problem:
During owing to carrying out stealth cutting to Sapphire Substrate, laser is not by ODR, therefore generally first carry out stealth and cut scribing, in optical coating system, then complete the evaporation of ODR, then complete sliver by breaking machine and process.But according to the mode of first scribing evaporation ODR again, epitaxial wafer can be caused very easily broken, cause epitaxial wafer directly to be scrapped, for manufacturer brings cost allowance.
Summary of the invention
Epitaxial wafer can be caused very easily broken in order to solve prior art, causing epitaxial wafer directly to be scrapped, for manufacturer brings the problem of cost allowance, embodiments provide a kind of preparation method possessing the light-emitting diode chip for backlight unit of full-shape speculum.Described technical scheme is as follows:
Embodiments provide a kind of preparation method possessing the light-emitting diode chip for backlight unit of full-shape speculum, described method comprises:
One epitaxial wafer is provided, described epitaxial wafer comprises Sapphire Substrate and is sequentially laminated on graphical sapphire substrate PSS, the epitaxial loayer in described Sapphire Substrate, described epitaxial loayer comprises the N-type layer, active layer and the P-type layer that are sequentially laminated on described PSS, described epitaxial loayer offers the groove extending to described N-type layer from described P-type layer;
Dicing lane is formed in the front of described epitaxial wafer, the front of described epitaxial wafer is the surface of the side contrary with described Sapphire Substrate of described epitaxial wafer, and the degree of depth of described dicing lane equals the thickness of the described epitaxial loayer at described dicing lane place and the thickness sum of described PSS;
Described epitaxial wafer is prepared current barrier layer, current extending and electrode, and thinning described epitaxial wafer;
At the back side evaporation ODR of described epitaxial wafer, the back side of described epitaxial wafer is the surface that described Sapphire Substrate does not grow described PSS;
Laser scribing is carried out along described dicing lane from the front of described epitaxial wafer;
Sliver processing is carried out to described epitaxial wafer, obtains LED chip.
In a kind of possible implementation of the present invention, the described front at epitaxial wafer forms dicing lane, comprising:
At the front deposited silicon dioxide layer of described epitaxial wafer;
Adopt photoetching and wet etching, in described silicon dioxide layer, form dicing lane;
Using plasma etches, and forms the dicing lane in described epitaxial loayer along the dicing lane in described silicon dioxide layer;
The dicing lane in described PSS is formed along the dicing lane in described epitaxial wafer;
Remove described silicon dioxide layer.
Alternatively, the described dicing lane formed along the dicing lane in described epitaxial wafer in described PSS, comprising:
Using plasma etching or high temperature corrosion, form the dicing lane in described PSS along the dicing lane in described epitaxial wafer.
Alternatively, when described plasma etching forms the dicing lane in described PSS, upper electrode power is 2000-2500W, lower electrode power is 500-800W, etching pressure is 1.5-2.0mtorr, and etching temperature is 20-40 DEG C, and etching gas is the boron chloride of 120-150sccm.
Alternatively, when described plasma etching forms the dicing lane in described epitaxial loayer, upper electrode power is 1800-2400W, lower electrode power is 300-400W, etching pressure is 2.5-3.5mtorr, etching temperature is 0-10 DEG C, and etching gas is the boron chloride of 20-40sccm and the chlorine of 100-140sccm.
Alternatively, the thickness of described silicon dioxide layer is 700-1000nm.
Alternatively, the described silicon dioxide layer of described removal, comprising:
Adopt wet etching, remove described silicon dioxide layer.
Alternatively, described wet etching adopts buffered oxide etch agent BOE solution.
In the another kind of possible implementation of the present invention, described method also comprises:
Adopt photoetching and plasma etching, etch the groove extending to N-type layer from described P-type layer on said epitaxial layer there, etching depth is 1.3-1.6um.
In another possible implementation of the present invention, the described back side evaporation ODR at described epitaxial wafer, comprising:
After described epitaxial wafer puts into chemical vapor deposition machine, be evacuated to 5.0*E-5Pa;
The rete that Tritanium/Trititanium and silicon dioxide replaces is oxidized at the back side evaporation five of described epitaxial wafer, and evaporation one deck alumina layer on the rete replaced at five oxidation Tritanium/Trititaniums and silicon dioxide;
The rete of evaporation metal silver on described alumina layer;
Evaporation one deck alumina layer again on the rete of described argent.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is:
By first forming dicing lane in the front of epitaxial wafer, then at the back side evaporation ODR of epitaxial wafer, then laser scribing is carried out from the front of epitaxial wafer along dicing lane, first evaporation ODR scribing again, solve due to according to the first scribing mode of evaporation ODR and the epitaxial wafer that causes is very easily broken, cost allowance is directly scrapped, brought for manufacturer to epitaxial wafer problem again, greatly reduce the risk that epitaxial wafer breaks and the cost allowance brought thus, save the manufacturing cost of LED chip.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of flow chart possessing the preparation method of the LED chip of ODR that the embodiment of the present invention provides;
Fig. 2 a-Fig. 2 f is the structural representation preparing LED chip in the process of LED chip that the embodiment of the present invention provides;
Fig. 3 is the flow chart of the formation dicing lane that the embodiment of the present invention provides;
Fig. 4 a-Fig. 4 e is the structural representation of epitaxial wafer in the process of the formation dicing lane that the embodiment of the present invention provides.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Embodiment
Embodiments provide a kind of preparation method possessing the LED chip of ODR, see Fig. 1, the method comprises:
Step 100 a: epitaxial wafer is provided.
In the present embodiment, epitaxial wafer comprises Sapphire Substrate and stacks gradually PSS (Patterned Sapphire Substrate on a sapphire substrate, graphical sapphire substrate), epitaxial loayer, epitaxial loayer comprises the N-type layer be sequentially laminated on PSS, active layer and P-type layer, epitaxial loayer offers the groove extending to N-type layer from P-type layer and (refers to Fig. 2 a).
Fig. 2 a is the structural representation of the LED chip after step 100 performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 31 is N-type layer, and 32 is active layer, and 33 is P-type layer.
The composition of Sapphire Substrate comprises aluminium oxide.PSS grows dry etching mask on a sapphire substrate, by the photoetching process of standard, mask is carved figure, utilizes ICP (plasma etching) technology etching sapphire to obtain.The size of epitaxial wafer can be two inches, and also can be four inches, the application is not restricted this.
Alternatively, the method can also comprise step:
Adopt photoetching and plasma etching, epitaxial loayer etches the groove extending to N-type layer from P-type layer, is convenient to the preparation of N electrode.
Preferably, the thickness of the photoresist applied during photoetching can be 3-4um.
Alternatively, the plasma etching epitaxial loayer utilizing chlorine to be formed during plasma etching.
Particularly, etching depth can be 1.3-1.6um.Experiment shows, when etching depth is 1.3-1.6um, the photoelectric properties of chip are better, can not be subject to etching injury.
In specific implementation, first apply one deck photoresist during photoetching, then through overexposure and development, region to be etched can be out exposed.Then adopt plasma etching, just can etch photoresist and region to be etched simultaneously, thus form the groove extending to N-type layer from P-type layer.
Alternatively, the method can also comprise step:
Cleaning epitaxial wafer.
Particularly, cleaning epitaxial wafer is prior art, is not described in detail in this.
Step 101: form dicing lane in the front of epitaxial wafer.
Fig. 2 b is the structural representation of the LED chip after step 101 performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 4 is dicing lane.
In the present embodiment, the front of epitaxial wafer is the surface (representing with thick line in Fig. 2 b) of the side contrary with Sapphire Substrate of epitaxial wafer.The degree of depth of dicing lane equals the thickness of the epitaxial loayer at dicing lane place and the thickness sum of PSS.
In a kind of implementation of the present embodiment, see Fig. 3, this step 101 can comprise:
Step 101a: at the front deposited silicon dioxide layer of epitaxial wafer.
Fig. 4 a is the structural representation of the epitaxial wafer after step 101a performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 5 is silicon dioxide layer.
Alternatively, this step 101a can comprise:
Adopt PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method), at the front deposited silicon dioxide layer of epitaxial loayer.
Preferably, the thickness of silicon dioxide layer can be 700-1000nm.Due to plasma etching form the dicing lane in epitaxial loayer and PSS time; silicon dioxide layer can be lost in the same time; if the thickness of silicon dioxide layer is less than 700nm, then can be less and epitaxial loayer cannot be protected due to the thickness of silicon dioxide layer, cause plasma damage epitaxial loayer.And if the thickness of silicon dioxide layer is greater than 1000nm, then resource can be wasted.
Step 101b: adopt photoetching and wet etching, form dicing lane in silicon dioxide layer.
Fig. 4 b is the structural representation of the epitaxial wafer after step 101b performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 4 is dicing lane, and 5 is silicon dioxide layer.
Particularly, the thickness of the dicing lane in silicon dioxide layer is equal with the thickness of silicon dioxide layer.
Preferably, the thickness of the photoresist applied during photoetching can be 8-10um.
Preferably, wet etching can adopt BOE (Buffered Oxide Etchant, buffered oxide etch agent) solution.
Particularly, BOE solution comprises hydrofluoric acid and ammonium fluoride.Wherein, ammonium fluoride can play cushioning effect in corrosion process, is convenient to control corrosion rate speed.
It should be noted that, after execution step 101b, drier can be utilized to wash by water and dry.
Step 101c: using plasma etches, forms the dicing lane in epitaxial loayer along the dicing lane in silicon dioxide layer.
Fig. 4 c is the structural representation of the epitaxial wafer after step 101c performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 4 is dicing lane, and 5 is silicon dioxide layer.
Understandably; after performing step 101b; the region of the non-dicing lane of epitaxial loayer has silicon dioxide layer to protect; when therefore carrying out plasma etching; plasma can only etch the epitaxial loayer at dicing lane place; remove from the exposed epitaxial loayer out of the dicing lane in silicon dioxide layer, form the dicing lane in epitaxial loayer.
In specific implementation, this step 101c can adopt ICP machine to realize.
Particularly, the thickness of the dicing lane in epitaxial loayer is equal with the thickness of the epitaxial loayer at dicing lane place.
Alternatively, when plasma etching forms the dicing lane in epitaxial loayer, upper electrode power can be 1800-2400W, lower electrode power can be 300-400W, etching pressure can be 2.5-3.5mtorr, etching temperature can be 0-10 DEG C, and etching gas can be the boron chloride of 20-40sccm and the chlorine of 100-140sccm.
It should be noted that, etching depth can calculate according to etch rate and etch period, when etch rate one timing, can be obtained the etching depth of needs by adjustment etch period.In the present embodiment, the dicing lane in epitaxial loayer is arranged in N-type layer, and etching depth is greater than the thickness of N-type layer, can ensure that the material etch in the dicing lane in epitaxial loayer is clean.
Step 101d: form the dicing lane in PSS along the dicing lane in epitaxial loayer.
Fig. 4 d is the structural representation of the epitaxial wafer after step 101d performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 4 is dicing lane, and 5 is silicon dioxide layer.
Preferably, this step 101f can comprise:
Using plasma etches, and forms the dicing lane in PSS along the dicing lane in epitaxial loayer.
Understandably; after performing step 101b and step 101c; the region of the non-dicing lane of epitaxial loayer has silicon dioxide layer to protect; when therefore carrying out plasma etching; plasma only can etch along the dicing lane in epitaxial loayer; remove from the exposed PSS out of the dicing lane in epitaxial loayer, thus form the dicing lane in PSS.
Particularly, the thickness of the dicing lane in PSS is equal with the thickness of PSS.
Alternatively, when plasma etching forms the dicing lane in PSS, upper electrode power is 2000-2500W, and lower electrode power is 500-800W, and etching pressure is 1.5-2.0mtorr, and etching temperature is 20-40 DEG C, and etching gas is the boron chloride of 120-150sccm.Now, the speed of etching PSS is very fast, raises the efficiency.
Alternatively, this step 101f can comprise:
Adopt high temperature corrosion, form the dicing lane in PSS along the dicing lane in epitaxial loayer.
Particularly, high temperature corrosion can use the concentrated sulfuric acid and SPA in vain, and corrosion temperature can be 250-300 DEG C.
Step 101e: remove silicon dioxide layer.
Fig. 4 e is the structural representation of the epitaxial wafer after step 101e performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 4 is dicing lane.
Alternatively, this step 101e can comprise:
Adopt wet etching, remove silicon dioxide layer.
Preferably, wet etching can adopt BOE solution, very fast to the corrosion efficiency of silicon dioxide.
Particularly, BOE solution comprises hydrofluoric acid and ammonium fluoride.
Alternatively, before step 101e, the method can also comprise:
Remove residual photoresist, and bath dries.
Preferably, remove photoresist and can adopt organic solvent.
Particularly, organic solvent can comprise NMP (1-METHYLPYRROLIDONE).
It should be noted that, adopt above-mentioned implementation, the epitaxial loayer at dicing lane place and PSS can be removed clean, when making scribing, laser enters PSS smoothly, and can not damage the epitaxial loayer of dicing lane edge.
Step 102: prepare CBL (Current Blocking Layer, current barrier layer), current extending and electrode on epitaxial wafer, and thinning epitaxial wafer.
Fig. 2 c is the structural representation of the LED chip after step 102 performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 4 is dicing lane, and 6 is current barrier layer, and 7 is that current extending, 8 is for electrode.
Particularly, current extending is ITO (Indium Tin Oxide, indium tin oxide) layer.
Alternatively, the thickness of the epitaxial wafer after thinning can be 130-150um.
In specific implementation, can adopt evaporator on epitaxial wafer, prepare current extending and electrode.
Preferably, after step 102, the method can also comprise:
Epitaxial wafer is rinsed with organic solvent.
It should be noted that, need in epitaxial wafer thinning process first with paraffin, epitaxial wafer to be bonded at above ceramic disk, then just by the mode of grinding, epitaxial wafer is thinned to certain thickness, finally adopt organic solvent cleaning, to remove the paraffin on epitaxial wafer.
Step 103: at the back side evaporation ODR of epitaxial wafer.
Fig. 2 d is the structural representation of the LED chip after step 103 performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 4 is dicing lane, and 6 is current barrier layer, 7 be current extending, 8 for electrode, 9 is ODR.
In the present embodiment, the back side of epitaxial wafer is the surface (thick line in Fig. 2 d represents) that Sapphire Substrate does not grow PSS.
In specific implementation, this step 103 can adopt optical coating system to realize.
Alternatively, this step 103 can comprise:
After epitaxial wafer puts into chemical vapor deposition machine, be evacuated to 5.0*E-5Pa;
The rete that Tritanium/Trititanium and silicon dioxide replaces is oxidized at the back side evaporation five of epitaxial wafer, and evaporation one deck alumina layer on the rete replaced at five oxidation Tritanium/Trititaniums and silicon dioxide;
The rete of evaporation metal silver on alumina layer;
Evaporation one deck alumina layer again on the rete of argent.
It should be noted that, the oxide different by evaporation and argent realize ODR, can improve the luminosity of chip.
Particularly, the number of plies of rete that five oxidation Tritanium/Trititaniums and silicon dioxide replace can be 20 layers.
In specific implementation, when evaporation five is oxidized rete that Tritanium/Trititanium and silicon dioxide replaces and the alumina layer on the rete that five oxidation Tritanium/Trititaniums and silicon dioxide replace, ionogenic power can be 800-1000W.During the rete of evaporation metal silver, ion source stops working.During alumina layer on the rete of evaporation metal silver, need to reopen ion source, can by ionogenic power stability at 1000W.
It should be noted that, the effect of alumina layer prevents rete exposure oxidized in atmosphere.
Step 104: carry out laser scribing from the front of epitaxial wafer along dicing lane.
Fig. 2 e is the structural representation of the LED chip after step 104 performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 4 is dicing lane, and 6 is current barrier layer, 7 be current extending, 8 for electrode, 9 is ODR.
In specific implementation, this step 104 can adopt stealthy cutting technique to realize.Laser power can be 0.3-0.6W, and laser frequency can be 90-110KHz, and cutting-in can be 40-50um.
Step 105: sliver processing is carried out to epitaxial wafer, obtains LED chip.
Fig. 2 f is the structural representation of the LED chip after step 105 performs.Wherein, 1 is Sapphire Substrate, and 2 is PSS, and 3 is epitaxial loayer, and 4 is dicing lane, and 6 is current barrier layer, 7 be current extending, 8 for electrode, 9 is ODR.
Understandably, before step 105, after step 104, step can also be comprised: check whether the epitaxial loayer of dicing lane edge is burnt by laser.If the epitaxial loayer of dicing lane edge is burnt, then represent that these chips are all damaged, can not normal luminous, or photoelectric properties are abnormal, without the need to continuing processing.
First the embodiment of the present invention by forming dicing lane in the front of epitaxial wafer, then at the back side evaporation ODR of epitaxial wafer, then laser scribing is carried out from the front of epitaxial wafer along dicing lane, first evaporation ODR scribing again, solve due to according to first scribing again evaporation ODR mode and cause thinning after the problem that epitaxial wafer is very easily broken, cost allowance is directly scrapped, brought for manufacturer to epitaxial wafer, greatly reduce the risk that epitaxial wafer breaks and the cost allowance brought thus, save the manufacturing cost of LED chip.
One of ordinary skill in the art will appreciate that all or part of step realizing above-described embodiment can have been come by hardware, the hardware that also can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be read-only memory, disk or CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. possess a preparation method for the LED chip of full-shape speculum ODR, it is characterized in that, described method comprises:
One epitaxial wafer is provided, described epitaxial wafer comprises Sapphire Substrate and is sequentially laminated on graphical sapphire substrate PSS, the epitaxial loayer in described Sapphire Substrate, described epitaxial loayer comprises the N-type layer, active layer and the P-type layer that are sequentially laminated on described PSS, described epitaxial loayer offers the groove extending to described N-type layer from described P-type layer;
Dicing lane is formed in the front of described epitaxial wafer, the front of described epitaxial wafer is the surface of the side contrary with described Sapphire Substrate of described epitaxial wafer, and the degree of depth of described dicing lane equals the thickness of the described epitaxial loayer at described dicing lane place and the thickness sum of described PSS;
Described epitaxial wafer is prepared current barrier layer, current extending and electrode, and thinning described epitaxial wafer;
At the back side evaporation ODR of described epitaxial wafer, the back side of described epitaxial wafer is the surface that described Sapphire Substrate does not grow described PSS;
Laser scribing is carried out along described dicing lane from the front of described epitaxial wafer;
Sliver processing is carried out to described epitaxial wafer, obtains LED chip.
2. method according to claim 1, is characterized in that, the described front at epitaxial wafer forms dicing lane, comprising:
At the front deposited silicon dioxide layer of described epitaxial wafer;
Adopt photoetching and wet etching, in described silicon dioxide layer, form dicing lane;
Using plasma etches, and forms the dicing lane in described epitaxial loayer along the dicing lane in described silicon dioxide layer;
The dicing lane in described PSS is formed along the dicing lane in described epitaxial wafer;
Remove described silicon dioxide layer.
3. method according to claim 2, is characterized in that, the described dicing lane formed along the dicing lane in described epitaxial wafer in described PSS, comprising:
Using plasma etching or high temperature corrosion, form the dicing lane in described PSS along the dicing lane in described epitaxial wafer.
4. method according to claim 3, it is characterized in that, when described plasma etching forms the dicing lane in described PSS, upper electrode power is 2000-2500W, lower electrode power is 500-800W, etching pressure is 1.5-2.0mtorr, and etching temperature is 20-40 DEG C, and etching gas is the boron chloride of 120-150sccm.
5. method according to claim 2, it is characterized in that, when described plasma etching forms the dicing lane in described epitaxial loayer, upper electrode power is 1800-2400W, lower electrode power is 300-400W, etching pressure is 2.5-3.5mtorr, and etching temperature is 0-10 DEG C, and etching gas is the boron chloride of 20-40sccm and the chlorine of 100-140sccm.
6. method according to claim 2, is characterized in that, the thickness of described silicon dioxide layer is 700-1000nm.
7. method according to claim 2, is characterized in that, the described silicon dioxide layer of described removal, comprising:
Adopt wet etching, remove described silicon dioxide layer.
8. the method according to claim 2 or 7, is characterized in that, described wet etching adopts buffered oxide etch agent BOE solution.
9. method according to claim 1, is characterized in that, described method also comprises:
Adopt photoetching and plasma etching, etch the groove extending to N-type layer from described P-type layer on said epitaxial layer there, etching depth is 1.3-1.6um.
10. method according to claim 1, is characterized in that, the described back side evaporation ODR at described epitaxial wafer, comprising:
After described epitaxial wafer puts into chemical vapor deposition machine, be evacuated to 5.0*E-5Pa;
The rete that Tritanium/Trititanium and silicon dioxide replaces is oxidized at the back side evaporation five of described epitaxial wafer, and evaporation one deck alumina layer on the rete replaced at five oxidation Tritanium/Trititaniums and silicon dioxide;
The rete of evaporation metal silver on described alumina layer;
Evaporation one deck alumina layer again on the rete of described argent.
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| CN105206573A (en) * | 2015-08-20 | 2015-12-30 | 华灿光电(苏州）有限公司 | Preparation method of light emitting diode |
| CN104617193B (en) * | 2015-01-23 | 2018-02-09 | 华灿光电(苏州）有限公司 | A kind of preparation method for the light-emitting diode chip for backlight unit for possessing full-shape speculum |
| CN113644169A (en) * | 2021-08-13 | 2021-11-12 | 福建兆元光电有限公司 | Red light LED chip and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104617193A (en) * | 2015-01-23 | 2015-05-13 | 华灿光电(苏州）有限公司 | Method for preparing LED chip with omni-directional reflector |
| CN104617193B (en) * | 2015-01-23 | 2018-02-09 | 华灿光电(苏州）有限公司 | A kind of preparation method for the light-emitting diode chip for backlight unit for possessing full-shape speculum |
| CN105206573A (en) * | 2015-08-20 | 2015-12-30 | 华灿光电(苏州）有限公司 | Preparation method of light emitting diode |
| CN105206573B (en) * | 2015-08-20 | 2018-05-22 | 华灿光电(苏州）有限公司 | A kind of light-emitting diodes tube preparation method |
| CN113644169A (en) * | 2021-08-13 | 2021-11-12 | 福建兆元光电有限公司 | Red light LED chip and manufacturing method thereof |
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