CN104617193B - A kind of preparation method for the light-emitting diode chip for backlight unit for possessing full-shape speculum - Google Patents
A kind of preparation method for the light-emitting diode chip for backlight unit for possessing full-shape speculum Download PDFInfo
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- CN104617193B CN104617193B CN201510033508.6A CN201510033508A CN104617193B CN 104617193 B CN104617193 B CN 104617193B CN 201510033508 A CN201510033508 A CN 201510033508A CN 104617193 B CN104617193 B CN 104617193B
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- 229920001467 poly(styrenesulfonates) Polymers 0.000 claims abstract description 27
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Abstract
The invention discloses a kind of preparation method for the light-emitting diode chip for backlight unit for possessing full-shape speculum, belong to technical field of semiconductors.The preparation method includes：One epitaxial wafer is provided；Dicing lane is formed in the front of epitaxial wafer；Current barrier layer, current extending and electrode are prepared on epitaxial wafer, and epitaxial wafer is thinned；ODR is deposited at the back side of epitaxial wafer；From the front of epitaxial wafer laser scribing is carried out along dicing lane；Sliver processing is carried out to epitaxial wafer, obtains LED chip；Wherein, dicing lane is formed in the front of epitaxial wafer, including：Photoresist is covered in the positive first area of epitaxial wafer；Layer gold is deposited on the positive second area and photoresist of epitaxial wafer；Through hole is formed in layer gold；The dicing lane formed along the through hole in layer gold in epitaxial layer；The dicing lane formed along the dicing lane in epitaxial layer in PSS layer；Remove layer gold.The present invention solves LED chip and scrapped, and is the problem of manufacturer brings cost allowance.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of light-emitting diode chip for backlight unit for possessing full-shape speculum
Preparation method.
Background technology
LED (Light Emitting Diode, light emitting diode) is a kind of semiconductor electronic component that can be luminous, is had
Small volume, the characteristics of brightness is high, energy consumption is small, it is widely used in display screen, backlight and lighting field.ODR(Omni
Directional Reflector, full-shape speculum) mainly it is made up of metal and silica, titanium oxide, can be right
The incident light of any direction all has high reflectance, and generally ODR is vaporized in the Sapphire Substrate of LED, and increase is flat
Equal reflection efficiency, improve the light extraction efficiency of LED chip.
A kind of current preparation method for the light-emitting diode chip for backlight unit for possessing full-shape speculum includes：In the positive shape of epitaxial wafer
Into dicing lane；ODR is deposited at the back side of epitaxial wafer；From the front of epitaxial wafer laser scribing is carried out along dicing lane；To epitaxial wafer
Sliver processing is carried out, obtains LED chip.Wherein, when forming dicing lane in the front of epitaxial wafer, mask is made using silica
Layer, using plasma perform etching to epitaxial wafer, form dicing lane.
During the present invention is realized, inventor has found that prior art at least has problems with：
When etching epitaxial wafer due to using plasma, plasma simultaneously also can etching silicon dioxide and to silica
Etching speed also than very fast, if the thickness of silicon dioxide layer is smaller, easily hurt epitaxial wafer, cause the electrical of LED chip
Parameter is bad, causes LED chip to be scrapped, therefore in order to ensure etching fully, it is necessary to which one layer of very thick silica (reaches 10 μ
M), but so on the one hand very big, another aspect, too thick silica can be wasted to the production capacity for the equipment for depositing silica
Ply stress release easily makes epitaxial wafer deformation, causes epitaxial wafer to crush, and LED chip is scrapped, and cost allowance is brought for manufacturer.
The content of the invention
LED chip can be caused to scrap to solve prior art, be the problem of manufacturer brings cost allowance, the present invention is real
Apply example and provide a kind of preparation method for the light-emitting diode chip for backlight unit for possessing full-shape speculum.The technical scheme is as follows：
The embodiments of the invention provide a kind of preparation method for the light-emitting diode chip for backlight unit for possessing full-shape speculum, the side
Method includes：
An epitaxial wafer is provided, the epitaxial wafer includes Sapphire Substrate and is sequentially formed in the Sapphire Substrate
Graphical sapphire substrate PSS layer, epitaxial layer, the epitaxial layer include be sequentially laminated in the PSS layer N-type layer, have
Active layer and P-type layer, the groove that the N-type layer is extended to from the P-type layer is offered on the epitaxial layer；
Dicing lane is formed in the front of the epitaxial wafer, the front of the epitaxial wafer is the epitaxial wafer and the blue treasured
The surface of the opposite side in stone lining bottom, the depth of the dicing lane are equal to thickness and the institute of the epitaxial layer at the dicing lane
State the thickness sum of PSS layer；
Current barrier layer, current extending and electrode are prepared on the epitaxial wafer, and the epitaxial wafer is thinned；
ODR is deposited at the back side of the epitaxial wafer, the back side of the epitaxial wafer is described in the Sapphire Substrate does not grow
The surface of PSS layer；
From the front of the epitaxial wafer laser scribing is carried out along the dicing lane；
Sliver processing is carried out to the epitaxial wafer, obtains LED chip；
It is described to form dicing lane in the front of the epitaxial wafer, including：
Photoresist is covered in the positive first area of the epitaxial wafer, the first area is the area to form dicing lane
Domain；
Using electron beam evaporation, layer gold is deposited on the positive second area and the photoresist of the epitaxial wafer, institute
State the region in addition to the first area in the front that second area is the epitaxial wafer；
Using lift-off technology, through hole is formed in the layer gold；
Using plasma etches, the dicing lane formed along the through hole in the layer gold in the epitaxial layer；
The dicing lane formed along the dicing lane in the epitaxial layer in the PSS layer；
Using wet etching, the layer gold is removed；
Wherein, the thickness of the layer gold is 200-500nm.
It is described to cover photoetching in the positive first area of the epitaxial wafer in a kind of possible implementation of the present invention
Glue, including：
In the front surface coated photoresist of the epitaxial wafer；
Photoresist on the front of the epitaxial wafer is exposed and developed, removes the photoresist of the second area.
Alternatively, the thickness of the photoresist is 3.0-3.5 μm.
It is described to use lift-off technology in another possible implementation of the invention, through hole is formed in the layer gold,
Including：
Layer gold on the photoresist is peeled off using blue film；
Remove the photoresist of residual, and drying of washing by water.
Alternatively, the photoresist for removing residual, including：
The photoresist of residual is removed using organic solvent.
Preferably, the organic solvent is 1-METHYLPYRROLIDONE.
In another possible implementation of the invention, the wet etching is using chloroazotic acid and the mixed solution of water.
Alternatively, the volume ratio of the mixed solution of the chloroazotic acid and water is hydrochloric acid：Nitric acid：Water=3:1:1.
It is described in the back side of epitaxial wafer evaporation ODR in another possible implementation of the invention, including：
After the epitaxial wafer is put into chemical vapor deposition machine, 5.0*E-5Pa is evacuated to；
The oxidation Tritanium/Trititaniums and alternate film layer of silica of evaporation five at the back side of the epitaxial wafer, and in five oxidation Tritanium/Trititaniums and
One layer of alumina layer is deposited in the alternate film layer of silica；
The film layer of evaporation metal silver on the alumina layer；
One layer of alumina layer is deposited again in the film layer of the argent.
The beneficial effect that technical scheme provided in an embodiment of the present invention is brought is：
By covering photoresist in the positive first area of epitaxial wafer first, then using electron beam evaporation, in extension
Layer gold is deposited on the positive second area and photoresist of piece, then using lift-off technology, through hole is formed in layer gold, using gold
Layer makees mask, and dicing lane is formed in the front of epitaxial wafer, and because plasma does not react with gold, therefore layer gold can be very thin, no
It can cause to waste due to too thick, will not also make epitaxial wafer deformation due to stress release and cause epitaxial wafer broken and LED chip
Scrap, while can also effectively protect epitaxial wafer, avoid causing the electrical parameter of LED chip bad and cause LED chip to be scrapped,
The cost allowance for greatly reducing the risk of epitaxial wafer rupture and thus bringing, has saved the manufacturing cost of LED chip.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of flow chart of the preparation method of LED chip for possessing ODR provided in an embodiment of the present invention；
Fig. 2 a- Fig. 2 f be it is provided in an embodiment of the present invention preparation LED chip during LED chip structural representation；
Fig. 3 a- Fig. 3 f be it is provided in an embodiment of the present invention formation dicing lane during epitaxial wafer structural representation.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment
The embodiments of the invention provide a kind of preparation method for the LED chip for possessing ODR, referring to Fig. 1, this method includes：
Step 100：One epitaxial wafer is provided.
In the present embodiment, epitaxial wafer includes Sapphire Substrate and sequentially forms PSS on a sapphire substrate
(Patterned Sapphire Substrate, graphical sapphire substrate) layer, epitaxial layer, epitaxial layer include being sequentially laminated on
N-type layer, active layer and P-type layer in PSS layer, offer on epitaxial layer and the groove of N-type layer is extended to from P-type layer (refer to figure
2a)。
Fig. 2 a are the structural representation of the LED chip after step 100 performs.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 31 be N-type layer, and 32 be active layer, and 33 be P-type layer.
The composition of Sapphire Substrate includes aluminum oxide.PSS layer is to grow dry etching mask on a sapphire substrate, is used
Mask is carved figure by the photoetching process of standard, is obtained using ICP (plasma etching) technology etching sapphire.Epitaxial wafer
Size can be two inches, or four inches, the application is not restricted to this.
Alternatively, this method can also include step：
Using photoetching and plasma etching, the groove that N-type layer is extended to from P-type layer is etched on epitaxial layer, is easy to N
The preparation of electrode.
Preferably, the thickness of the photoresist coated during photoetching can be 3-4 μm.
Alternatively, the plasma etching epitaxial layer formed during plasma etching using chlorine.
Specifically, etching depth can be 1.1-1.6 μm.Experiment shows, when etching depth is 1.1-1.6 μm, chip
Photoelectric properties are preferable, will not be by etching injury.
In the specific implementation, first coat one layer of photoresist during photoetching, then by exposed and developed, region meeting to be etched
Expose and.Then plasma etching is used, it is possible to while photoresist and region to be etched are performed etching, so as to be formed
The groove of N-type layer is extended to from P-type layer.
Alternatively, this method can also include step：
Clean epitaxial wafer.
Specifically, it is prior art to clean epitaxial wafer, be will not be described in detail herein.
Step 101：Dicing lane is formed in the front of epitaxial wafer.
Fig. 2 b are the structural representation of the LED chip after step 101 performs.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 4 be dicing lane.
In the present embodiment, the front of epitaxial wafer is surface (Fig. 2 b of the side opposite with Sapphire Substrate of epitaxial wafer
It is middle to be represented with thick line).The depth of dicing lane is equal to the thickness of epitaxial layer and the thickness sum of PSS layer at dicing lane.
Specifically, include referring to Fig. 1, the step 101：
Step 101a：Photoresist is covered in the positive first area of epitaxial wafer.
Wherein, first area (being represented in Fig. 3 a with thick line) is the region for forming dicing lane.
Fig. 3 a are the structural representation of the epitaxial wafer after step 101a is performed.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 5 be photoresist.
Alternatively, step 101a can include：
In the front surface coated photoresist of epitaxial wafer；
Photoresist on the front of epitaxial wafer is exposed and developed, removes the photoresist of second area.
Wherein, second area is the region in the front of epitaxial wafer in addition to first area.
Preferably, the thickness of photoresist can be 3.0-3.5 μm.
Step 101b：Using electron beam evaporation, layer gold is deposited on the positive second area and photoresist of epitaxial wafer.
Wherein, second area is the region in the front of epitaxial wafer in addition to first area.
Fig. 3 b are the structural representation of the epitaxial wafer after step 101b is performed.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 5 be photoresist, and 6 be layer gold.
When alternatively, using electron beam evaporation, vacuum can be 3.0*10-7-5.0*10-7Torr, power can be
2000-4000W, plating rate can be 5-10A/s.
Preferably, the thickness of layer gold can be 200-500nm.
Step 101c：Using lift-off technology, through hole is formed in layer gold.
When wherein, using lift-off technology, the layer gold one of photoresist (covering is on the first region) and covering on a photoresist
Rise and stripped of, therefore through hole is on the first region.
Fig. 3 c are the structural representation of the epitaxial wafer after step 101c is performed.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 4 be dicing lane, and 6 be layer gold.
Specifically, the thickness of the through hole in layer gold and the thickness of layer gold are equal.
Alternatively, step 101c can include：
Using the layer gold on blue film stripping photoresist；
Remove the photoresist of residual, and drying of washing by water.
Preferably, the photoresist of residual is removed, can be included：
The photoresist of residual is removed using organic solvent.
Specifically, organic solvent can be 1-METHYLPYRROLIDONE (NMP).
Alternatively, bath dries, and can include：
Washed by water and dried using drier.
Step 101d：Using plasma etches, the dicing lane formed along the through hole in layer gold in epitaxial layer.
Fig. 3 d are the structural representation of the epitaxial wafer after step 101d is performed.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 4 be dicing lane, and 6 be layer gold.
It is to be appreciated that after performing step 101c, there is layer gold protection in the region of the non-dicing lane of epitaxial layer, therefore carry out etc.
During ion etching, plasma can only etch the epitaxial layer at dicing lane, remove the through hole out of layer gold expose come it is outer
Prolong layer, the dicing lane formed in epitaxial layer.
In the specific implementation, step 101d can use ICP machines to realize.
Specifically, the thickness of the dicing lane in epitaxial layer is equal with the thickness of the epitaxial layer at dicing lane.
Alternatively, when plasma etching forms the dicing lane in epitaxial layer, upper electrode power can be 1800-2400W,
Lower electrode power can be 300-400W, and etching pressure can be 2.5-3.5mtorr, and etching temperature can be 0-10 DEG C, etching
Gas can be 20-40sccm boron chloride and 100-140sccm chlorine.
It should be noted that etching depth can be calculated according to etch rate and etch period, when etch rate one
Regularly, the etching depth of needs can be obtained by adjusting etch period.In the present embodiment, the dicing lane position in epitaxial layer
In N-type layer, etching depth is more than the thickness of N-type layer, it is ensured that the material etch in dicing lane in epitaxial layer is clean.
Step 101e：The dicing lane formed along the dicing lane in epitaxial layer in PSS layer.
Fig. 3 e are the structural representation of the epitaxial wafer after step 101e is performed.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 4 be dicing lane, and 5 be layer gold.
Preferably, step 101e can include：
Using plasma etches, the dicing lane formed along the dicing lane in epitaxial layer in PSS layer.
It is to be appreciated that after performing step 101c and step 101d, there is layer gold protection in the region of the non-dicing lane of epitaxial layer,
When therefore carrying out plasma etching, plasma can only perform etching along the dicing lane in epitaxial layer, remove from epitaxial layer
The PSS layer come is exposed at interior dicing lane, so as to form the dicing lane in PSS layer.
Specifically, the thickness of the dicing lane in PSS layer and the thickness of PSS layer are equal.
Alternatively, when plasma etching forms the dicing lane in PSS layer, upper electrode power 2000-2500W, lower electricity
Pole power is 500-800W, and etching pressure is 1.5-2.0mtorr, and etching temperature is 20-40 DEG C, etching gas 120-
150sccm boron chloride.Now, it is very fast to etch the speed of PSS layer, improves efficiency.
Alternatively, step 101e can include：
Using high temperature corrosion, the dicing lane formed along the dicing lane in epitaxial layer in PSS layer.
Specifically, high temperature corrosion can use the concentrated sulfuric acid and concentrated phosphoric acid in vain, and corrosion temperature can be 250-300 DEG C.
Step 101f：Using wet etching, layer gold is removed.
Fig. 3 f are the structural representation of the epitaxial wafer after step 101f is performed.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 4 be dicing lane.
Preferably, wet etching can use the mixed solution of chloroazotic acid and water, very fast to the corrosion efficiency of gold.
Specifically, chloroazotic acid includes hydrochloric acid and nitric acid.
Alternatively, the volume ratio of the mixed solution of chloroazotic acid and water can be hydrochloric acid：Nitric acid：Water=3：1：1.
Alternatively, before step 101f, this method can also include：
Remove the photoresist of residual, and drying of washing by water.
Preferably, organic solvent can be used by removing photoresist.
Specifically, organic solvent can include NMP (1-METHYLPYRROLIDONE).
It should be noted that using above-mentioned implementation, the epitaxial layer at dicing lane and PSS layer can be removed totally,
Laser during scribing is smoothly entered PSS layer, and the epitaxial layer of dicing lane edge will not be damaged.
Step 102：CBL (Current Blocking Layer, current barrier layer), current expansion are prepared on epitaxial wafer
Layer and electrode, and epitaxial wafer is thinned.
Fig. 2 c are the structural representation of the LED chip after step 102 performs.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 4 be dicing lane, and 7 be current barrier layer, 8 is current extending, 9 is electrode.
Specifically, current extending is ITO (Indium Tin Oxide, indium tin oxide) layer.
Alternatively, the thickness of the epitaxial wafer after being thinned can be 130-150 μm.
In the specific implementation, current extending and electrode can be prepared on epitaxial wafer using evaporator.
Preferably, after step 102, this method can also include：
Epitaxial wafer is rinsed with organic solvent.
It should be noted that need that first epitaxial wafer is bonded above ceramic disk with paraffin in epitaxial wafer thinning process, then
Epitaxial wafer could be thinned to certain thickness by way of grinding, finally be cleaned using organic solvent, to remove on epitaxial wafer
Paraffin.
Step 103：ODR is deposited at the back side of epitaxial wafer.
Fig. 2 d are the structural representation of the LED chip after step 103 performs.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 4 be dicing lane, and 7 be current barrier layer, 8 is current extending, 9 is electrode, 10 be ODR.
In the present embodiment, the back side of epitaxial wafer is surface (the thick line table in Fig. 2 d that Sapphire Substrate does not grow PSS layer
Show).
In the specific implementation, the step 103 can use optical coating system to realize.
Alternatively, the step 103 can include：
After epitaxial wafer is put into chemical vapor deposition machine, 5.0*E-5Pa is evacuated to；
The oxidation Tritanium/Trititanium of evaporation five and the alternate film layer of silica at the back side of epitaxial wafer, and in five oxidation Tritanium/Trititaniums and dioxy
One layer of alumina layer is deposited in the alternate film layer of SiClx；
The film layer of evaporation metal silver on alumina layer；
One layer of alumina layer is deposited again in the film layer of argent.
It should be noted that realizing ODR by the way that different oxides and argent is deposited, the luminance of chip can be improved
Degree.
Specifically, the number of plies of five oxidation Tritanium/Trititaniums and the alternate film layer of silica can be 20 layers.
In the specific implementation, evaporation five aoxidizes Tritanium/Trititanium and the alternate film layer of silica and in five oxidation Tritanium/Trititaniums and titanium dioxide
During alumina layer in the alternate film layer of silicon, the power of ion gun can be 800-1000W.During the film layer of evaporation metal silver, from
Component stops working., can be by the power of ion gun, it is necessary to reopen ion gun during alumina layer in the film layer of evaporation metal silver
Stabilization is in 1000W.
It should be noted that the effect of alumina layer is to prevent film layer exposure to be oxidized in atmosphere.
Step 104：From the front of epitaxial wafer laser scribing is carried out along dicing lane.
Fig. 2 e are the structural representation of the LED chip after step 104 performs.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 4 be dicing lane, and 7 be current barrier layer, 8 is current extending, 9 is electrode, 10 be ODR.
In the specific implementation, the step 104 can use stealthy cutting technique to realize.Laser power can be 0.3-
0.6W, laser frequency can be 90-110KHz, and cutting-in can be 40-50 μm.
Step 105：Sliver processing is carried out to epitaxial wafer, obtains LED chip.
Fig. 2 f are the structural representation of the LED chip after step 105 performs.Wherein, 1 is Sapphire Substrate, and 2 be PSS
Layer, 3 be epitaxial layer, and 4 be dicing lane, and 7 be current barrier layer, 8 is current extending, 9 is electrode, 10 be ODR.
It is to be appreciated that before step 105 and after step 104, step can also be included：Check dicing lane edge
Whether the epitaxial layer at place is burnt by laser.If the epitaxial layer of dicing lane edge is burnt, then it represents that these chips are all damaged, no
Energy normal luminous, or photoelectric properties are abnormal, without continuing to process.
The embodiment of the present invention in the positive first area of epitaxial wafer by covering photoresist first, then using electron beam
Evaporation, is deposited layer gold on the positive second area and photoresist of epitaxial wafer, then using lift-off technology, is formed in layer gold
Through hole, mask is made using layer gold, dicing lane is formed in the front of epitaxial wafer, because plasma does not react with gold, therefore layer gold
Can be very thin, it will not cause to waste due to too thick, epitaxial wafer deformation will not be also made due to stress release and causes epitaxial wafer to break
Broken and LED chip is scrapped, while can also effectively protect epitaxial wafer, is avoided causing the electrical parameter of LED chip bad and is caused
LED chip is scrapped, and the cost allowance for greatly reducing the risk of epitaxial wafer rupture and thus bringing, has saved the system of LED chip
Cause this.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc., it should be included in the scope of the protection.
Claims (9)
1. a kind of preparation method for the LED chip for possessing full-shape speculum ODR, methods described include：
An epitaxial wafer is provided, the epitaxial wafer includes Sapphire Substrate and the figure being sequentially formed in the Sapphire Substrate
Shape Sapphire Substrate PSS layer, epitaxial layer, the epitaxial layer include N-type layer, the active layer being sequentially laminated in the PSS layer
And P-type layer, the groove that the N-type layer is extended to from the P-type layer is offered on the epitaxial layer；
Dicing lane is formed in the front of the epitaxial wafer, the front of the epitaxial wafer serves as a contrast for the epitaxial wafer and the sapphire
The surface of the opposite side in bottom, the depth of the dicing lane be equal to the thickness of the epitaxial layer at the dicing lane with it is described
The thickness sum of PSS layer；
Current barrier layer, current extending and electrode are prepared on the epitaxial wafer, and the epitaxial wafer is thinned；
ODR is deposited at the back side of the epitaxial wafer, the back side of the epitaxial wafer does not grow the PSS layer for the Sapphire Substrate
Surface；
From the front of the epitaxial wafer laser scribing is carried out along the dicing lane；
Sliver processing is carried out to the epitaxial wafer, obtains LED chip；
Characterized in that, described form dicing lane in the front of the epitaxial wafer, including：
Photoresist is covered in the positive first area of the epitaxial wafer, the first area is the region to form dicing lane；
Using electron beam evaporation, layer gold is deposited on the positive second area and the photoresist of the epitaxial wafer, described
Two regions are the region in the front of the epitaxial wafer in addition to the first area；
Using lift-off technology, through hole is formed in the layer gold；
Using plasma etches, the dicing lane formed along the through hole in the layer gold in the epitaxial layer；
The dicing lane formed along the dicing lane in the epitaxial layer in the PSS layer；
Using wet etching, the layer gold is removed；
Wherein, the thickness of the layer gold is 200-500nm.
2. preparation method according to claim 1, it is characterised in that described in the positive first area of the epitaxial wafer
Photoresist is covered, including：
In the front surface coated photoresist of the epitaxial wafer；
Photoresist on the front of the epitaxial wafer is exposed and developed, removes the photoresist of the second area.
3. preparation method according to claim 2, it is characterised in that the thickness of the photoresist is 3.0-3.5 μm.
4. preparation method according to claim 1, it is characterised in that described to use lift-off technology, the shape in the layer gold
Into through hole, including：
Layer gold on the photoresist is peeled off using blue film；
Remove the photoresist of residual, and drying of washing by water.
5. preparation method according to claim 4, it is characterised in that the photoresist for removing residual, including：
The photoresist of residual is removed using organic solvent.
6. preparation method according to claim 5, it is characterised in that the organic solvent is 1-METHYLPYRROLIDONE.
7. preparation method according to claim 1, it is characterised in that the wet etching is molten using the mixing of chloroazotic acid and water
Liquid.
8. preparation method according to claim 7, it is characterised in that the volume ratio of the mixed solution of the chloroazotic acid and water
For hydrochloric acid：Nitric acid：Water=3:1:1.
9. preparation method according to claim 1, it is characterised in that described that ODR, bag are deposited at the back side of the epitaxial wafer
Include：
After the epitaxial wafer is put into chemical vapor deposition machine, 5.0*E-5Pa is evacuated to；
The oxidation Tritanium/Trititanium of evaporation five and the alternate film layer of silica at the back side of the epitaxial wafer, and in five oxidation Tritanium/Trititaniums and dioxy
One layer of alumina layer is deposited in the alternate film layer of SiClx；
The film layer of evaporation metal silver on the alumina layer；
One layer of alumina layer is deposited again in the film layer of the argent.
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| CN101369614A (en) * | 2007-08-17 | 2009-02-18 | 刘胜 | Packaging structure and method for high power white light LED |
| CN102130253A (en) * | 2011-01-27 | 2011-07-20 | 广东银雨芯片半导体有限公司 | LED crystal plate with high light-emitting efficiency and manufacturing method thereof |
| CN104201254A (en) * | 2014-07-31 | 2014-12-10 | 华灿光电(苏州）有限公司 | Manufacturing method of light-emitting diode chip provided with omnidirectional reflector (ODR) |
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